aic7xxx.c (41514) | aic7xxx.c (41646) |
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1/* 2 * Generic driver for the aic7xxx based adaptec SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 5 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 6 * aic7880, aic7870, aic7860, and aic7850 controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. --- 22 unchanged lines hidden (view full) --- 31 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * | 1/* 2 * Generic driver for the aic7xxx based adaptec SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 5 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 6 * aic7880, aic7870, aic7860, and aic7850 controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. --- 22 unchanged lines hidden (view full) --- 31 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * |
39 * $Id: aic7xxx.c,v 1.10 1998/11/23 01:33:46 gibbs Exp $ | 39 * $Id: aic7xxx.c,v 1.11 1998/12/04 22:54:44 archie Exp $ |
40 */ 41/* 42 * A few notes on features of the driver. 43 * 44 * SCB paging takes advantage of the fact that devices stay disconnected 45 * from the bus a relatively long time and that while they're disconnected, 46 * having the SCBs for these transactions down on the host adapter is of 47 * little use. Instead of leaving this idle SCB down on the card we copy --- 80 unchanged lines hidden (view full) --- 128#include <sys/kernel.h> 129 130#ifndef AHC_TMODE_ENABLE 131#define AHC_TMODE_ENABLE 0 132#endif 133 134#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 135#define MIN(a,b) (((a) < (b)) ? (a) : (b)) | 40 */ 41/* 42 * A few notes on features of the driver. 43 * 44 * SCB paging takes advantage of the fact that devices stay disconnected 45 * from the bus a relatively long time and that while they're disconnected, 46 * having the SCBs for these transactions down on the host adapter is of 47 * little use. Instead of leaving this idle SCB down on the card we copy --- 80 unchanged lines hidden (view full) --- 128#include <sys/kernel.h> 129 130#ifndef AHC_TMODE_ENABLE 131#define AHC_TMODE_ENABLE 0 132#endif 133 134#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 135#define MIN(a,b) (((a) < (b)) ? (a) : (b)) |
136#define ALL_TARGETS (~0) 137#define ALL_LUNS (~0) | |
138#define ALL_CHANNELS '\0' | 136#define ALL_CHANNELS '\0' |
137#define ALL_TARGETS_MASK 0xFFFF |
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139 140#define SIM_IS_SCSIBUS_B(ahc, sim) \ 141 (sim == ahc->sim_b) 142#define SCB_IS_SCSIBUS_B(scb) \ 143 (((scb)->hscb->tcl & SELBUSB) != 0) 144#define SCB_TARGET(scb) \ 145 (((scb)->hscb->tcl & TID) >> 4) 146#define SCB_CHANNEL(scb) \ 147 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 148#define SCB_LUN(scb) \ 149 ((scb)->hscb->tcl & LID) 150#define SCB_TARGET_OFFSET(scb) \ 151 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 152#define SCB_TARGET_MASK(scb) \ 153 (0x01 << (SCB_TARGET_OFFSET(scb))) 154 155#define ccb_scb_ptr spriv_ptr0 156#define ccb_ahc_ptr spriv_ptr1 157 | 138 139#define SIM_IS_SCSIBUS_B(ahc, sim) \ 140 (sim == ahc->sim_b) 141#define SCB_IS_SCSIBUS_B(scb) \ 142 (((scb)->hscb->tcl & SELBUSB) != 0) 143#define SCB_TARGET(scb) \ 144 (((scb)->hscb->tcl & TID) >> 4) 145#define SCB_CHANNEL(scb) \ 146 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 147#define SCB_LUN(scb) \ 148 ((scb)->hscb->tcl & LID) 149#define SCB_TARGET_OFFSET(scb) \ 150 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 151#define SCB_TARGET_MASK(scb) \ 152 (0x01 << (SCB_TARGET_OFFSET(scb))) 153 154#define ccb_scb_ptr spriv_ptr0 155#define ccb_ahc_ptr spriv_ptr1 156 |
157typedef enum { 158 ROLE_UNKNOWN, 159 ROLE_INITIATOR, 160 ROLE_TARGET, 161} role_t; 162 |
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158struct ahc_devinfo { 159 int target_offset; 160 u_int16_t target_mask; 161 u_int8_t target; | 163struct ahc_devinfo { 164 int target_offset; 165 u_int16_t target_mask; 166 u_int8_t target; |
167 u_int8_t lun; |
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162 char channel; | 168 char channel; |
169 role_t role; /* 170 * Only guaranteed to be correct if not 171 * in the busfree state. 172 */ |
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163}; 164 165typedef enum { 166 SEARCH_COMPLETE, 167 SEARCH_COUNT, 168 SEARCH_REMOVE 169} ahc_search_action; 170 --- 28 unchanged lines hidden (view full) --- 199static struct scb * 200 ahc_get_scb(struct ahc_softc *ahc); 201static void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 202static struct scb * 203 ahc_alloc_scb(struct ahc_softc *ahc); 204static void ahc_fetch_devinfo(struct ahc_softc *ahc, 205 struct ahc_devinfo *devinfo); 206static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, | 173}; 174 175typedef enum { 176 SEARCH_COMPLETE, 177 SEARCH_COUNT, 178 SEARCH_REMOVE 179} ahc_search_action; 180 --- 28 unchanged lines hidden (view full) --- 209static struct scb * 210 ahc_get_scb(struct ahc_softc *ahc); 211static void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 212static struct scb * 213 ahc_alloc_scb(struct ahc_softc *ahc); 214static void ahc_fetch_devinfo(struct ahc_softc *ahc, 215 struct ahc_devinfo *devinfo); 216static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, |
207 u_int target, char channel); | 217 u_int target, u_int lun, char channel, 218 role_t role); |
208static u_int ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev); 209static void ahc_done(struct ahc_softc *ahc, struct scb *scbp); 210static void ahc_handle_target_cmd(struct ahc_softc *ahc, 211 struct target_cmd *cmd); 212static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 213static void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat); | 219static u_int ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev); 220static void ahc_done(struct ahc_softc *ahc, struct scb *scbp); 221static void ahc_handle_target_cmd(struct ahc_softc *ahc, 222 struct target_cmd *cmd); 223static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 224static void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat); |
214static void ahc_handle_reqinit(struct ahc_softc *ahc, 215 struct scb *scb); 216static int ahc_parse_msg(struct ahc_softc *ahc, struct scb *scb, | 225static void ahc_build_transfer_msg(struct ahc_softc *ahc, 226 struct ahc_devinfo *devinfo); 227static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 228 struct ahc_devinfo *devinfo, 229 struct scb *scb); 230static void ahc_setup_target_msgin(struct ahc_softc *ahc, 231 struct ahc_devinfo *devinfo); 232static void ahc_handle_msg_reject(struct ahc_softc *ahc, 233 struct ahc_devinfo *devinfo); 234static void ahc_clear_msg_state(struct ahc_softc *ahc); 235static void ahc_handle_message_phase(struct ahc_softc *ahc, 236 struct cam_path *path); 237static int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full); 238static int ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, |
217 struct ahc_devinfo *devinfo); 218static void ahc_handle_devreset(struct ahc_softc *ahc, int target, 219 char channel, cam_status status, 220 ac_code acode, char *message, 221 int verbose_only); 222static void ahc_loadseq(struct ahc_softc *ahc); 223static int ahc_check_patch(struct ahc_softc *ahc, 224 struct patch **start_patch, --- 16 unchanged lines hidden (view full) --- 241static int ahc_search_disc_list(struct ahc_softc *ahc, int target, 242 char channel, int lun, u_int tag); 243static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 244 u_int prev, u_int scbptr); 245static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 246static void ahc_clear_intstat(struct ahc_softc *ahc); 247static void ahc_reset_current_bus(struct ahc_softc *ahc); 248static struct ahc_syncrate * | 239 struct ahc_devinfo *devinfo); 240static void ahc_handle_devreset(struct ahc_softc *ahc, int target, 241 char channel, cam_status status, 242 ac_code acode, char *message, 243 int verbose_only); 244static void ahc_loadseq(struct ahc_softc *ahc); 245static int ahc_check_patch(struct ahc_softc *ahc, 246 struct patch **start_patch, --- 16 unchanged lines hidden (view full) --- 263static int ahc_search_disc_list(struct ahc_softc *ahc, int target, 264 char channel, int lun, u_int tag); 265static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 266 u_int prev, u_int scbptr); 267static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 268static void ahc_clear_intstat(struct ahc_softc *ahc); 269static void ahc_reset_current_bus(struct ahc_softc *ahc); 270static struct ahc_syncrate * |
271 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period); 272static struct ahc_syncrate * |
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249 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 250 u_int maxsync); 251static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, 252 u_int maxsync); 253static void ahc_validate_offset(struct ahc_softc *ahc, 254 struct ahc_syncrate *syncrate, 255 u_int *offset, int wide); | 273 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 274 u_int maxsync); 275static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, 276 u_int maxsync); 277static void ahc_validate_offset(struct ahc_softc *ahc, 278 struct ahc_syncrate *syncrate, 279 u_int *offset, int wide); |
280static void ahc_update_target_msg_request(struct ahc_softc *ahc, 281 struct ahc_devinfo *devinfo, 282 struct ahc_target_tinfo *tinfo, 283 int force); 284static int ahc_create_path(struct ahc_softc *ahc, 285 struct ahc_devinfo *devinfo, 286 struct cam_path **path); |
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256static void ahc_set_syncrate(struct ahc_softc *ahc, 257 struct ahc_devinfo *devinfo, 258 struct cam_path *path, 259 struct ahc_syncrate *syncrate, 260 u_int period, u_int offset, u_int type); 261static void ahc_set_width(struct ahc_softc *ahc, 262 struct ahc_devinfo *devinfo, 263 struct cam_path *path, u_int width, u_int type); --- 5 unchanged lines hidden (view full) --- 269static void ahc_calc_residual(struct scb *scb); 270 271static void ahc_update_pending_syncrates(struct ahc_softc *ahc); 272 273static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); 274 275static timeout_t 276 ahc_timeout; | 287static void ahc_set_syncrate(struct ahc_softc *ahc, 288 struct ahc_devinfo *devinfo, 289 struct cam_path *path, 290 struct ahc_syncrate *syncrate, 291 u_int period, u_int offset, u_int type); 292static void ahc_set_width(struct ahc_softc *ahc, 293 struct ahc_devinfo *devinfo, 294 struct cam_path *path, u_int width, u_int type); --- 5 unchanged lines hidden (view full) --- 300static void ahc_calc_residual(struct scb *scb); 301 302static void ahc_update_pending_syncrates(struct ahc_softc *ahc); 303 304static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); 305 306static timeout_t 307 ahc_timeout; |
308static __inline int sequencer_paused(struct ahc_softc *ahc); |
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277static __inline void pause_sequencer(struct ahc_softc *ahc); 278static __inline void unpause_sequencer(struct ahc_softc *ahc, 279 int unpause_always); 280static __inline void restart_sequencer(struct ahc_softc *ahc); 281static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc, 282 u_int tcl, int unbusy); 283 284static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb); --- 6 unchanged lines hidden (view full) --- 291static __inline u_int32_t 292ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 293{ 294 return (ahc->hscb_busaddr + (sizeof(struct hardware_scb) * index)); 295} 296 297#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 298 | 309static __inline void pause_sequencer(struct ahc_softc *ahc); 310static __inline void unpause_sequencer(struct ahc_softc *ahc, 311 int unpause_always); 312static __inline void restart_sequencer(struct ahc_softc *ahc); 313static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc, 314 u_int tcl, int unbusy); 315 316static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb); --- 6 unchanged lines hidden (view full) --- 323static __inline u_int32_t 324ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 325{ 326 return (ahc->hscb_busaddr + (sizeof(struct hardware_scb) * index)); 327} 328 329#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 330 |
331static __inline int 332sequencer_paused(struct ahc_softc *ahc) 333{ 334 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 335} 336 |
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299static __inline void 300pause_sequencer(struct ahc_softc *ahc) 301{ 302 ahc_outb(ahc, HCNTRL, ahc->pause); 303 304 /* 305 * Since the sequencer can disable pausing in a critical section, we 306 * must loop until it actually stops. 307 */ | 337static __inline void 338pause_sequencer(struct ahc_softc *ahc) 339{ 340 ahc_outb(ahc, HCNTRL, ahc->pause); 341 342 /* 343 * Since the sequencer can disable pausing in a critical section, we 344 * must loop until it actually stops. 345 */ |
308 while ((ahc_inb(ahc, HCNTRL) & PAUSE) == 0) | 346 while (sequencer_paused(ahc) == 0) |
309 ; 310} 311 312static __inline void 313unpause_sequencer(struct ahc_softc *ahc, int unpause_always) 314{ | 347 ; 348} 349 350static __inline void 351unpause_sequencer(struct ahc_softc *ahc, int unpause_always) 352{ |
315 if ((ahc->flags & AHC_HANDLING_REQINITS) == 0 316 && (unpause_always 317 || (ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)) | 353 if (unpause_always 354 || (ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) |
318 ahc_outb(ahc, HCNTRL, ahc->unpause); 319} 320 321/* 322 * Restart the sequencer program from address zero 323 */ 324static __inline void 325restart_sequencer(struct ahc_softc *ahc) --- 229 unchanged lines hidden (view full) --- 555 default: 556 printf(" Unsupported adapter type. Ignoring\n"); 557 return(-1); 558 } 559 return (0); 560} 561 562/* | 355 ahc_outb(ahc, HCNTRL, ahc->unpause); 356} 357 358/* 359 * Restart the sequencer program from address zero 360 */ 361static __inline void 362restart_sequencer(struct ahc_softc *ahc) --- 229 unchanged lines hidden (view full) --- 592 default: 593 printf(" Unsupported adapter type. Ignoring\n"); 594 return(-1); 595 } 596 return (0); 597} 598 599/* |
600 * Called when we have an active connection to a target on the bus, 601 * this function finds the nearest syncrate to the input period limited 602 * by the capabilities of the bus connectivity of the target. 603 */ 604static struct ahc_syncrate * 605ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 606 u_int maxsync; 607 608 if ((ahc->features & AHC_ULTRA2) != 0) { 609 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 610 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 611 maxsync = AHC_SYNCRATE_ULTRA2; 612 } else { 613 maxsync = AHC_SYNCRATE_ULTRA; 614 } 615 } else if ((ahc->features & AHC_ULTRA) != 0) { 616 maxsync = AHC_SYNCRATE_ULTRA; 617 } else { 618 maxsync = AHC_SYNCRATE_FAST; 619 } 620 return (ahc_find_syncrate(ahc, period, maxsync)); 621} 622 623/* |
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563 * Look up the valid period to SCSIRATE conversion in our table. 564 * Return the period and offset that should be sent to the target 565 * if this was the beginning of an SDTR. 566 */ 567static struct ahc_syncrate * 568ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 569{ 570 struct ahc_syncrate *syncrate; --- 77 unchanged lines hidden (view full) --- 648 maxoffset = MAX_OFFSET_16BIT; 649 else 650 maxoffset = MAX_OFFSET_8BIT; 651 } 652 *offset = MIN(*offset, maxoffset); 653} 654 655static void | 624 * Look up the valid period to SCSIRATE conversion in our table. 625 * Return the period and offset that should be sent to the target 626 * if this was the beginning of an SDTR. 627 */ 628static struct ahc_syncrate * 629ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 630{ 631 struct ahc_syncrate *syncrate; --- 77 unchanged lines hidden (view full) --- 709 maxoffset = MAX_OFFSET_16BIT; 710 else 711 maxoffset = MAX_OFFSET_8BIT; 712 } 713 *offset = MIN(*offset, maxoffset); 714} 715 716static void |
717ahc_update_target_msg_request(struct ahc_softc *ahc, 718 struct ahc_devinfo *devinfo, 719 struct ahc_target_tinfo *tinfo, 720 int force) 721{ 722 int paused; 723 u_int targ_msg_req_orig; 724 725 targ_msg_req_orig = ahc->targ_msg_req; 726 if (tinfo->current.period != tinfo->goal.period 727 || tinfo->current.width != tinfo->goal.width 728 || (force 729 && (tinfo->goal.period != 0 730 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) 731 ahc->targ_msg_req |= devinfo->target_mask; 732 else 733 ahc->targ_msg_req &= ~devinfo->target_mask; 734 735 if (ahc->targ_msg_req != targ_msg_req_orig) { 736 /* Update the message request bit for this target */ 737 paused = sequencer_paused(ahc); 738 739 if (!paused) 740 pause_sequencer(ahc); 741 742 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 743 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 744 (ahc->targ_msg_req >> 8) & 0xFF); 745 746 if (!paused) 747 unpause_sequencer(ahc, /*unpause always*/FALSE); 748 } 749} 750 751static int 752ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 753 struct cam_path **path) 754{ 755 path_id_t path_id; 756 int error; 757 758 if (devinfo->channel == 'B') 759 path_id = cam_sim_path(ahc->sim_b); 760 else 761 path_id = cam_sim_path(ahc->sim); 762 763 return (xpt_create_path(path, /*periph*/NULL, 764 path_id, devinfo->target, 765 devinfo->lun)); 766} 767 768static void |
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656ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 657 struct cam_path *path, struct ahc_syncrate *syncrate, 658 u_int period, u_int offset, u_int type) 659{ | 769ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 770 struct cam_path *path, struct ahc_syncrate *syncrate, 771 u_int period, u_int offset, u_int type) 772{ |
773 struct ahc_target_tinfo *tinfo; |
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660 u_int old_period; 661 u_int old_offset; 662 663 if (syncrate == NULL) { 664 period = 0; 665 offset = 0; 666 } 667 | 774 u_int old_period; 775 u_int old_offset; 776 777 if (syncrate == NULL) { 778 period = 0; 779 offset = 0; 780 } 781 |
668 old_period = ahc->transinfo[devinfo->target_offset].current.period; 669 old_offset = ahc->transinfo[devinfo->target_offset].current.offset; | 782 tinfo = &ahc->transinfo[devinfo->target_offset]; 783 old_period = tinfo->current.period; 784 old_offset = tinfo->current.offset; |
670 671 if ((type & AHC_TRANS_CUR) != 0 672 && (old_period != period || old_offset != offset)) { | 785 786 if ((type & AHC_TRANS_CUR) != 0 787 && (old_period != period || old_offset != offset)) { |
673 struct ccb_trans_settings neg; | 788 struct cam_path *path2; |
674 u_int scsirate; 675 | 789 u_int scsirate; 790 |
676 scsirate = ahc->transinfo[devinfo->target_offset].scsirate; | 791 scsirate = tinfo->scsirate; |
677 if ((ahc->features & AHC_ULTRA2) != 0) { 678 679 scsirate &= ~SXFR_ULTRA2; 680 681 if (syncrate != NULL) { 682 scsirate |= syncrate->sxfr_ultra2; 683 } 684 | 792 if ((ahc->features & AHC_ULTRA2) != 0) { 793 794 scsirate &= ~SXFR_ULTRA2; 795 796 if (syncrate != NULL) { 797 scsirate |= syncrate->sxfr_ultra2; 798 } 799 |
685 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) { | 800 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) |
686 ahc_outb(ahc, SCSIOFFSET, offset); | 801 ahc_outb(ahc, SCSIOFFSET, offset); |
687 } 688 ahc_outb(ahc, TARG_OFFSET + devinfo->target_offset, 689 offset); | |
690 } else { 691 692 scsirate &= ~(SXFR|SOFS); 693 /* 694 * Ensure Ultra mode is set properly for 695 * this target. 696 */ 697 ahc->ultraenb &= ~devinfo->target_mask; --- 12 unchanged lines hidden (view full) --- 710 if (ahc->ultraenb & devinfo->target_mask) 711 sxfrctl0 |= FAST20; 712 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 713 } 714 } 715 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 716 ahc_outb(ahc, SCSIRATE, scsirate); 717 | 802 } else { 803 804 scsirate &= ~(SXFR|SOFS); 805 /* 806 * Ensure Ultra mode is set properly for 807 * this target. 808 */ 809 ahc->ultraenb &= ~devinfo->target_mask; --- 12 unchanged lines hidden (view full) --- 822 if (ahc->ultraenb & devinfo->target_mask) 823 sxfrctl0 |= FAST20; 824 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 825 } 826 } 827 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 828 ahc_outb(ahc, SCSIRATE, scsirate); 829 |
718 ahc->transinfo[devinfo->target_offset].scsirate = scsirate; 719 ahc->transinfo[devinfo->target_offset].current.period = period; 720 ahc->transinfo[devinfo->target_offset].current.offset = offset; | 830 tinfo->scsirate = scsirate; 831 tinfo->current.period = period; 832 tinfo->current.offset = offset; |
721 722 /* Update the syncrates in any pending scbs */ 723 ahc_update_pending_syncrates(ahc); 724 725 /* | 833 834 /* Update the syncrates in any pending scbs */ 835 ahc_update_pending_syncrates(ahc); 836 837 /* |
726 * Tell the SCSI layer about the | 838 * If possible, tell the SCSI layer about the |
727 * new transfer parameters. 728 */ | 839 * new transfer parameters. 840 */ |
729 neg.sync_period = period; 730 neg.sync_offset = offset; 731 neg.valid = CCB_TRANS_SYNC_RATE_VALID 732 | CCB_TRANS_SYNC_OFFSET_VALID; 733 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 734 xpt_async(AC_TRANSFER_NEG, path, &neg); | 841 /* If possible, update the XPT's notion of our transfer rate */ 842 path2 = NULL; 843 if (path == NULL) { 844 int error; 845 846 error = ahc_create_path(ahc, devinfo, &path2); 847 if (error == CAM_REQ_CMP) 848 path = path2; 849 else 850 path2 = NULL; 851 } 852 853 if (path != NULL) { 854 struct ccb_trans_settings neg; 855 856 neg.sync_period = period; 857 neg.sync_offset = offset; 858 neg.valid = CCB_TRANS_SYNC_RATE_VALID 859 | CCB_TRANS_SYNC_OFFSET_VALID; 860 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 861 xpt_async(AC_TRANSFER_NEG, path, &neg); 862 } 863 864 if (path2 != NULL) 865 xpt_free_path(path2); 866 |
735 if (bootverbose) { | 867 if (bootverbose) { |
736 if (neg.sync_offset != 0) { | 868 if (offset != 0) { |
737 printf("%s: target %d synchronous at %sMHz, " 738 "offset = 0x%x\n", ahc_name(ahc), 739 devinfo->target, syncrate->rate, offset); 740 } else { 741 printf("%s: target %d using " 742 "asynchronous transfers\n", 743 ahc_name(ahc), devinfo->target); 744 } 745 } 746 } 747 748 if ((type & AHC_TRANS_GOAL) != 0) { | 869 printf("%s: target %d synchronous at %sMHz, " 870 "offset = 0x%x\n", ahc_name(ahc), 871 devinfo->target, syncrate->rate, offset); 872 } else { 873 printf("%s: target %d using " 874 "asynchronous transfers\n", 875 ahc_name(ahc), devinfo->target); 876 } 877 } 878 } 879 880 if ((type & AHC_TRANS_GOAL) != 0) { |
749 ahc->transinfo[devinfo->target_offset].goal.period = period; 750 ahc->transinfo[devinfo->target_offset].goal.offset = offset; | 881 tinfo->goal.period = period; 882 tinfo->goal.offset = offset; |
751 } 752 753 if ((type & AHC_TRANS_USER) != 0) { | 883 } 884 885 if ((type & AHC_TRANS_USER) != 0) { |
754 ahc->transinfo[devinfo->target_offset].user.period = period; 755 ahc->transinfo[devinfo->target_offset].user.offset = offset; | 886 tinfo->user.period = period; 887 tinfo->user.offset = offset; |
756 } | 888 } |
889 890 ahc_update_target_msg_request(ahc, devinfo, tinfo, /*force*/FALSE); |
|
757} 758 759static void 760ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 761 struct cam_path *path, u_int width, u_int type) 762{ | 891} 892 893static void 894ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 895 struct cam_path *path, u_int width, u_int type) 896{ |
763 u_int oldwidth; | 897 struct ahc_target_tinfo *tinfo; 898 u_int oldwidth; |
764 | 899 |
765 oldwidth = ahc->transinfo[devinfo->target_offset].current.width; | 900 tinfo = &ahc->transinfo[devinfo->target_offset]; 901 oldwidth = tinfo->current.width; |
766 767 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { | 902 903 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { |
768 struct ccb_trans_settings neg; | 904 struct cam_path *path2; |
769 u_int scsirate; 770 | 905 u_int scsirate; 906 |
771 scsirate = ahc->transinfo[devinfo->target_offset].scsirate; | 907 scsirate = tinfo->scsirate; |
772 scsirate &= ~WIDEXFER; 773 if (width == MSG_EXT_WDTR_BUS_16_BIT) 774 scsirate |= WIDEXFER; 775 | 908 scsirate &= ~WIDEXFER; 909 if (width == MSG_EXT_WDTR_BUS_16_BIT) 910 scsirate |= WIDEXFER; 911 |
776 ahc->transinfo[devinfo->target_offset].scsirate = scsirate; | 912 tinfo->scsirate = scsirate; |
777 778 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 779 ahc_outb(ahc, SCSIRATE, scsirate); 780 | 913 914 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 915 ahc_outb(ahc, SCSIRATE, scsirate); 916 |
781 ahc->transinfo[devinfo->target_offset].current.width = width; | 917 tinfo->current.width = width; |
782 | 918 |
783 /* Tell the SCSI layer about the new transfer params */ 784 neg.bus_width = width; 785 neg.valid = CCB_TRANS_BUS_WIDTH_VALID; 786 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 787 xpt_async(AC_TRANSFER_NEG, path, &neg); | 919 /* If possible, update the XPT's notion of our transfer rate */ 920 path2 = NULL; 921 if (path == NULL) { 922 int error; 923 924 error = ahc_create_path(ahc, devinfo, &path2); 925 if (error == CAM_REQ_CMP) 926 path = path2; 927 else 928 path2 = NULL; 929 } 930 931 if (path != NULL) { 932 struct ccb_trans_settings neg; 933 934 neg.bus_width = width; 935 neg.valid = CCB_TRANS_BUS_WIDTH_VALID; 936 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 937 xpt_async(AC_TRANSFER_NEG, path, &neg); 938 } 939 940 if (path2 != NULL) 941 xpt_free_path(path2); 942 |
788 if (bootverbose) { 789 printf("%s: target %d using %dbit transfers\n", 790 ahc_name(ahc), devinfo->target, | 943 if (bootverbose) { 944 printf("%s: target %d using %dbit transfers\n", 945 ahc_name(ahc), devinfo->target, |
791 8 * (0x01 << neg.bus_width)); | 946 8 * (0x01 << width)); |
792 } 793 } | 947 } 948 } |
794 if ((type & AHC_TRANS_GOAL) != 0) { 795 ahc->transinfo[devinfo->target_offset].goal.width = width; 796 } 797 if ((type & AHC_TRANS_USER) != 0) { 798 ahc->transinfo[devinfo->target_offset].user.width = width; 799 } | 949 if ((type & AHC_TRANS_GOAL) != 0) 950 tinfo->goal.width = width; 951 if ((type & AHC_TRANS_USER) != 0) 952 tinfo->user.width = width; 953 954 ahc_update_target_msg_request(ahc, devinfo, tinfo, /*force*/FALSE); |
800} 801 802/* 803 * Attach all the sub-devices we can find 804 */ 805int 806ahc_attach(struct ahc_softc *ahc) 807{ --- 115 unchanged lines hidden (view full) --- 923 ahc->path_b = path2; 924 } 925 return (count); 926} 927 928static void 929ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 930{ | 955} 956 957/* 958 * Attach all the sub-devices we can find 959 */ 960int 961ahc_attach(struct ahc_softc *ahc) 962{ --- 115 unchanged lines hidden (view full) --- 1078 ahc->path_b = path2; 1079 } 1080 return (count); 1081} 1082 1083static void 1084ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1085{ |
931 u_int saved_tcl; | 1086 u_int saved_tcl; 1087 role_t role; |
932 | 1088 |
1089 if (ahc_inb(ahc, SSTAT0) & TARGET) 1090 role = ROLE_TARGET; 1091 else 1092 role = ROLE_INITIATOR; 1093 |
|
933 saved_tcl = ahc_inb(ahc, SAVED_TCL); 934 ahc_compile_devinfo(devinfo, (saved_tcl >> 4) & 0x0f, | 1094 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1095 ahc_compile_devinfo(devinfo, (saved_tcl >> 4) & 0x0f, |
935 (saved_tcl & SELBUSB) ? 'B': 'A'); | 1096 saved_tcl & 0x3, (saved_tcl & SELBUSB) ? 'B': 'A', 1097 role); |
936} 937 938static void | 1098} 1099 1100static void |
939ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int target, char channel) | 1101ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int target, u_int lun, 1102 char channel, role_t role) |
940{ 941 devinfo->target = target; | 1103{ 1104 devinfo->target = target; |
1105 devinfo->lun = lun; |
|
942 devinfo->target_offset = target; 943 devinfo->channel = channel; | 1106 devinfo->target_offset = target; 1107 devinfo->channel = channel; |
1108 devinfo->role = role; |
|
944 if (channel == 'B') 945 devinfo->target_offset += 8; 946 devinfo->target_mask = (0x01 << devinfo->target_offset); 947} 948 949/* 950 * Catch an interrupt from the adapter 951 */ --- 78 unchanged lines hidden (view full) --- 1030 for (i = 0; error != 1 && i < num_errors; i++) 1031 error >>= 1; 1032 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1033 ahc_name(ahc), hard_error[i].errmesg, 1034 ahc_inb(ahc, SEQADDR0) | 1035 (ahc_inb(ahc, SEQADDR1) << 8)); 1036 1037 /* Tell everyone that this HBA is no longer availible */ | 1109 if (channel == 'B') 1110 devinfo->target_offset += 8; 1111 devinfo->target_mask = (0x01 << devinfo->target_offset); 1112} 1113 1114/* 1115 * Catch an interrupt from the adapter 1116 */ --- 78 unchanged lines hidden (view full) --- 1195 for (i = 0; error != 1 && i < num_errors; i++) 1196 error >>= 1; 1197 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1198 ahc_name(ahc), hard_error[i].errmesg, 1199 ahc_inb(ahc, SEQADDR0) | 1200 (ahc_inb(ahc, SEQADDR1) << 8)); 1201 1202 /* Tell everyone that this HBA is no longer availible */ |
1038 ahc_abort_scbs(ahc, ALL_TARGETS, ALL_CHANNELS, 1039 ALL_LUNS, SCB_LIST_NULL, CAM_NO_HBA); | 1203 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 1204 CAM_LUN_WILDCARD, SCB_LIST_NULL, CAM_NO_HBA); |
1040 } 1041 if (intstat & SEQINT) 1042 ahc_handle_seqint(ahc, intstat); 1043 1044 if (intstat & SCSIINT) 1045 ahc_handle_scsiint(ahc, intstat); 1046} 1047 --- 7 unchanged lines hidden (view full) --- 1055 int initiator; 1056 int target; 1057 int lun; 1058 1059 initiator = cmd->initiator_channel >> 4; 1060 target = cmd->targ_id; 1061 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 1062 | 1205 } 1206 if (intstat & SEQINT) 1207 ahc_handle_seqint(ahc, intstat); 1208 1209 if (intstat & SCSIINT) 1210 ahc_handle_scsiint(ahc, intstat); 1211} 1212 --- 7 unchanged lines hidden (view full) --- 1220 int initiator; 1221 int target; 1222 int lun; 1223 1224 initiator = cmd->initiator_channel >> 4; 1225 target = cmd->targ_id; 1226 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 1227 |
1063 xpt_print_path(ahc->path); 1064 printf("Received Target Command (%d:%d:%d)\n", 1065 initiator, target, lun); 1066 ahc_dump_targcmd(cmd); 1067 | |
1068 byte = cmd->bytes; 1069 tstate = ahc->enabled_targets[target]; 1070 lstate = NULL; 1071 if (tstate != NULL && lun < 8) 1072 lstate = tstate->enabled_luns[lun]; 1073 1074 /* 1075 * XXX Need to have a default TMODE devce that attaches to luns --- 58 unchanged lines hidden (view full) --- 1134 1135 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 1136 /* 1137 * We weren't allowed to disconnect. 1138 * We're hanging on the bus until a 1139 * continue target I/O comes in response 1140 * to this accept tio. 1141 */ | 1228 byte = cmd->bytes; 1229 tstate = ahc->enabled_targets[target]; 1230 lstate = NULL; 1231 if (tstate != NULL && lun < 8) 1232 lstate = tstate->enabled_luns[lun]; 1233 1234 /* 1235 * XXX Need to have a default TMODE devce that attaches to luns --- 58 unchanged lines hidden (view full) --- 1294 1295 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 1296 /* 1297 * We weren't allowed to disconnect. 1298 * We're hanging on the bus until a 1299 * continue target I/O comes in response 1300 * to this accept tio. 1301 */ |
1142 xpt_print_path(atio->ccb_h.path); 1143 printf("Incoming Command did not disconnect %p\n", lstate); | |
1144 ahc->pending_device = lstate; 1145 } 1146 xpt_done((union ccb*)atio); 1147} 1148 1149static void 1150ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1151{ --- 61 unchanged lines hidden (view full) --- 1213 restart_sequencer(ahc); 1214 return; 1215 } else { 1216 printf("%s:%c:%d: unknown scsi bus phase. Attempting " 1217 "to continue\n", ahc_name(ahc), devinfo.channel, 1218 devinfo.target); 1219 } 1220 break; | 1302 ahc->pending_device = lstate; 1303 } 1304 xpt_done((union ccb*)atio); 1305} 1306 1307static void 1308ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1309{ --- 61 unchanged lines hidden (view full) --- 1371 restart_sequencer(ahc); 1372 return; 1373 } else { 1374 printf("%s:%c:%d: unknown scsi bus phase. Attempting " 1375 "to continue\n", ahc_name(ahc), devinfo.channel, 1376 devinfo.target); 1377 } 1378 break; |
1221 case EXTENDED_MSG: 1222 { 1223 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 1224 ahc->msg_len = 0; 1225 ahc->msg_index = 0; 1226 1227 /* 1228 * To actually receive the message, simply turn on 1229 * REQINIT interrupts and let our interrupt handler 1230 * do the rest (REQINIT should already be true). 1231 */ 1232 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENREQINIT); 1233 ahc->flags |= AHC_HANDLING_REQINITS; 1234 return; 1235 } | |
1236 case REJECT_MSG: 1237 { | 1379 case REJECT_MSG: 1380 { |
1238 /* 1239 * What we care about here is if we had an 1240 * outstanding SDTR or WDTR message for this 1241 * target. If we did, this is a signal that 1242 * the target is refusing negotiation. 1243 */ 1244 u_int scb_index; 1245 u_int last_msg; 1246 1247 scb_index = ahc_inb(ahc, SCB_TAG); 1248 scb = ahc->scb_data->scbarray[scb_index]; 1249 1250 last_msg = ahc_inb(ahc, LAST_MSG); 1251 1252 if ((last_msg == MSG_IDENTIFYFLAG 1253 || last_msg == HOST_MSG) 1254 && (scb->flags & SCB_MSGOUT_WDTR) != 0 1255 && (scb->flags & SCB_MSGOUT_SENT) != 0) { 1256 struct ahc_target_tinfo *tinfo; 1257 1258 /* note 8bit xfers and clear flag */ 1259 printf("%s:%c:%d: refuses WIDE negotiation. Using " 1260 "8bit transfers\n", ahc_name(ahc), 1261 devinfo.channel, devinfo.target); 1262 scb->flags &= ~SCB_MSGOUT_BITS; 1263 ahc->wdtrpending &= ~devinfo.target_mask; 1264 ahc_set_width(ahc, &devinfo, scb->ccb->ccb_h.path, 1265 MSG_EXT_WDTR_BUS_8_BIT, 1266 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 1267 ahc_set_syncrate(ahc, &devinfo, scb->ccb->ccb_h.path, 1268 /*syncrate*/NULL, /*period*/0, 1269 /*offset*/0, AHC_TRANS_ACTIVE); 1270 tinfo = &ahc->transinfo[devinfo.target_offset]; 1271 if (tinfo->goal.period) { 1272 /* Start the sync negotiation */ 1273 ahc->sdtrpending |= devinfo.target_mask; 1274 scb->flags |= SCB_MSGOUT_SDTR; 1275 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1276 ahc_outb(ahc, SCSISIGO, 1277 ahc_inb(ahc, SCSISIGO) | ATNO); 1278 } 1279 } else if ((last_msg == MSG_IDENTIFYFLAG 1280 || last_msg == HOST_MSG) 1281 && (scb->flags & SCB_MSGOUT_SDTR) != 0 1282 && (scb->flags & SCB_MSGOUT_SENT) != 0) { 1283 1284 /* note asynch xfers and clear flag */ 1285 ahc_set_syncrate(ahc, &devinfo, scb->ccb->ccb_h.path, 1286 /*syncrate*/NULL, /*period*/0, 1287 /*offset*/0, 1288 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 1289 scb->flags &= ~SCB_MSGOUT_BITS; 1290 ahc->sdtrpending &= ~devinfo.target_mask; 1291 printf("%s:%c:%d: refuses synchronous negotiation. " 1292 "Using asynchronous transfers\n", 1293 ahc_name(ahc), 1294 devinfo.channel, devinfo.target); 1295 } else if ((last_msg == MSG_IDENTIFYFLAG) 1296 && (scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 1297 struct ccb_trans_settings neg; 1298 1299 printf("%s:%c:%d: refuses tagged commands. Performing " 1300 "non-tagged I/O\n", ahc_name(ahc), 1301 devinfo.channel, devinfo.target); 1302 1303 ahc->tagenable &= ~devinfo.target_mask; 1304 neg.flags = 0; 1305 neg.valid = CCB_TRANS_TQ_VALID; 1306 xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, 1307 /*priority*/1); 1308 xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg); 1309 /* 1310 * Resend the identify for this CCB as the target 1311 * may believe that the selection is invalid otherwise. 1312 */ 1313 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 1314 & ~MSG_SIMPLE_Q_TAG); 1315 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 1316 scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 1317 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 1318 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 1319 1320 /* 1321 * Requeue all tagged commands for this target 1322 * currently in our posession so they can be 1323 * converted to untagged commands. 1324 */ 1325 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 1326 SCB_CHANNEL(scb), 1327 SCB_LUN(scb), 1328 /*tag*/SCB_LIST_NULL, 1329 CAM_REQUEUE_REQ, 1330 SEARCH_COMPLETE); 1331 } else { 1332 /* 1333 * Otherwise, we ignore it. 1334 */ 1335#ifdef AHC_DEBUG 1336 if (ahc_debug & AHC_SHOWMISC) 1337 printf("%s:%c:%d: Message reject -- ignored\n", 1338 ahc_name(ahc), devinfo.channel, 1339 devinfo.target); 1340#endif 1341 break; 1342 } | 1381 ahc_handle_msg_reject(ahc, &devinfo); |
1343 break; 1344 } 1345 case BAD_STATUS: 1346 { 1347 u_int scb_index; 1348 struct hardware_scb *hscb; 1349 struct ccb_scsiio *csio; 1350 /* --- 88 unchanged lines hidden (view full) --- 1439 sg->addr = vtophys(&csio->sense_data); 1440 sg->len = csio->sense_len; 1441 1442 /* 1443 * Would be nice to preserve DISCENB here, 1444 * but due to the way we page SCBs, we can't. 1445 */ 1446 hscb->control = 0; | 1382 break; 1383 } 1384 case BAD_STATUS: 1385 { 1386 u_int scb_index; 1387 struct hardware_scb *hscb; 1388 struct ccb_scsiio *csio; 1389 /* --- 88 unchanged lines hidden (view full) --- 1478 sg->addr = vtophys(&csio->sense_data); 1479 sg->len = csio->sense_len; 1480 1481 /* 1482 * Would be nice to preserve DISCENB here, 1483 * but due to the way we page SCBs, we can't. 1484 */ 1485 hscb->control = 0; |
1486 |
|
1447 /* 1448 * This request sense could be because the 1449 * the device lost power or in some other 1450 * way has lost our transfer negotiations. 1451 * Renegotiate if appropriate. 1452 */ | 1487 /* 1488 * This request sense could be because the 1489 * the device lost power or in some other 1490 * way has lost our transfer negotiations. 1491 * Renegotiate if appropriate. 1492 */ |
1453 ahc_set_width(ahc, &devinfo, 1454 scb->ccb->ccb_h.path, 1455 MSG_EXT_WDTR_BUS_8_BIT, 1456 AHC_TRANS_CUR); 1457 ahc_set_syncrate(ahc, &devinfo, 1458 scb->ccb->ccb_h.path, 1459 /*syncrate*/NULL, /*period*/0, 1460 /*offset*/0, AHC_TRANS_CUR); 1461 scb->flags &= ~SCB_MSGOUT_BITS; | |
1462 tinfo = &ahc->transinfo[devinfo.target_offset]; | 1493 tinfo = &ahc->transinfo[devinfo.target_offset]; |
1463 if (tinfo->goal.width) { 1464 ahc->wdtrpending |= devinfo.target_mask; 1465 hscb->control |= MK_MESSAGE; 1466 scb->flags |= SCB_MSGOUT_WDTR; 1467 } else if (tinfo->goal.period) { 1468 ahc->sdtrpending |= devinfo.target_mask; 1469 hscb->control |= MK_MESSAGE; 1470 scb->flags |= SCB_MSGOUT_SDTR; 1471 } | 1494 ahc_update_target_msg_request(ahc, &devinfo, 1495 tinfo, 1496 /*force*/TRUE); |
1472 hscb->status = 0; 1473 hscb->SG_count = 1; 1474 hscb->SG_pointer = scb->ahc_dmaphys; 1475 hscb->data = sg->addr; 1476 hscb->datalen = sg->len; 1477 hscb->cmdpointer = hscb->cmdstore_busaddr; 1478 hscb->cmdlen = sizeof(*sc); 1479 scb->sg_count = hscb->SG_count; --- 26 unchanged lines hidden (view full) --- 1506 * sent yet. 1507 */ 1508 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1509 ahc_freeze_ccb(scb->ccb); 1510 break; 1511 } 1512 break; 1513 } | 1497 hscb->status = 0; 1498 hscb->SG_count = 1; 1499 hscb->SG_pointer = scb->ahc_dmaphys; 1500 hscb->data = sg->addr; 1501 hscb->datalen = sg->len; 1502 hscb->cmdpointer = hscb->cmdstore_busaddr; 1503 hscb->cmdlen = sizeof(*sc); 1504 scb->sg_count = hscb->SG_count; --- 26 unchanged lines hidden (view full) --- 1531 * sent yet. 1532 */ 1533 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1534 ahc_freeze_ccb(scb->ccb); 1535 break; 1536 } 1537 break; 1538 } |
1514 case TARGET_SYNC_CMD: 1515 { 1516 /* 1517 * We've already processed the command. If the command 1518 * is still pending, don't unpause the sequencer until 1519 * it returns. 1520 */ 1521 xpt_print_path(ahc->path); 1522 printf("Saw a target sync cmd\n"); 1523 if (ahc->pending_device != NULL) { 1524 printf(" Pending device too.\n"); 1525 return; 1526 } 1527 break; 1528 } | |
1529 case TARGET_MSG_HELP: 1530 { 1531 /* 1532 * XXX Handle BDR, Abort, Abort Tag, and transfer negotiations. 1533 */ 1534 restart_sequencer(ahc); 1535 return; 1536 } | 1539 case TARGET_MSG_HELP: 1540 { 1541 /* 1542 * XXX Handle BDR, Abort, Abort Tag, and transfer negotiations. 1543 */ 1544 restart_sequencer(ahc); 1545 return; 1546 } |
1537 case AWAITING_MSG: | 1547 case HOST_MSG_LOOP: |
1538 { | 1548 { |
1539 u_int scb_index; 1540 1541 scb_index = ahc_inb(ahc, SCB_TAG); 1542 scb = ahc->scb_data->scbarray[scb_index]; 1543 1544 /* 1545 * To facilitate adding multiple messages together, 1546 * each routine should increment the index and len 1547 * variables instead of setting them explicitly. 1548 */ 1549 ahc->msg_index = 0; 1550 ahc->msg_len = 0; 1551 | |
1552 /* | 1549 /* |
1553 * This SCB had MK_MESSAGE set in its control byte or 1554 * we have explicitly set HOST_MSG in MSG_OUT, 1555 * informing the sequencer that we want to send a 1556 * special message to this target. | 1550 * The sequencer has encountered a message phase 1551 * that requires host assistance for completion. 1552 * While handling the message phase(s), we will be 1553 * notified by the sequencer after each byte is 1554 * transfered so we can track bus phases. 1555 * 1556 * If this is the first time we've seen a HOST_MSG_LOOP, 1557 * initialize the state of the host message loop. |
1557 */ | 1558 */ |
1558 if ((scb->flags & SCB_DEVICE_RESET) == 0 1559 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG 1560 && (scb->hscb->control & TAG_ENB) != 0) { 1561 ahc->msg_buf[ahc->msg_index++] = 1562 scb->ccb->csio.tag_action; 1563 ahc->msg_buf[ahc->msg_index++] = 1564 scb->hscb->tag; 1565 ahc->msg_len += 2; 1566 } | 1559 if (ahc->msg_type == MSG_TYPE_NONE) { 1560 u_int bus_phase; |
1567 | 1561 |
1568 if (scb->flags & SCB_DEVICE_RESET) { 1569 ahc->msg_buf[ahc->msg_index++] = MSG_BUS_DEV_RESET; 1570 ahc->msg_len++; 1571 xpt_print_path(scb->ccb->ccb_h.path); 1572 printf("Bus Device Reset Message Sent\n"); 1573 } else if (scb->flags & SCB_ABORT) { 1574 if ((scb->hscb->control & TAG_ENB) != 0) 1575 ahc->msg_buf[ahc->msg_index++] = MSG_ABORT_TAG; 1576 else 1577 ahc->msg_buf[ahc->msg_index++] = MSG_ABORT; 1578 ahc->msg_len++; 1579 xpt_print_path(scb->ccb->ccb_h.path); 1580 printf("Abort Message Sent\n"); 1581 } else if (scb->flags & SCB_MSGOUT_WDTR) { 1582 struct ahc_target_tinfo *tinfo; | 1562 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1563 if (bus_phase != P_MESGIN && bus_phase != P_MESGOUT) 1564 panic("ahc_intr: HOST_MSG_LOOP bad phase 0x%x", 1565 bus_phase); |
1583 | 1566 |
1584 tinfo = &ahc->transinfo[devinfo.target_offset]; 1585 ahc_construct_wdtr(ahc, tinfo->goal.width); 1586 } else if (scb->flags & SCB_MSGOUT_SDTR) { 1587 struct ahc_target_tinfo *tinfo; 1588 u_int period; 1589 u_int maxsync; | 1567 if (devinfo.role == ROLE_INITIATOR) { 1568 struct scb *scb; 1569 u_int scb_index; |
1590 | 1570 |
1591 /* 1592 * Now that the target is actually selected, we 1593 * can further refine our sync rate based on the 1594 * output transceiver mode. 1595 */ 1596 if ((ahc->features & AHC_ULTRA2) != 0) { 1597 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1598 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1599 maxsync = AHC_SYNCRATE_ULTRA2; 1600 } else { 1601 maxsync = AHC_SYNCRATE_ULTRA; | 1571 scb_index = ahc_inb(ahc, SCB_TAG); 1572 scb = ahc->scb_data->scbarray[scb_index]; 1573 1574 if (bus_phase == P_MESGOUT) 1575 ahc_setup_initiator_msgout(ahc, 1576 &devinfo, 1577 scb); 1578 else { 1579 ahc->msg_type = 1580 MSG_TYPE_INITIATOR_MSGIN; 1581 ahc->msgin_index = 0; |
1602 } | 1582 } |
1603 } else if ((ahc->features & AHC_ULTRA) != 0) { 1604 maxsync = AHC_SYNCRATE_ULTRA; | |
1605 } else { | 1583 } else { |
1606 maxsync = AHC_SYNCRATE_FAST; | 1584 if (bus_phase == P_MESGOUT) { 1585 ahc->msg_type = 1586 MSG_TYPE_TARGET_MSGOUT; 1587 ahc->msgin_index = 0; 1588 } else 1589 /* XXX Ever executed??? */ 1590 ahc_setup_target_msgin(ahc, &devinfo); |
1607 } | 1591 } |
1608 tinfo = &ahc->transinfo[devinfo.target_offset]; 1609 period = tinfo->goal.period; 1610 ahc_find_syncrate(ahc, &period, maxsync); 1611 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 1612 } else { 1613 printf("ahc_intr: AWAITING_MSG for an SCB that " 1614 "does not have a waiting message"); 1615 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 1616 "SCB flags = %x", scb_index, scb->hscb->control, 1617 ahc_inb(ahc, MSG_OUT), scb->flags); | |
1618 } 1619 | 1592 } 1593 |
1620 /* 1621 * Record the fact that we attempted to send a message. 1622 */ 1623 scb->flags |= SCB_MSGOUT_SENT; 1624 1625 /* 1626 * To actually send the message, simply turn on 1627 * REQINIT interrupts and let our interrupt handler 1628 * do the rest (REQINIT should already be true). 1629 */ 1630 ahc->msg_index = 0; 1631 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1632 ahc->flags |= AHC_HANDLING_REQINITS; 1633 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENREQINIT); 1634 1635 return; | 1594 /* Pass a NULL path so that handlers generate their own */ 1595 ahc_handle_message_phase(ahc, /*path*/NULL); 1596 break; |
1636 } 1637 case DATA_OVERRUN: 1638 { 1639 /* 1640 * When the sequencer detects an overrun, it 1641 * places the controller in "BITBUCKET" mode 1642 * and allows the target to complete its transfer. 1643 * Unfortunately, none of the counters get updated --- 176 unchanged lines hidden (view full) --- 1820 tag = scb->hscb->tag; 1821 else 1822 tag = SCB_LIST_NULL; 1823 ahc_abort_scbs(ahc, target, channel, 1824 SCB_LUN(scb), tag, 1825 CAM_UNEXP_BUSFREE); 1826 } else { 1827 ahc_abort_scbs(ahc, target, channel, | 1597 } 1598 case DATA_OVERRUN: 1599 { 1600 /* 1601 * When the sequencer detects an overrun, it 1602 * places the controller in "BITBUCKET" mode 1603 * and allows the target to complete its transfer. 1604 * Unfortunately, none of the counters get updated --- 176 unchanged lines hidden (view full) --- 1781 tag = scb->hscb->tag; 1782 else 1783 tag = SCB_LIST_NULL; 1784 ahc_abort_scbs(ahc, target, channel, 1785 SCB_LUN(scb), tag, 1786 CAM_UNEXP_BUSFREE); 1787 } else { 1788 ahc_abort_scbs(ahc, target, channel, |
1828 ALL_LUNS, SCB_LIST_NULL, | 1789 CAM_LUN_WILDCARD, SCB_LIST_NULL, |
1829 CAM_UNEXP_BUSFREE); 1830 printf("%s: ", ahc_name(ahc)); 1831 } 1832 printf("Unexpected busfree. LASTPHASE == 0x%x\n" 1833 "SEQADDR == 0x%x\n", 1834 lastphase, ahc_inb(ahc, SEQADDR0) 1835 | (ahc_inb(ahc, SEQADDR1) << 8)); 1836 } 1837 ahc_outb(ahc, MSG_OUT, MSG_NOOP); | 1790 CAM_UNEXP_BUSFREE); 1791 printf("%s: ", ahc_name(ahc)); 1792 } 1793 printf("Unexpected busfree. LASTPHASE == 0x%x\n" 1794 "SEQADDR == 0x%x\n", 1795 lastphase, ahc_inb(ahc, SEQADDR0) 1796 | (ahc_inb(ahc, SEQADDR1) << 8)); 1797 } 1798 ahc_outb(ahc, MSG_OUT, MSG_NOOP); |
1838 ahc_outb(ahc, SIMODE1, 1839 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); 1840 ahc->flags &= ~AHC_HANDLING_REQINITS; | 1799 ahc_clear_msg_state(ahc); 1800 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); |
1841 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1842 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1843 restart_sequencer(ahc); 1844 } else if ((status & SELTO) != 0) { 1845 u_int scbptr; 1846 1847 scbptr = ahc_inb(ahc, WAITING_SCBH); 1848 ahc_outb(ahc, SCBPTR, scbptr); --- 19 unchanged lines hidden (view full) --- 1868 ahc_handle_devreset(ahc, SCB_TARGET(scb), 1869 SCB_CHANNEL(scb), CAM_SEL_TIMEOUT, 1870 /*ac_code*/0, "Selection Timeout", 1871 /*verbose_only*/TRUE); 1872 } 1873 /* Stop the selection */ 1874 ahc_outb(ahc, SCSISEQ, 0); 1875 | 1801 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1802 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1803 restart_sequencer(ahc); 1804 } else if ((status & SELTO) != 0) { 1805 u_int scbptr; 1806 1807 scbptr = ahc_inb(ahc, WAITING_SCBH); 1808 ahc_outb(ahc, SCBPTR, scbptr); --- 19 unchanged lines hidden (view full) --- 1828 ahc_handle_devreset(ahc, SCB_TARGET(scb), 1829 SCB_CHANNEL(scb), CAM_SEL_TIMEOUT, 1830 /*ac_code*/0, "Selection Timeout", 1831 /*verbose_only*/TRUE); 1832 } 1833 /* Stop the selection */ 1834 ahc_outb(ahc, SCSISEQ, 0); 1835 |
1876 ahc_outb(ahc, SIMODE1, 1877 ahc_inb(ahc, SIMODE1) & ~ENREQINIT); 1878 ahc->flags &= ~AHC_HANDLING_REQINITS; | 1836 ahc_clear_msg_state(ahc); |
1879 1880 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE); 1881 1882 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1883 1884 restart_sequencer(ahc); 1885 } else if (scb == NULL) { 1886 printf("%s: ahc_intr - referenced scb not " --- 54 unchanged lines hidden (view full) --- 1941 /* 1942 * We've set the hardware to assert ATN if we 1943 * get a parity error on "in" phases, so all we 1944 * need to do is stuff the message buffer with 1945 * the appropriate message. "In" phases have set 1946 * mesg_out to something other than MSG_NOP. 1947 */ 1948 if (mesg_out != MSG_NOOP) { | 1837 1838 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE); 1839 1840 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1841 1842 restart_sequencer(ahc); 1843 } else if (scb == NULL) { 1844 printf("%s: ahc_intr - referenced scb not " --- 54 unchanged lines hidden (view full) --- 1899 /* 1900 * We've set the hardware to assert ATN if we 1901 * get a parity error on "in" phases, so all we 1902 * need to do is stuff the message buffer with 1903 * the appropriate message. "In" phases have set 1904 * mesg_out to something other than MSG_NOP. 1905 */ 1906 if (mesg_out != MSG_NOOP) { |
1949 ahc_outb(ahc, MSG_OUT, mesg_out); | 1907 if (ahc->msg_type != MSG_TYPE_NONE) 1908 ahc->send_msg_perror = TRUE; 1909 else 1910 ahc_outb(ahc, MSG_OUT, mesg_out); |
1950 } 1951 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1952 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1953 unpause_sequencer(ahc, /*unpause_always*/TRUE); | 1911 } 1912 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1913 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1914 unpause_sequencer(ahc, /*unpause_always*/TRUE); |
1954 } else if ((status & REQINIT) != 0 1955 && (ahc->flags & AHC_HANDLING_REQINITS) != 0) { 1956 ahc_handle_reqinit(ahc, scb); | |
1957 } else { 1958 xpt_print_path(scb->ccb->ccb_h.path); 1959 printf("Unknown SCSIINT. Status = 0x%x\n", status); 1960 ahc_outb(ahc, CLRSINT1, status); 1961 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1962 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1963 } 1964} 1965 1966static void | 1915 } else { 1916 xpt_print_path(scb->ccb->ccb_h.path); 1917 printf("Unknown SCSIINT. Status = 0x%x\n", status); 1918 ahc_outb(ahc, CLRSINT1, status); 1919 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1920 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1921 } 1922} 1923 1924static void |
1967ahc_handle_reqinit(struct ahc_softc *ahc, struct scb *scb) | 1925ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1926{ 1927 /* 1928 * We need to initiate transfer negotiations. 1929 * If our current and goal settings are identical, 1930 * we want to renegotiate due to a check condition. 1931 */ 1932 struct ahc_target_tinfo *tinfo; 1933 int dowide; 1934 int dosync; 1935 1936 tinfo = &ahc->transinfo[devinfo->target_offset]; 1937 dowide = tinfo->current.width != tinfo->goal.width; 1938 dosync = tinfo->current.period != tinfo->goal.period; 1939 1940 if (!dowide && !dosync) { 1941 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 1942 dosync = tinfo->goal.period != 0; 1943 } 1944 1945 if (dowide) 1946 ahc_construct_wdtr(ahc, tinfo->goal.width); 1947 else if (dosync) { 1948 u_int period; 1949 1950 period = tinfo->goal.period; 1951 ahc_devlimited_syncrate(ahc, &period); 1952 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 1953 } else { 1954 panic("ahc_intr: AWAITING_MSG for negotiation, " 1955 "but no negotiation needed\n"); 1956 } 1957} 1958 1959static void 1960ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1961 struct scb *scb) 1962{ 1963 /* 1964 * To facilitate adding multiple messages together, 1965 * each routine should increment the index and len 1966 * variables instead of setting them explicitly. 1967 */ 1968 ahc->msgout_index = 0; 1969 ahc->msgout_len = 0; 1970 1971 if ((scb->flags & SCB_DEVICE_RESET) == 0 1972 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 1973 u_int identify_msg; 1974 1975 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 1976 if ((scb->hscb->control & DISCENB) != 0) 1977 identify_msg |= MSG_IDENTIFY_DISCFLAG; 1978 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 1979 ahc->msgout_len++; 1980 1981 if ((scb->hscb->control & TAG_ENB) != 0) { 1982 ahc->msgout_buf[ahc->msgout_index++] = 1983 scb->ccb->csio.tag_action; 1984 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 1985 ahc->msgout_len += 2; 1986 } 1987 } 1988 1989 if (scb->flags & SCB_DEVICE_RESET) { 1990 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 1991 ahc->msgout_len++; 1992 xpt_print_path(scb->ccb->ccb_h.path); 1993 printf("Bus Device Reset Message Sent\n"); 1994 } else if (scb->flags & SCB_ABORT) { 1995 if ((scb->hscb->control & TAG_ENB) != 0) 1996 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 1997 else 1998 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 1999 ahc->msgout_len++; 2000 xpt_print_path(scb->ccb->ccb_h.path); 2001 printf("Abort Message Sent\n"); 2002 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2003 ahc_build_transfer_msg(ahc, devinfo); 2004 } else { 2005 printf("ahc_intr: AWAITING_MSG for an SCB that " 2006 "does not have a waiting message"); 2007 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2008 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2009 ahc_inb(ahc, MSG_OUT), scb->flags); 2010 } 2011 2012 /* 2013 * Clear the MK_MESSAGE flag from the SCB so we aren't 2014 * asked to send this message again. 2015 */ 2016 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2017 ahc->msgout_index = 0; 2018 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2019} 2020 2021static void 2022ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2023{ 2024 /* 2025 * To facilitate adding multiple messages together, 2026 * each routine should increment the index and len 2027 * variables instead of setting them explicitly. 2028 */ 2029 ahc->msgout_index = 0; 2030 ahc->msgout_len = 0; 2031 2032 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2033 ahc_build_transfer_msg(ahc, devinfo); 2034 else 2035 panic("ahc_intr: AWAITING target message with no message"); 2036 2037 ahc->msgout_index = 0; 2038 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2039} 2040 2041static void 2042ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2043{ 2044 /* 2045 * What we care about here is if we had an 2046 * outstanding SDTR or WDTR message for this 2047 * target. If we did, this is a signal that 2048 * the target is refusing negotiation. 2049 */ 2050 struct scb *scb; 2051 u_int scb_index; 2052 u_int last_msg; 2053 2054 scb_index = ahc_inb(ahc, SCB_TAG); 2055 scb = ahc->scb_data->scbarray[scb_index]; 2056 2057 /* Might be necessary */ 2058 last_msg = ahc_inb(ahc, LAST_MSG); 2059 2060 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2061 struct ahc_target_tinfo *tinfo; 2062 2063 /* note 8bit xfers and clear flag */ 2064 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2065 "8bit transfers\n", ahc_name(ahc), 2066 devinfo->channel, devinfo->target); 2067 ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path, 2068 MSG_EXT_WDTR_BUS_8_BIT, 2069 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2070 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2071 /*syncrate*/NULL, /*period*/0, 2072 /*offset*/0, AHC_TRANS_ACTIVE); 2073 tinfo = &ahc->transinfo[devinfo->target_offset]; 2074 if (tinfo->goal.period) { 2075 u_int period; 2076 2077 /* Start the sync negotiation */ 2078 period = tinfo->goal.period; 2079 ahc_devlimited_syncrate(ahc, &period); 2080 ahc->msgout_index = 0; 2081 ahc->msgout_len = 0; 2082 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2083 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2084 } 2085 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2086 /* note asynch xfers and clear flag */ 2087 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2088 /*syncrate*/NULL, /*period*/0, 2089 /*offset*/0, 2090 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2091 printf("%s:%c:%d: refuses synchronous negotiation. " 2092 "Using asynchronous transfers\n", 2093 ahc_name(ahc), 2094 devinfo->channel, devinfo->target); 2095 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2096 struct ccb_trans_settings neg; 2097 2098 printf("%s:%c:%d: refuses tagged commands. Performing " 2099 "non-tagged I/O\n", ahc_name(ahc), 2100 devinfo->channel, devinfo->target); 2101 2102 ahc->tagenable &= ~devinfo->target_mask; 2103 neg.flags = 0; 2104 neg.valid = CCB_TRANS_TQ_VALID; 2105 xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, /*priority*/1); 2106 xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg); 2107 2108 /* 2109 * Resend the identify for this CCB as the target 2110 * may believe that the selection is invalid otherwise. 2111 */ 2112 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2113 & ~MSG_SIMPLE_Q_TAG); 2114 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2115 scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 2116 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2117 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2118 2119 /* 2120 * Requeue all tagged commands for this target 2121 * currently in our posession so they can be 2122 * converted to untagged commands. 2123 */ 2124 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2125 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2126 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 2127 } else { 2128 /* 2129 * Otherwise, we ignore it. 2130 */ 2131 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2132 ahc_name(ahc), devinfo->channel, devinfo->target, 2133 last_msg); 2134 } 2135} 2136 2137static void 2138ahc_clear_msg_state(struct ahc_softc *ahc) 2139{ 2140 ahc->msgout_len = 0; 2141 ahc->msgin_index = 0; 2142 ahc->msg_type = MSG_TYPE_NONE; 2143} 2144 2145static void 2146ahc_handle_message_phase(struct ahc_softc *ahc, struct cam_path *path) |
1968{ 1969 struct ahc_devinfo devinfo; | 2147{ 2148 struct ahc_devinfo devinfo; |
1970 u_int simode1; | 2149 u_int bus_phase; 2150 int end_session; |
1971 1972 ahc_fetch_devinfo(ahc, &devinfo); 1973 | 2151 2152 ahc_fetch_devinfo(ahc, &devinfo); 2153 |
2154 2155 end_session = FALSE; 2156 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2157 2158reswitch: |
|
1974 switch (ahc->msg_type) { 1975 case MSG_TYPE_INITIATOR_MSGOUT: 1976 { | 2159 switch (ahc->msg_type) { 2160 case MSG_TYPE_INITIATOR_MSGOUT: 2161 { |
1977 int lastbyte; 1978 int phasemis; 1979 u_int bus_phase; | 2162 int lastbyte; 2163 int phasemis; 2164 int msgdone; |
1980 | 2165 |
1981 if (ahc->msg_len == 0) | 2166 if (ahc->msgout_len == 0) |
1982 panic("REQINIT interrupt with no active message"); 1983 | 2167 panic("REQINIT interrupt with no active message"); 2168 |
1984 lastbyte = (ahc->msg_index == ahc->msg_len - 1); 1985 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; | |
1986 phasemis = bus_phase != P_MESGOUT; | 2169 phasemis = bus_phase != P_MESGOUT; |
2170 if (phasemis) { 2171 if (bus_phase == P_MESGIN) { 2172 u_int scsisigo; |
|
1987 | 2173 |
1988 if (lastbyte || phasemis) { 1989 /* Time to end our message session */ 1990 ahc->msg_len = 0; 1991 ahc->msg_type = MSG_TYPE_NONE; 1992 simode1 = ahc_inb(ahc, SIMODE1) & ~ENREQINIT; 1993 ahc_outb(ahc, SIMODE1, simode1); 1994 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1995 ahc->flags &= ~AHC_HANDLING_REQINITS; 1996 1997 if (phasemis == 0) { 1998 ahc_outb(ahc, SINDEX, 1999 ahc->msg_buf[ahc->msg_index]); 2000 ahc_outb(ahc, RETURN_1, 0); 2001 } else { 2002 ahc_outb(ahc, RETURN_1, MSGOUT_PHASEMIS); | 2174 /* 2175 * Change gears and see if 2176 * this messages is of interest to 2177 * us or should be passed back to 2178 * the sequencer. 2179 */ 2180 ahc->send_msg_perror = FALSE; 2181 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2182 ahc->msgin_index = 0; 2183 goto reswitch; |
2003 } | 2184 } |
2185 end_session = TRUE; 2186 break; 2187 } |
|
2004 | 2188 |
2005 unpause_sequencer(ahc, /* unpause_always */TRUE); 2006 } else { | 2189 if (ahc->send_msg_perror) { 2190 ahc_outb(ahc, CLRSINT1, CLRATNO); 2191 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2192 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2193 break; 2194 } 2195 2196 msgdone = ahc->msgout_index == ahc->msgout_len; 2197 if (msgdone) { |
2007 /* | 2198 /* |
2008 * Clear our interrupt status and present the byte 2009 * on the bus, but don't unpause the sequencer. | 2199 * The target has requested a retry. 2200 * Re-assert ATN, reset our message index to 2201 * 0, and try again. |
2010 */ | 2202 */ |
2011 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2012 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2013 ahc_outb(ahc, SCSIDATL, ahc->msg_buf[ahc->msg_index++]); | 2203 ahc->msgout_index = 0; 2204 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); |
2014 } | 2205 } |
2206 2207 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2208 if (lastbyte) { 2209 /* Last byte is signified by dropping ATN */ 2210 ahc_outb(ahc, CLRSINT1, CLRATNO); 2211 } 2212 2213 /* 2214 * Clear our interrupt status and present 2215 * the next byte on the bus. 2216 */ 2217 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2218 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); |
|
2015 break; 2016 } 2017 case MSG_TYPE_INITIATOR_MSGIN: 2018 { | 2219 break; 2220 } 2221 case MSG_TYPE_INITIATOR_MSGIN: 2222 { |
2019 int phasemis; 2020 int done; | 2223 int phasemis; 2224 int message_done; |
2021 | 2225 |
2022 phasemis = (ahc_inb(ahc, SCSISIGI) & PHASE_MASK) != P_MESGIN; | 2226 phasemis = bus_phase != P_MESGIN; |
2023 | 2227 |
2024 if (phasemis == 0) { | 2228 if (phasemis) { 2229 ahc->msgin_index = 0; 2230 if (bus_phase == P_MESGOUT 2231 && (ahc->send_msg_perror == TRUE 2232 || (ahc->msgout_len != 0 2233 && ahc->msgout_index == 0))) { 2234 u_int scsisigo; |
2025 | 2235 |
2026 ahc->msg_len++; 2027 /* Pull the byte in without acking it */ 2028 ahc->msg_buf[ahc->msg_index] = ahc_inb(ahc, SCSIBUSL); 2029 done = ahc_parse_msg(ahc, scb, &devinfo); 2030 /* Ack the byte */ 2031 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2032 ahc_outb(ahc, CLRINT, CLRSCSIINT); | 2236 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2237 goto reswitch; 2238 } 2239 end_session = TRUE; 2240 break; 2241 } 2242 2243 /* Pull the byte in without acking it */ 2244 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2245 2246 message_done = ahc_parse_msg(ahc, path, &devinfo); 2247 2248 if (message_done) { 2249 /* 2250 * Clear our incoming message buffer in case there 2251 * is another message following this one. 2252 */ 2253 ahc->msgin_index = 0; 2254 2255 /* 2256 * If this message illicited a response, 2257 * assert ATN so the target takes us to the 2258 * message out phase. 2259 */ 2260 if (ahc->msgout_len != 0) 2261 ahc_outb(ahc, SCSISIGO, 2262 ahc_inb(ahc, SCSISIGO) | ATNO); 2263 } 2264 2265 /* Ack the byte */ 2266 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2267 ahc_inb(ahc, SCSIDATL); 2268 ahc->msgin_index++; 2269 break; 2270 } 2271 case MSG_TYPE_TARGET_MSGIN: 2272 { 2273 int msgdone; 2274 int msgout_request; 2275 2276 if (ahc->msgout_len == 0) 2277 panic("Target REQINIT with no active message"); 2278 2279 /* 2280 * If we interrupted a mesgout session, the initiator 2281 * will not know this until our first REQ. So, we 2282 * only honor mesgout requests after we've sent our 2283 * first byte. 2284 */ 2285 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2286 && ahc->msgout_index > 0) 2287 msgout_request = TRUE; 2288 else 2289 msgout_request = FALSE; 2290 2291 if (msgout_request) { 2292 2293 /* 2294 * Change gears and see if 2295 * this messages is of interest to 2296 * us or should be passed back to 2297 * the sequencer. 2298 */ 2299 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2300 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2301 ahc->msgin_index = 0; 2302 /* Dummy read to REQ for first byte */ |
2033 ahc_inb(ahc, SCSIDATL); | 2303 ahc_inb(ahc, SCSIDATL); |
2034 ahc->msg_index++; | 2304 ahc_outb(ahc, SXFRCTL0, 2305 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2306 break; |
2035 } | 2307 } |
2036 if (phasemis || done) { 2037 /* Time to end our message session */ 2038 ahc->msg_len = 0; 2039 ahc->msg_type = MSG_TYPE_NONE; 2040 simode1 = ahc_inb(ahc, SIMODE1) & ~ENREQINIT; 2041 ahc->flags &= ~AHC_HANDLING_REQINITS; 2042 ahc_outb(ahc, SIMODE1, simode1); 2043 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2044 unpause_sequencer(ahc, /* unpause_always */TRUE); | 2308 2309 msgdone = ahc->msgout_index == ahc->msgout_len; 2310 if (msgdone) { 2311 ahc_outb(ahc, SXFRCTL0, 2312 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2313 end_session = TRUE; 2314 break; |
2045 } | 2315 } |
2316 2317 /* 2318 * Present the next byte on the bus. 2319 */ 2320 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2321 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); |
|
2046 break; 2047 } | 2322 break; 2323 } |
2324 case MSG_TYPE_TARGET_MSGOUT: 2325 { 2326 int lastbyte; 2327 int msgdone; 2328 2329 /* 2330 * The initiator signals that this is 2331 * the last byte by dropping ATN. 2332 */ 2333 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2334 2335 /* 2336 * Read the latched byte, but turn off SPIOEN first 2337 * so that we don't inadvertantly cause a REQ for the 2338 * next byte. 2339 */ 2340 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2341 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2342 msgdone = ahc_parse_msg(ahc, path, &devinfo); 2343 ahc->msgin_index++; 2344 2345 /* 2346 * XXX Read spec about initiator dropping ATN too soon 2347 * and use msgdone to detect it. 2348 */ 2349 if (msgdone) { 2350 ahc->msgin_index = 0; 2351 2352 /* 2353 * If this message illicited a response, transition 2354 * to the Message in phase and send it. 2355 */ 2356 if (ahc->msgout_len != 0) { 2357 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2358 ahc_outb(ahc, SXFRCTL0, 2359 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2360 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2361 ahc->msgin_index = 0; 2362 break; 2363 } 2364 } 2365 2366 if (lastbyte) 2367 end_session = TRUE; 2368 else { 2369 /* Ask for the next byte. */ 2370 ahc_outb(ahc, SXFRCTL0, 2371 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2372 } 2373 2374 break; 2375 } |
|
2048 default: 2049 panic("Unknown REQINIT message type"); 2050 } | 2376 default: 2377 panic("Unknown REQINIT message type"); 2378 } |
2379 2380 if (end_session) { 2381 ahc_clear_msg_state(ahc); 2382 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2383 } else 2384 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); |
|
2051} 2052 | 2385} 2386 |
2387/* 2388 * See if we sent a particular extended message to the target. 2389 * If "full" is true, the target saw the full message. 2390 * If "full" is false, the target saw at least the first 2391 * byte of the message. 2392 */ |
|
2053static int | 2393static int |
2054ahc_parse_msg(struct ahc_softc *ahc, struct scb *scb, | 2394ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2395{ 2396 int found; 2397 int index; 2398 2399 found = FALSE; 2400 index = 0; 2401 2402 while (index < ahc->msgout_len) { 2403 if ((ahc->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 2404 || ahc->msgout_buf[index] == MSG_MESSAGE_REJECT) 2405 index++; 2406 else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2407 && ahc->msgout_buf[index] < MSG_IGN_WIDE_RESIDUE) { 2408 /* Skip tag type and tag id */ 2409 index += 2; 2410 } else if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2411 /* Found a candidate */ 2412 if (ahc->msgout_buf[index+2] == msgtype) { 2413 u_int end_index; 2414 2415 end_index = index + 1 2416 + ahc->msgout_buf[index + 1]; 2417 if (full) { 2418 if (ahc->msgout_index > end_index) 2419 found = TRUE; 2420 } else if (ahc->msgout_index > index) 2421 found = TRUE; 2422 } 2423 break; 2424 } else { 2425 panic("ahc_sent_msg: Inconsistent msg buffer"); 2426 } 2427 } 2428 return (found); 2429} 2430 2431static int 2432ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, |
2055 struct ahc_devinfo *devinfo) 2056{ 2057 int reject; 2058 int done; | 2433 struct ahc_devinfo *devinfo) 2434{ 2435 int reject; 2436 int done; |
2437 int response; |
|
2059 u_int targ_scsirate; 2060 2061 done = FALSE; | 2438 u_int targ_scsirate; 2439 2440 done = FALSE; |
2441 response = FALSE; |
|
2062 reject = FALSE; 2063 targ_scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 2064 /* 2065 * Parse as much of the message as is availible, 2066 * rejecting it if we don't support it. When 2067 * the entire message is availible and has been 2068 * handled, return TRUE indicating that we have 2069 * parsed an entire message. | 2442 reject = FALSE; 2443 targ_scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 2444 /* 2445 * Parse as much of the message as is availible, 2446 * rejecting it if we don't support it. When 2447 * the entire message is availible and has been 2448 * handled, return TRUE indicating that we have 2449 * parsed an entire message. |
2450 * 2451 * In the case of extended messages, we accept the length 2452 * byte outright and perform more checking once we know the 2453 * extended message type. |
|
2070 */ | 2454 */ |
2071 if (ahc->msg_buf[0] != MSG_EXTENDED) { | 2455 if (ahc->msgin_buf[0] == MSG_MESSAGE_REJECT) { 2456 ahc_handle_msg_reject(ahc, devinfo); 2457 done = TRUE; 2458 } else if (ahc->msgin_buf[0] == MSG_NOOP) { 2459 done = TRUE; 2460 } else if (ahc->msgin_buf[0] != MSG_EXTENDED) { |
2072 reject = TRUE; | 2461 reject = TRUE; |
2073 } 2074 2075 /* 2076 * Just accept the length byte outright and perform 2077 * more checking once we know the message type. 2078 */ 2079 if (!reject && (ahc->msg_len > 2)) { 2080 switch (ahc->msg_buf[2]) { | 2462 } else if (ahc->msgin_index >= 2) { 2463 switch (ahc->msgin_buf[2]) { |
2081 case MSG_EXT_SDTR: 2082 { 2083 struct ahc_syncrate *syncrate; 2084 u_int period; 2085 u_int offset; 2086 u_int saved_offset; 2087 u_int maxsync; 2088 | 2464 case MSG_EXT_SDTR: 2465 { 2466 struct ahc_syncrate *syncrate; 2467 u_int period; 2468 u_int offset; 2469 u_int saved_offset; 2470 u_int maxsync; 2471 |
2089 if (ahc->msg_buf[1] != MSG_EXT_SDTR_LEN) { | 2472 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { |
2090 reject = TRUE; 2091 break; 2092 } 2093 2094 /* 2095 * Wait until we have both args before validating 2096 * and acting on this message. | 2473 reject = TRUE; 2474 break; 2475 } 2476 2477 /* 2478 * Wait until we have both args before validating 2479 * and acting on this message. |
2480 * 2481 * Add one to MSG_EXT_SDTR_LEN to account for 2482 * the extended message preamble. |
|
2097 */ | 2483 */ |
2098 if (ahc->msg_len < (MSG_EXT_SDTR_LEN + /*preamble*/2)) | 2484 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) |
2099 break; 2100 | 2485 break; 2486 |
2101 period = ahc->msg_buf[3]; 2102 saved_offset = offset = ahc->msg_buf[4]; 2103 if ((ahc->features & AHC_ULTRA2) != 0) { 2104 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 2105 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 2106 maxsync = AHC_SYNCRATE_ULTRA2; 2107 } else { 2108 maxsync = AHC_SYNCRATE_ULTRA; 2109 } 2110 } else if ((ahc->features & AHC_ULTRA) != 0) { 2111 maxsync = AHC_SYNCRATE_ULTRA; 2112 } else { 2113 maxsync = AHC_SYNCRATE_FAST; 2114 } 2115 syncrate = ahc_find_syncrate(ahc, &period, maxsync); | 2487 period = ahc->msgin_buf[3]; 2488 saved_offset = offset = ahc->msgin_buf[4]; 2489 syncrate = ahc_devlimited_syncrate(ahc, &period); |
2116 ahc_validate_offset(ahc, syncrate, &offset, 2117 targ_scsirate & WIDEXFER); | 2490 ahc_validate_offset(ahc, syncrate, &offset, 2491 targ_scsirate & WIDEXFER); |
2118 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, | 2492 ahc_set_syncrate(ahc, devinfo, path, |
2119 syncrate, period, offset, 2120 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2121 2122 /* 2123 * See if we initiated Sync Negotiation 2124 * and didn't have to fall down to async 2125 * transfers. 2126 */ | 2493 syncrate, period, offset, 2494 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2495 2496 /* 2497 * See if we initiated Sync Negotiation 2498 * and didn't have to fall down to async 2499 * transfers. 2500 */ |
2127 if ((scb->flags & (SCB_MSGOUT_SDTR|SCB_MSGOUT_SENT)) 2128 == (SCB_MSGOUT_SDTR|SCB_MSGOUT_SENT)) { | 2501 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { |
2129 /* We started it */ 2130 if (saved_offset != offset) { 2131 /* Went too low - force async */ 2132 reject = TRUE; 2133 } | 2502 /* We started it */ 2503 if (saved_offset != offset) { 2504 /* Went too low - force async */ 2505 reject = TRUE; 2506 } |
2134 scb->flags &= ~SCB_MSGOUT_BITS; 2135 ahc->sdtrpending &= ~devinfo->target_mask; | |
2136 } else { 2137 /* 2138 * Send our own SDTR in reply 2139 */ | 2507 } else { 2508 /* 2509 * Send our own SDTR in reply 2510 */ |
2140 scb->flags &= ~SCB_MSGOUT_BITS; 2141 scb->flags |= SCB_MSGOUT_SDTR; 2142 ahc->sdtrpending |= devinfo->target_mask; 2143 xpt_print_path(scb->ccb->ccb_h.path); 2144 printf("Sending SDTR!!\n"); 2145 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2146 ahc_outb(ahc, SCSISIGO, 2147 ahc_inb(ahc, SCSISIGO) | ATNO); | 2511 if (bootverbose) 2512 printf("Sending SDTR!\n"); 2513 ahc->msgout_index = 0; 2514 ahc->msgout_len = 0; 2515 ahc_construct_sdtr(ahc, period, offset); 2516 ahc->msgout_index = 0; 2517 response = TRUE; |
2148 } 2149 done = TRUE; 2150 break; 2151 } 2152 case MSG_EXT_WDTR: 2153 { 2154 u_int bus_width; | 2518 } 2519 done = TRUE; 2520 break; 2521 } 2522 case MSG_EXT_WDTR: 2523 { 2524 u_int bus_width; |
2525 u_int sending_reply; |
|
2155 | 2526 |
2156 if (ahc->msg_buf[1] != MSG_EXT_WDTR_LEN) { | 2527 sending_reply = FALSE; 2528 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { |
2157 reject = TRUE; 2158 break; 2159 } 2160 2161 /* 2162 * Wait until we have our arg before validating 2163 * and acting on this message. | 2529 reject = TRUE; 2530 break; 2531 } 2532 2533 /* 2534 * Wait until we have our arg before validating 2535 * and acting on this message. |
2536 * 2537 * Add one to MSG_EXT_WDTR_LEN to account for 2538 * the extended message preamble. |
|
2164 */ | 2539 */ |
2165 if (ahc->msg_len < (MSG_EXT_WDTR_LEN + /*preamble*/2)) | 2540 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) |
2166 break; 2167 | 2541 break; 2542 |
2168 bus_width = ahc->msg_buf[3]; 2169 if ((scb->flags & (SCB_MSGOUT_WDTR|SCB_MSGOUT_SENT)) 2170 == (SCB_MSGOUT_WDTR|SCB_MSGOUT_SENT)) { | 2543 bus_width = ahc->msgin_buf[3]; 2544 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { |
2171 /* 2172 * Don't send a WDTR back to the 2173 * target, since we asked first. 2174 */ 2175 switch (bus_width){ 2176 default: 2177 /* 2178 * How can we do anything greater --- 7 unchanged lines hidden (view full) --- 2186 8 * (0x01 << bus_width)); 2187 /* FALLTHROUGH */ 2188 case MSG_EXT_WDTR_BUS_8_BIT: 2189 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2190 break; 2191 case MSG_EXT_WDTR_BUS_16_BIT: 2192 break; 2193 } | 2545 /* 2546 * Don't send a WDTR back to the 2547 * target, since we asked first. 2548 */ 2549 switch (bus_width){ 2550 default: 2551 /* 2552 * How can we do anything greater --- 7 unchanged lines hidden (view full) --- 2560 8 * (0x01 << bus_width)); 2561 /* FALLTHROUGH */ 2562 case MSG_EXT_WDTR_BUS_8_BIT: 2563 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2564 break; 2565 case MSG_EXT_WDTR_BUS_16_BIT: 2566 break; 2567 } |
2194 scb->flags &= ~SCB_MSGOUT_WDTR; 2195 ahc->wdtrpending &= ~devinfo->target_mask; | |
2196 } else { 2197 /* 2198 * Send our own WDTR in reply 2199 */ | 2568 } else { 2569 /* 2570 * Send our own WDTR in reply 2571 */ |
2200 printf("Sending WDTR!\n"); 2201 scb->flags &= ~SCB_MSGOUT_BITS; 2202 scb->flags |= SCB_MSGOUT_WDTR; | 2572 if (bootverbose) 2573 printf("Sending WDTR!\n"); |
2203 switch (bus_width) { 2204 default: 2205 if (ahc->features & AHC_WIDE) { 2206 /* Respond Wide */ 2207 bus_width = 2208 MSG_EXT_WDTR_BUS_16_BIT; 2209 break; 2210 } 2211 /* FALLTHROUGH */ 2212 case MSG_EXT_WDTR_BUS_8_BIT: 2213 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2214 break; 2215 } | 2574 switch (bus_width) { 2575 default: 2576 if (ahc->features & AHC_WIDE) { 2577 /* Respond Wide */ 2578 bus_width = 2579 MSG_EXT_WDTR_BUS_16_BIT; 2580 break; 2581 } 2582 /* FALLTHROUGH */ 2583 case MSG_EXT_WDTR_BUS_8_BIT: 2584 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2585 break; 2586 } |
2216 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2217 ahc_outb(ahc, SCSISIGO, 2218 ahc_inb(ahc, SCSISIGO) | ATNO); 2219 ahc->wdtrpending |= devinfo->target_mask; | 2587 ahc->msgout_index = 0; 2588 ahc->msgout_len = 0; 2589 ahc_construct_wdtr(ahc, bus_width); 2590 ahc->msgout_index = 0; 2591 response = TRUE; 2592 sending_reply = TRUE; |
2220 } | 2593 } |
2221 ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path, 2222 bus_width, | 2594 ahc_set_width(ahc, devinfo, path, bus_width, |
2223 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2224 2225 /* After a wide message, we are async */ | 2595 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2596 2597 /* After a wide message, we are async */ |
2226 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, | 2598 ahc_set_syncrate(ahc, devinfo, path, |
2227 /*syncrate*/NULL, /*period*/0, 2228 /*offset*/0, AHC_TRANS_ACTIVE); | 2599 /*syncrate*/NULL, /*period*/0, 2600 /*offset*/0, AHC_TRANS_ACTIVE); |
2229 if ((ahc->wdtrpending & devinfo->target_mask) == 0 2230 && (reject == 0)) { | 2601 if (sending_reply == FALSE && reject == FALSE) { |
2231 struct ahc_target_tinfo *tinfo; 2232 | 2602 struct ahc_target_tinfo *tinfo; 2603 |
2233 scb->flags &= ~SCB_MSGOUT_WDTR; | |
2234 tinfo = &ahc->transinfo[devinfo->target_offset]; 2235 if (tinfo->goal.period) { | 2604 tinfo = &ahc->transinfo[devinfo->target_offset]; 2605 if (tinfo->goal.period) { |
2606 u_int period; 2607 |
|
2236 /* Start the sync negotiation */ | 2608 /* Start the sync negotiation */ |
2237 ahc->sdtrpending |= 2238 devinfo->target_mask; 2239 scb->flags |= SCB_MSGOUT_SDTR; 2240 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2241 ahc_outb(ahc, SCSISIGO, 2242 ahc_inb(ahc, SCSISIGO) | ATNO); | 2609 period = tinfo->goal.period; 2610 ahc_devlimited_syncrate(ahc, &period); 2611 ahc->msgout_index = 0; 2612 ahc->msgout_len = 0; 2613 ahc_construct_sdtr(ahc, period, 2614 tinfo->goal.offset); 2615 ahc->msgout_index = 0; 2616 response = TRUE; |
2243 } 2244 } 2245 done = TRUE; 2246 break; 2247 } 2248 default: 2249 /* Unknown extended message. Reject it. */ 2250 reject = TRUE; 2251 break; 2252 } 2253 } 2254 2255 if (reject) { 2256 /* 2257 * Assert attention and setup to 2258 * reject the message. 2259 */ | 2617 } 2618 } 2619 done = TRUE; 2620 break; 2621 } 2622 default: 2623 /* Unknown extended message. Reject it. */ 2624 reject = TRUE; 2625 break; 2626 } 2627 } 2628 2629 if (reject) { 2630 /* 2631 * Assert attention and setup to 2632 * reject the message. 2633 */ |
2260 ahc_outb(ahc, MSG_OUT, MSG_MESSAGE_REJECT); 2261 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); | 2634 ahc->msgout_index = 0; 2635 ahc->msgout_len = 1; 2636 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; |
2262 done = TRUE; | 2637 done = TRUE; |
2638 response = TRUE; |
|
2263 } | 2639 } |
2640 2641 if (done && !response) 2642 /* Clear the outgoing message buffer */ 2643 ahc->msgout_len = 0; 2644 |
|
2264 return (done); 2265} 2266 2267static void 2268ahc_handle_devreset(struct ahc_softc *ahc, int target, char channel, 2269 cam_status status, ac_code acode, char *message, 2270 int verbose_only) 2271{ 2272 struct ahc_devinfo devinfo; 2273 struct cam_path *path; | 2645 return (done); 2646} 2647 2648static void 2649ahc_handle_devreset(struct ahc_softc *ahc, int target, char channel, 2650 cam_status status, ac_code acode, char *message, 2651 int verbose_only) 2652{ 2653 struct ahc_devinfo devinfo; 2654 struct cam_path *path; |
2274 path_id_t path_id; | |
2275 int found; 2276 int error; 2277 | 2655 int found; 2656 int error; 2657 |
2278 ahc_compile_devinfo(&devinfo, target, channel); | 2658 ahc_compile_devinfo(&devinfo, target, CAM_LUN_WILDCARD, channel, 2659 ROLE_UNKNOWN); |
2279 | 2660 |
2280 if (channel == 'B') 2281 path_id = cam_sim_path(ahc->sim_b); 2282 else 2283 path_id = cam_sim_path(ahc->sim); | 2661 error = ahc_create_path(ahc, &devinfo, &path); |
2284 | 2662 |
2285 error = xpt_create_path(&path, /*periph*/NULL, path_id, target, 2286 CAM_LUN_WILDCARD); | |
2287 /* 2288 * Go back to async/narrow transfers and renegotiate. | 2663 /* 2664 * Go back to async/narrow transfers and renegotiate. |
2665 * ahc_set_width and ahc_set_syncrate can cope with NULL 2666 * paths. |
|
2289 */ | 2667 */ |
2290 if (error == CAM_REQ_CMP) { 2291 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 2292 AHC_TRANS_CUR); 2293 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 2294 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 2295 } 2296 found = ahc_abort_scbs(ahc, target, channel, ALL_LUNS, | 2668 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 2669 AHC_TRANS_CUR); 2670 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 2671 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 2672 found = ahc_abort_scbs(ahc, target, channel, CAM_LUN_WILDCARD, |
2297 SCB_LIST_NULL, status); 2298 2299 if (error == CAM_REQ_CMP && acode != 0) 2300 xpt_async(AC_SENT_BDR, path, NULL); 2301 2302 if (error == CAM_REQ_CMP) 2303 xpt_free_path(path); 2304 --- 35 unchanged lines hidden (view full) --- 2340 /* 2341 * Unbusy this target/channel/lun. 2342 * XXX if we are holding two commands per lun, 2343 * send the next command. 2344 */ 2345 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 2346 2347 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { | 2673 SCB_LIST_NULL, status); 2674 2675 if (error == CAM_REQ_CMP && acode != 0) 2676 xpt_async(AC_SENT_BDR, path, NULL); 2677 2678 if (error == CAM_REQ_CMP) 2679 xpt_free_path(path); 2680 --- 35 unchanged lines hidden (view full) --- 2716 /* 2717 * Unbusy this target/channel/lun. 2718 * XXX if we are holding two commands per lun, 2719 * send the next command. 2720 */ 2721 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 2722 2723 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { |
2348 xpt_print_path(ccb->ccb_h.path); 2349 printf("CONT_TARGET_IO complete\n"); | |
2350 ccb->ccb_h.status = CAM_REQ_CMP; 2351 ahc_free_scb(ahc, scb); 2352 xpt_done(ccb); 2353 return; 2354 } 2355 2356 /* 2357 * If the recovery SCB completes, we have to be --- 28 unchanged lines hidden (view full) --- 2386 SEARCH_REMOVE); 2387 if (ahc_ccb_status(ccb) == CAM_BDR_SENT) 2388 ahc_set_ccb_status(ccb, CAM_CMD_TIMEOUT); 2389 xpt_print_path(ccb->ccb_h.path); 2390 printf("no longer in timeout, status = %x\n", 2391 ccb->ccb_h.status); 2392 } 2393 | 2724 ccb->ccb_h.status = CAM_REQ_CMP; 2725 ahc_free_scb(ahc, scb); 2726 xpt_done(ccb); 2727 return; 2728 } 2729 2730 /* 2731 * If the recovery SCB completes, we have to be --- 28 unchanged lines hidden (view full) --- 2760 SEARCH_REMOVE); 2761 if (ahc_ccb_status(ccb) == CAM_BDR_SENT) 2762 ahc_set_ccb_status(ccb, CAM_CMD_TIMEOUT); 2763 xpt_print_path(ccb->ccb_h.path); 2764 printf("no longer in timeout, status = %x\n", 2765 ccb->ccb_h.status); 2766 } 2767 |
2394 if ((scb->flags & (SCB_MSGOUT_WDTR|SCB_MSGOUT_SDTR)) != 0) { 2395 /* 2396 * Turn off the pending flags for any DTR messages 2397 * regardless of whether they completed successfully 2398 * or not. This ensures that we don't have lingering 2399 * state after we abort an SCB. 2400 */ 2401 u_int16_t mask; 2402 2403 mask = (0x01 << (SCB_TARGET(scb) 2404 | (SCB_IS_SCSIBUS_B(scb) ? SELBUSB : 0))); 2405 if (scb->flags & SCB_MSGOUT_WDTR) 2406 ahc->wdtrpending &= ~mask; 2407 if (scb->flags & SCB_MSGOUT_SDTR) 2408 ahc->sdtrpending &= ~mask; 2409 } | |
2410 /* Don't clobber any existing error state */ 2411 if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) { 2412 ccb->ccb_h.status |= CAM_REQ_CMP; 2413 } else if ((scb->flags & SCB_SENSE) != 0) { 2414 /* We performed autosense retrieval */ 2415 scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 2416 } 2417 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; --- 54 unchanged lines hidden (view full) --- 2472 /* 2473 * Assume we have a board at this stage and it has been reset. 2474 */ 2475 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 2476 ahc->our_id = ahc->our_id_b = 7; 2477 } 2478 2479 /* | 2768 /* Don't clobber any existing error state */ 2769 if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) { 2770 ccb->ccb_h.status |= CAM_REQ_CMP; 2771 } else if ((scb->flags & SCB_SENSE) != 0) { 2772 /* We performed autosense retrieval */ 2773 scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 2774 } 2775 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; --- 54 unchanged lines hidden (view full) --- 2830 /* 2831 * Assume we have a board at this stage and it has been reset. 2832 */ 2833 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 2834 ahc->our_id = ahc->our_id_b = 7; 2835 } 2836 2837 /* |
2838 * Default to allowing initiator operations. 2839 */ 2840 ahc->flags |= AHC_INITIATORMODE; 2841 2842 /* |
|
2480 * XXX Would be better to use a per device flag, but PCI and EISA 2481 * devices don't have them yet. 2482 */ | 2843 * XXX Would be better to use a per device flag, but PCI and EISA 2844 * devices don't have them yet. 2845 */ |
2483 if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) | 2846 if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) { |
2484 ahc->flags |= AHC_TARGETMODE; | 2847 ahc->flags |= AHC_TARGETMODE; |
2848 if ((ahc->features & AHC_ULTRA2) == 0) 2849 /* Only have space for both on the Ultra2 chips */ 2850 ahc->flags &= ~AHC_INITIATORMODE; 2851 } |
|
2485 | 2852 |
2853 |
|
2486 if ((ahc->features & AHC_TWIN) != 0) { 2487 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 2488 ahc->our_id, ahc->our_id_b, 2489 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 2490 } else { 2491 if ((ahc->features & AHC_WIDE) != 0) { 2492 printf("Wide "); 2493 } else { --- 125 unchanged lines hidden (view full) --- 2619 * the board bios has left us. In the lower four bits of each 2620 * target's scratch space any value other than 0 indicates 2621 * that we should initiate synchronous transfers. If it's zero, 2622 * the user or the BIOS has decided to disable synchronous 2623 * negotiation to that target so we don't activate the needsdtr 2624 * flag. 2625 */ 2626 ahc->ultraenb = 0; | 2854 if ((ahc->features & AHC_TWIN) != 0) { 2855 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 2856 ahc->our_id, ahc->our_id_b, 2857 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 2858 } else { 2859 if ((ahc->features & AHC_WIDE) != 0) { 2860 printf("Wide "); 2861 } else { --- 125 unchanged lines hidden (view full) --- 2987 * the board bios has left us. In the lower four bits of each 2988 * target's scratch space any value other than 0 indicates 2989 * that we should initiate synchronous transfers. If it's zero, 2990 * the user or the BIOS has decided to disable synchronous 2991 * negotiation to that target so we don't activate the needsdtr 2992 * flag. 2993 */ 2994 ahc->ultraenb = 0; |
2627 ahc->tagenable = ALL_TARGETS; | 2995 ahc->tagenable = ALL_TARGETS_MASK; |
2628 2629 /* Grab the disconnection disable table and invert it for our needs */ 2630 if (ahc->flags & AHC_USEDEFAULTS) { 2631 printf("%s: Host Adapter Bios disabled. Using default SCSI " 2632 "device parameters\n", ahc_name(ahc)); 2633 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 2634 AHC_TERM_ENB_A|AHC_TERM_ENB_B; | 2996 2997 /* Grab the disconnection disable table and invert it for our needs */ 2998 if (ahc->flags & AHC_USEDEFAULTS) { 2999 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3000 "device parameters\n", ahc_name(ahc)); 3001 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3002 AHC_TERM_ENB_A|AHC_TERM_ENB_B; |
2635 ahc->discenable = ALL_TARGETS; | 3003 ahc->discenable = ALL_TARGETS_MASK; |
2636 if ((ahc->features & AHC_ULTRA) != 0) 2637 ahc->ultraenb = 0xffff; 2638 } else { 2639 ahc->discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 2640 | ahc_inb(ahc, DISC_DSB)); 2641 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 2642 ahc->ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 2643 | ahc_inb(ahc, ULTRA_ENB); --- 59 unchanged lines hidden (view full) --- 2703 } 2704 if ((scsirate & WIDEXFER) != 0 2705 && (ahc->features & AHC_WIDE) != 0) { 2706 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 2707 } 2708 2709 } 2710 } | 3004 if ((ahc->features & AHC_ULTRA) != 0) 3005 ahc->ultraenb = 0xffff; 3006 } else { 3007 ahc->discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3008 | ahc_inb(ahc, DISC_DSB)); 3009 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3010 ahc->ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3011 | ahc_inb(ahc, ULTRA_ENB); --- 59 unchanged lines hidden (view full) --- 3071 } 3072 if ((scsirate & WIDEXFER) != 0 3073 && (ahc->features & AHC_WIDE) != 0) { 3074 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3075 } 3076 3077 } 3078 } |
2711 ahc->sdtrpending = 0; 2712 ahc->wdtrpending = 0; | |
2713 2714#ifdef AHC_DEBUG 2715 if (ahc_debug & AHC_SHOWMISC) 2716 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n" 2717 "DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 2718 ahc->needsdtr_orig, ahc->needwdtr_orig, 2719 ahc->discenable, ahc->ultraenb); 2720#endif --- 98 unchanged lines hidden (view full) --- 2819 } 2820 } 2821 2822 /* Our Q FIFOs are empty. */ 2823 ahc_outb(ahc, KERNEL_QINPOS, 0); 2824 ahc_outb(ahc, QINPOS, 0); 2825 ahc_outb(ahc, QOUTPOS, 0); 2826 | 3079 3080#ifdef AHC_DEBUG 3081 if (ahc_debug & AHC_SHOWMISC) 3082 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n" 3083 "DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3084 ahc->needsdtr_orig, ahc->needwdtr_orig, 3085 ahc->discenable, ahc->ultraenb); 3086#endif --- 98 unchanged lines hidden (view full) --- 3185 } 3186 } 3187 3188 /* Our Q FIFOs are empty. */ 3189 ahc_outb(ahc, KERNEL_QINPOS, 0); 3190 ahc_outb(ahc, QINPOS, 0); 3191 ahc_outb(ahc, QOUTPOS, 0); 3192 |
3193 /* Don't have any special messages to send to targets */ 3194 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3195 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3196 |
|
2827 /* 2828 * Use the built in queue management registers 2829 * if they are available. 2830 */ 2831 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 2832 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 2833 ahc_outb(ahc, SDSCB_QOFF, 0); 2834 ahc_outb(ahc, SNSCB_QOFF, 0); --- 117 unchanged lines hidden (view full) --- 2952 } 2953 2954 /* 2955 * The target_id represents the target we attempt to 2956 * select. In target mode, this is the initiator of 2957 * the original command. 2958 */ 2959 target_id = ccb->csio.init_id; | 3197 /* 3198 * Use the built in queue management registers 3199 * if they are available. 3200 */ 3201 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3202 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3203 ahc_outb(ahc, SDSCB_QOFF, 0); 3204 ahc_outb(ahc, SNSCB_QOFF, 0); --- 117 unchanged lines hidden (view full) --- 3322 } 3323 3324 /* 3325 * The target_id represents the target we attempt to 3326 * select. In target mode, this is the initiator of 3327 * the original command. 3328 */ 3329 target_id = ccb->csio.init_id; |
2960 xpt_print_path(ccb->ccb_h.path); 2961 printf("Sending a continue TIO\n"); | |
2962 /* FALLTHROUGH */ 2963 } 2964 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2965 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2966 { 2967 struct scb *scb; 2968 struct hardware_scb *hscb; 2969 struct ahc_target_tinfo *tinfo; --- 45 unchanged lines hidden (view full) --- 3015 hscb->control |= DISCENB; 3016 3017 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 3018 hscb->cmdpointer = NULL; 3019 scb->flags |= SCB_DEVICE_RESET; 3020 hscb->control |= MK_MESSAGE; 3021 ahc_execute_scb(scb, NULL, 0, 0); 3022 } else { | 3330 /* FALLTHROUGH */ 3331 } 3332 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 3333 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3334 { 3335 struct scb *scb; 3336 struct hardware_scb *hscb; 3337 struct ahc_target_tinfo *tinfo; --- 45 unchanged lines hidden (view full) --- 3383 hscb->control |= DISCENB; 3384 3385 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 3386 hscb->cmdpointer = NULL; 3387 scb->flags |= SCB_DEVICE_RESET; 3388 hscb->control |= MK_MESSAGE; 3389 ahc_execute_scb(scb, NULL, 0, 0); 3390 } else { |
3023 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 3024 if (tinfo->current.width != tinfo->goal.width) { 3025 if ((ahc->wdtrpending & mask) == 0) { 3026 ahc->wdtrpending |= mask; 3027 hscb->control |= MK_MESSAGE; 3028 scb->flags |= SCB_MSGOUT_WDTR; 3029 } 3030 } else if ((tinfo->current.period 3031 != tinfo->goal.period) 3032 && (ahc->sdtrpending & mask) == 0) { 3033 ahc->sdtrpending |= mask; 3034 hscb->control |= MK_MESSAGE; 3035 scb->flags |= SCB_MSGOUT_SDTR; 3036 } 3037 } else { | 3391 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { |
3038 if (ahc->pending_device == lstate) { 3039 scb->flags |= SCB_TARGET_IMMEDIATE; 3040 ahc->pending_device = NULL; 3041 } 3042 hscb->control |= TARGET_SCB; 3043 hscb->cmdpointer = IDENTIFY_SEEN; 3044 if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { 3045 hscb->cmdpointer |= SPHASE_PENDING; --- 143 unchanged lines hidden (view full) --- 3189 struct ahc_devinfo devinfo; 3190 struct ccb_trans_settings *cts; 3191 struct ahc_target_tinfo *tinfo; 3192 u_int update_type; 3193 int s; 3194 3195 cts = &ccb->cts; 3196 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, | 3392 if (ahc->pending_device == lstate) { 3393 scb->flags |= SCB_TARGET_IMMEDIATE; 3394 ahc->pending_device = NULL; 3395 } 3396 hscb->control |= TARGET_SCB; 3397 hscb->cmdpointer = IDENTIFY_SEEN; 3398 if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { 3399 hscb->cmdpointer |= SPHASE_PENDING; --- 143 unchanged lines hidden (view full) --- 3543 struct ahc_devinfo devinfo; 3544 struct ccb_trans_settings *cts; 3545 struct ahc_target_tinfo *tinfo; 3546 u_int update_type; 3547 int s; 3548 3549 cts = &ccb->cts; 3550 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, |
3197 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); | 3551 cts->ccb_h.target_lun, 3552 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3553 ROLE_UNKNOWN); |
3198 tinfo = &ahc->transinfo[devinfo.target_offset]; 3199 update_type = 0; 3200 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3201 update_type |= AHC_TRANS_GOAL; 3202 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 3203 update_type |= AHC_TRANS_USER; 3204 3205 s = splcam(); --- 19 unchanged lines hidden (view full) --- 3225 break; 3226 /* FALLTHROUGH to 8bit */ 3227 case MSG_EXT_WDTR_BUS_32_BIT: 3228 case MSG_EXT_WDTR_BUS_8_BIT: 3229 default: 3230 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3231 break; 3232 } | 3554 tinfo = &ahc->transinfo[devinfo.target_offset]; 3555 update_type = 0; 3556 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3557 update_type |= AHC_TRANS_GOAL; 3558 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 3559 update_type |= AHC_TRANS_USER; 3560 3561 s = splcam(); --- 19 unchanged lines hidden (view full) --- 3581 break; 3582 /* FALLTHROUGH to 8bit */ 3583 case MSG_EXT_WDTR_BUS_32_BIT: 3584 case MSG_EXT_WDTR_BUS_8_BIT: 3585 default: 3586 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3587 break; 3588 } |
3233 if ((update_type & AHC_TRANS_GOAL) != 0) 3234 tinfo->goal.width = cts->bus_width; 3235 if ((update_type & AHC_TRANS_USER) != 0) 3236 tinfo->user.width = cts->bus_width; | 3589 ahc_set_width(ahc, &devinfo, cts->ccb_h.path, 3590 cts->bus_width, update_type); |
3237 } 3238 3239 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 3240 struct ahc_syncrate *syncrate; 3241 u_int maxsync; 3242 3243 if ((ahc->features & AHC_ULTRA2) != 0) 3244 maxsync = AHC_SYNCRATE_ULTRA2; --- 13 unchanged lines hidden (view full) --- 3258 maxsync); 3259 ahc_validate_offset(ahc, syncrate, &cts->sync_offset, 3260 tinfo->goal.width); 3261 3262 /* We use a period of 0 to represent async */ 3263 if (cts->sync_offset == 0) 3264 cts->sync_period = 0; 3265 | 3591 } 3592 3593 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 3594 struct ahc_syncrate *syncrate; 3595 u_int maxsync; 3596 3597 if ((ahc->features & AHC_ULTRA2) != 0) 3598 maxsync = AHC_SYNCRATE_ULTRA2; --- 13 unchanged lines hidden (view full) --- 3612 maxsync); 3613 ahc_validate_offset(ahc, syncrate, &cts->sync_offset, 3614 tinfo->goal.width); 3615 3616 /* We use a period of 0 to represent async */ 3617 if (cts->sync_offset == 0) 3618 cts->sync_period = 0; 3619 |
3266 if ((update_type & AHC_TRANS_GOAL) != 0) { 3267 tinfo->goal.period = cts->sync_period; 3268 tinfo->goal.offset = cts->sync_offset; 3269 } 3270 if ((update_type & AHC_TRANS_USER) != 0) { 3271 tinfo->user.period = cts->sync_period; 3272 tinfo->user.offset = cts->sync_offset; 3273 } | 3620 ahc_set_syncrate(ahc, &devinfo, cts->ccb_h.path, 3621 syncrate, cts->sync_period, 3622 cts->sync_offset, update_type); |
3274 } 3275 splx(s); 3276 ccb->ccb_h.status = CAM_REQ_CMP; 3277 xpt_done(ccb); 3278 break; 3279 } 3280 case XPT_GET_TRAN_SETTINGS: 3281 /* Get default/user set transfer settings for the target */ 3282 { 3283 struct ahc_devinfo devinfo; 3284 struct ccb_trans_settings *cts; 3285 struct ahc_target_tinfo *targ_info; 3286 struct ahc_transinfo *tinfo; 3287 int s; 3288 3289 cts = &ccb->cts; 3290 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, | 3623 } 3624 splx(s); 3625 ccb->ccb_h.status = CAM_REQ_CMP; 3626 xpt_done(ccb); 3627 break; 3628 } 3629 case XPT_GET_TRAN_SETTINGS: 3630 /* Get default/user set transfer settings for the target */ 3631 { 3632 struct ahc_devinfo devinfo; 3633 struct ccb_trans_settings *cts; 3634 struct ahc_target_tinfo *targ_info; 3635 struct ahc_transinfo *tinfo; 3636 int s; 3637 3638 cts = &ccb->cts; 3639 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, |
3291 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); | 3640 cts->ccb_h.target_lun, 3641 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3642 ROLE_UNKNOWN); |
3292 targ_info = &ahc->transinfo[devinfo.target_offset]; 3293 3294 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3295 tinfo = &targ_info->current; 3296 else 3297 tinfo = &targ_info->user; 3298 3299 s = splcam(); --- 88 unchanged lines hidden (view full) --- 3388 cpi->hba_inquiry |= PI_WIDE_16; 3389 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3390 cpi->target_sprt = PIT_PROCESSOR 3391 | PIT_DISCONNECT 3392 | PIT_TERM_IO; 3393 } else { 3394 cpi->target_sprt = 0; 3395 } | 3643 targ_info = &ahc->transinfo[devinfo.target_offset]; 3644 3645 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3646 tinfo = &targ_info->current; 3647 else 3648 tinfo = &targ_info->user; 3649 3650 s = splcam(); --- 88 unchanged lines hidden (view full) --- 3739 cpi->hba_inquiry |= PI_WIDE_16; 3740 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3741 cpi->target_sprt = PIT_PROCESSOR 3742 | PIT_DISCONNECT 3743 | PIT_TERM_IO; 3744 } else { 3745 cpi->target_sprt = 0; 3746 } |
3396 cpi->hba_misc = 0; | 3747 cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE) 3748 ? 0 : PIM_NOINITIATOR|PIM_NOBUSRESET; |
3397 cpi->hba_eng_cnt = 0; 3398 cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 3399 cpi->max_lun = 7; 3400 if (SIM_IS_SCSIBUS_B(ahc, sim)) 3401 cpi->initiator_id = ahc->our_id_b; 3402 else 3403 cpi->initiator_id = ahc->our_id; 3404 cpi->bus_id = cam_sim_bus(sim); --- 21 unchanged lines hidden (view full) --- 3426 sim = (struct cam_sim *)callback_arg; 3427 ahc = (struct ahc_softc *)cam_sim_softc(sim); 3428 switch (code) { 3429 case AC_LOST_DEVICE: 3430 { 3431 struct ahc_devinfo devinfo; 3432 3433 ahc_compile_devinfo(&devinfo, xpt_path_target_id(path), | 3749 cpi->hba_eng_cnt = 0; 3750 cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 3751 cpi->max_lun = 7; 3752 if (SIM_IS_SCSIBUS_B(ahc, sim)) 3753 cpi->initiator_id = ahc->our_id_b; 3754 else 3755 cpi->initiator_id = ahc->our_id; 3756 cpi->bus_id = cam_sim_bus(sim); --- 21 unchanged lines hidden (view full) --- 3778 sim = (struct cam_sim *)callback_arg; 3779 ahc = (struct ahc_softc *)cam_sim_softc(sim); 3780 switch (code) { 3781 case AC_LOST_DEVICE: 3782 { 3783 struct ahc_devinfo devinfo; 3784 3785 ahc_compile_devinfo(&devinfo, xpt_path_target_id(path), |
3434 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); | 3786 xpt_path_lun_id(path), 3787 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3788 ROLE_UNKNOWN); |
3435 3436 /* 3437 * Revert to async/narrow transfers 3438 * for the next device. 3439 */ 3440 pause_sequencer(ahc); 3441 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 3442 AHC_TRANS_GOAL|AHC_TRANS_CUR); --- 82 unchanged lines hidden (view full) --- 3525 scb->flags |= SCB_ACTIVE; 3526 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3527 3528 ccb->ccb_h.timeout_ch = 3529 timeout(ahc_timeout, (caddr_t)scb, 3530 (ccb->ccb_h.timeout * hz) / 1000); 3531 3532 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { | 3789 3790 /* 3791 * Revert to async/narrow transfers 3792 * for the next device. 3793 */ 3794 pause_sequencer(ahc); 3795 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 3796 AHC_TRANS_GOAL|AHC_TRANS_CUR); --- 82 unchanged lines hidden (view full) --- 3879 scb->flags |= SCB_ACTIVE; 3880 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3881 3882 ccb->ccb_h.timeout_ch = 3883 timeout(ahc_timeout, (caddr_t)scb, 3884 (ccb->ccb_h.timeout * hz) / 1000); 3885 3886 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { |
3533 xpt_print_path(ccb->ccb_h.path); 3534 printf("Returning an immediate CTIO\n"); | |
3535 if ((ahc->flags & AHC_PAGESCBS) == 0) 3536 ahc_outb(ahc, SCBPTR, scb->hscb->tag); | 3887 if ((ahc->flags & AHC_PAGESCBS) == 0) 3888 ahc_outb(ahc, SCBPTR, scb->hscb->tag); |
3889 pause_sequencer(ahc); |
|
3537 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); | 3890 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); |
3538 unpause_sequencer(ahc, /*unpause_always*/TRUE); | 3891 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 3892 unpause_sequencer(ahc, /*unpause_always*/FALSE); |
3539 } else { 3540 3541 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 3542 3543 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3544 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 3545 } else { 3546 pause_sequencer(ahc); --- 546 unchanged lines hidden (view full) --- 4093 bus_state = P_BUSFREE; 4094 break; 4095 } 4096 4097 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 4098 4099 printf("SEQADDR == 0x%x\n", ahc_inb(ahc, SEQADDR0) 4100 | (ahc_inb(ahc, SEQADDR1) << 8)); | 3893 } else { 3894 3895 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 3896 3897 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3898 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 3899 } else { 3900 pause_sequencer(ahc); --- 546 unchanged lines hidden (view full) --- 4447 bus_state = P_BUSFREE; 4448 break; 4449 } 4450 4451 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 4452 4453 printf("SEQADDR == 0x%x\n", ahc_inb(ahc, SEQADDR0) 4454 | (ahc_inb(ahc, SEQADDR1) << 8)); |
4455 4456 printf("SIMODE1 = 0x%x\n", ahc_inb(ahc, SIMODE1)); 4457 printf("INTSTAT = 0x%x\n", ahc_inb(ahc, INTSTAT)); |
|
4101 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4102#if 0 4103 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4104 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4105 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4106 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4107 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4108 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); --- 451 unchanged lines hidden (view full) --- 4560 char cur_channel; 4561 struct cam_path *path; 4562 4563 pause_sequencer(ahc); 4564 /* 4565 * Clean up all the state information for the 4566 * pending transactions on this bus. 4567 */ | 4458 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4459#if 0 4460 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4461 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4462 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4463 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4464 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4465 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); --- 451 unchanged lines hidden (view full) --- 4917 char cur_channel; 4918 struct cam_path *path; 4919 4920 pause_sequencer(ahc); 4921 /* 4922 * Clean up all the state information for the 4923 * pending transactions on this bus. 4924 */ |
4568 found = ahc_abort_scbs(ahc, ALL_TARGETS, channel, ALL_LUNS, 4569 SCB_LIST_NULL, CAM_SCSI_BUS_RESET); | 4925 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 4926 CAM_LUN_WILDCARD, SCB_LIST_NULL, 4927 CAM_SCSI_BUS_RESET); |
4570 path = channel == 'B' ? ahc->path_b : ahc->path; 4571 4572 /* Notify the XPT that a bus reset occurred */ 4573 xpt_async(AC_BUS_RESET, path, NULL); 4574 4575 /* 4576 * Revert to async/narrow transfers until we renegotiate. 4577 */ 4578 max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 4579 for (target = 0; target <= max_target; target++) { 4580 struct ahc_devinfo devinfo; 4581 | 4928 path = channel == 'B' ? ahc->path_b : ahc->path; 4929 4930 /* Notify the XPT that a bus reset occurred */ 4931 xpt_async(AC_BUS_RESET, path, NULL); 4932 4933 /* 4934 * Revert to async/narrow transfers until we renegotiate. 4935 */ 4936 max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 4937 for (target = 0; target <= max_target; target++) { 4938 struct ahc_devinfo devinfo; 4939 |
4582 ahc_compile_devinfo(&devinfo, target, channel); | 4940 ahc_compile_devinfo(&devinfo, target, CAM_LUN_WILDCARD, 4941 channel, ROLE_UNKNOWN); |
4583 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 4584 AHC_TRANS_CUR); 4585 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 4586 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 4587 } 4588 4589 /* 4590 * Reset the bus if we are initiating this reset and --- 5 unchanged lines hidden (view full) --- 4596 && ((sblkctl & SELBUSB) != 0)) 4597 cur_channel = 'B'; 4598 if (cur_channel != channel) { 4599 /* Case 1: Command for another bus is active 4600 * Stealthily reset the other bus without 4601 * upsetting the current bus. 4602 */ 4603 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); | 4942 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 4943 AHC_TRANS_CUR); 4944 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 4945 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 4946 } 4947 4948 /* 4949 * Reset the bus if we are initiating this reset and --- 5 unchanged lines hidden (view full) --- 4955 && ((sblkctl & SELBUSB) != 0)) 4956 cur_channel = 'B'; 4957 if (cur_channel != channel) { 4958 /* Case 1: Command for another bus is active 4959 * Stealthily reset the other bus without 4960 * upsetting the current bus. 4961 */ 4962 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); |
4604 ahc_outb(ahc, SIMODE1, 4605 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); | 4963 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); |
4606 ahc_outb(ahc, SCSISEQ, 4607 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4608 if (initiate_reset) 4609 ahc_reset_current_bus(ahc); 4610 ahc_clear_intstat(ahc); 4611 ahc_outb(ahc, SBLKCTL, sblkctl); 4612 unpause_sequencer(ahc, /*unpause_always*/FALSE); 4613 } else { 4614 /* Case 2: A command from this bus is active or we're idle */ | 4964 ahc_outb(ahc, SCSISEQ, 4965 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4966 if (initiate_reset) 4967 ahc_reset_current_bus(ahc); 4968 ahc_clear_intstat(ahc); 4969 ahc_outb(ahc, SBLKCTL, sblkctl); 4970 unpause_sequencer(ahc, /*unpause_always*/FALSE); 4971 } else { 4972 /* Case 2: A command from this bus is active or we're idle */ |
4615 ahc_outb(ahc, SIMODE1, 4616 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); 4617 ahc->flags &= ~AHC_HANDLING_REQINITS; 4618 ahc->msg_type = MSG_TYPE_NONE; | 4973 ahc_clear_msg_state(ahc); 4974 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); |
4619 ahc_outb(ahc, SCSISEQ, 4620 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4621 if (initiate_reset) 4622 ahc_reset_current_bus(ahc); 4623 ahc_clear_intstat(ahc); 4624 restart_sequencer(ahc); 4625 } 4626 return found; --- 4 unchanged lines hidden (view full) --- 4631{ 4632 int targ = SCB_TARGET(scb); 4633 char chan = SCB_CHANNEL(scb); 4634 int slun = SCB_LUN(scb); 4635 int match; 4636 4637 match = ((chan == channel) || (channel == ALL_CHANNELS)); 4638 if (match != 0) | 4975 ahc_outb(ahc, SCSISEQ, 4976 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4977 if (initiate_reset) 4978 ahc_reset_current_bus(ahc); 4979 ahc_clear_intstat(ahc); 4980 restart_sequencer(ahc); 4981 } 4982 return found; --- 4 unchanged lines hidden (view full) --- 4987{ 4988 int targ = SCB_TARGET(scb); 4989 char chan = SCB_CHANNEL(scb); 4990 int slun = SCB_LUN(scb); 4991 int match; 4992 4993 match = ((chan == channel) || (channel == ALL_CHANNELS)); 4994 if (match != 0) |
4639 match = ((targ == target) || (target == ALL_TARGETS)); | 4995 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); |
4640 if (match != 0) | 4996 if (match != 0) |
4641 match = ((lun == slun) || (lun == ALL_LUNS)); | 4997 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); |
4642 if (match != 0) 4643 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 4644 4645 return match; 4646} 4647 4648static void 4649ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 4650{ | 4998 if (match != 0) 4999 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5000 5001 return match; 5002} 5003 5004static void 5005ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5006{ |
4651 ahc->msg_buf[ahc->msg_index++] = MSG_EXTENDED; 4652 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_SDTR_LEN; 4653 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_SDTR; 4654 ahc->msg_buf[ahc->msg_index++] = period; 4655 ahc->msg_buf[ahc->msg_index++] = offset; 4656 ahc->msg_len += 5; | 5007 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5008 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5009 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5010 ahc->msgout_buf[ahc->msgout_index++] = period; 5011 ahc->msgout_buf[ahc->msgout_index++] = offset; 5012 ahc->msgout_len += 5; |
4657} 4658 4659static void 4660ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 4661{ | 5013} 5014 5015static void 5016ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5017{ |
4662 ahc->msg_buf[ahc->msg_index++] = MSG_EXTENDED; 4663 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_WDTR_LEN; 4664 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_WDTR; 4665 ahc->msg_buf[ahc->msg_index++] = bus_width; 4666 ahc->msg_len += 4; | 5018 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5019 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5020 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5021 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5022 ahc->msgout_len += 4; |
4667} 4668 4669static void 4670ahc_calc_residual(struct scb *scb) 4671{ 4672 struct hardware_scb *hscb; 4673 4674 hscb = scb->hscb; --- 78 unchanged lines hidden (view full) --- 4753 struct scb *pending_scb; 4754 struct hardware_scb *pending_hscb; 4755 struct ahc_target_tinfo *tinfo; 4756 struct ahc_devinfo devinfo; 4757 4758 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 4759 pending_hscb = pending_scb->hscb; 4760 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), | 5023} 5024 5025static void 5026ahc_calc_residual(struct scb *scb) 5027{ 5028 struct hardware_scb *hscb; 5029 5030 hscb = scb->hscb; --- 78 unchanged lines hidden (view full) --- 5109 struct scb *pending_scb; 5110 struct hardware_scb *pending_hscb; 5111 struct ahc_target_tinfo *tinfo; 5112 struct ahc_devinfo devinfo; 5113 5114 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 5115 pending_hscb = pending_scb->hscb; 5116 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), |
4761 SCB_CHANNEL(pending_scb)); | 5117 SCB_LUN(pending_scb), 5118 SCB_CHANNEL(pending_scb), 5119 ROLE_UNKNOWN); |
4762 tinfo = &ahc->transinfo[devinfo.target_offset]; 4763 pending_hscb->control &= ~ULTRAENB; 4764 if ((ahc->ultraenb & devinfo.target_mask) != 0) 4765 pending_hscb->control |= ULTRAENB; 4766 pending_hscb->scsirate = tinfo->scsirate; 4767 pending_hscb->scsioffset = tinfo->current.offset; 4768 pending_ccb_count++; 4769 ccbh = LIST_NEXT(ccbh, sim_links.le); --- 14 unchanged lines hidden (view full) --- 4784 struct hardware_scb *pending_hscb; 4785 struct ahc_target_tinfo *tinfo; 4786 struct ahc_devinfo devinfo; 4787 u_int control; 4788 4789 pending_scb = ahc->scb_data->scbarray[scb_tag]; 4790 pending_hscb = pending_scb->hscb; 4791 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), | 5120 tinfo = &ahc->transinfo[devinfo.target_offset]; 5121 pending_hscb->control &= ~ULTRAENB; 5122 if ((ahc->ultraenb & devinfo.target_mask) != 0) 5123 pending_hscb->control |= ULTRAENB; 5124 pending_hscb->scsirate = tinfo->scsirate; 5125 pending_hscb->scsioffset = tinfo->current.offset; 5126 pending_ccb_count++; 5127 ccbh = LIST_NEXT(ccbh, sim_links.le); --- 14 unchanged lines hidden (view full) --- 5142 struct hardware_scb *pending_hscb; 5143 struct ahc_target_tinfo *tinfo; 5144 struct ahc_devinfo devinfo; 5145 u_int control; 5146 5147 pending_scb = ahc->scb_data->scbarray[scb_tag]; 5148 pending_hscb = pending_scb->hscb; 5149 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), |
4792 SCB_CHANNEL(pending_scb)); | 5150 SCB_LUN(pending_scb), 5151 SCB_CHANNEL(pending_scb), 5152 ROLE_UNKNOWN); |
4793 tinfo = &ahc->transinfo[devinfo.target_offset]; 4794 control = ahc_inb(ahc, SCB_CONTROL); 4795 control &= ~ULTRAENB; 4796 if ((ahc->ultraenb & devinfo.target_mask) != 0) 4797 control |= ULTRAENB; 4798 ahc_outb(ahc, SCB_CONTROL, control); 4799 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 4800 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); --- 47 unchanged lines hidden --- | 5153 tinfo = &ahc->transinfo[devinfo.target_offset]; 5154 control = ahc_inb(ahc, SCB_CONTROL); 5155 control &= ~ULTRAENB; 5156 if ((ahc->ultraenb & devinfo.target_mask) != 0) 5157 control |= ULTRAENB; 5158 ahc_outb(ahc, SCB_CONTROL, control); 5159 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5160 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); --- 47 unchanged lines hidden --- |