36c36
< __FBSDID("$FreeBSD: head/sys/boot/sparc64/loader/main.c 221869 2011-05-14 01:53:38Z attilio $");
---
> __FBSDID("$FreeBSD: head/sys/boot/sparc64/loader/main.c 223719 2011-07-02 11:14:54Z marius $");
99c99
< static inline u_long dtlb_get_data_sun4u(u_int);
---
> static inline u_long dtlb_get_data_sun4u(u_int, u_int);
102c102
< static inline u_long itlb_get_data_sun4u(u_int);
---
> static inline u_long itlb_get_data_sun4u(u_int, u_int);
138a139
> static u_int tlb_locked;
358c359
< dtlb_get_data_sun4u(u_int slot)
---
> dtlb_get_data_sun4u(u_int tlb, u_int slot)
359a361
> u_long data, pstate;
360a363
> slot = TLB_DAR_SLOT(tlb, slot);
362,363c365,366
< * We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
< * around errata of USIII and beyond.
---
> * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
> * work around errata of USIII and beyond.
365,366c368,373
< (void)ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG);
< return (ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG));
---
> pstate = rdpr(pstate);
> wrpr(pstate, pstate & ~PSTATE_IE, 0);
> (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
> data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
> wrpr(pstate, pstate, 0);
> return (data);
370c377
< itlb_get_data_sun4u(u_int slot)
---
> itlb_get_data_sun4u(u_int tlb, u_int slot)
371a379
> u_long data, pstate;
372a381
> slot = TLB_DAR_SLOT(tlb, slot);
374,375c383,384
< * We read ASI_ITLB_DATA_ACCESS_REG twice in order to work
< * around errata of USIII and beyond.
---
> * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
> * work around errata of USIII and beyond.
377,378c386,391
< (void)ldxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG);
< return (ldxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG));
---
> pstate = rdpr(pstate);
> wrpr(pstate, pstate & ~PSTATE_IE, 0);
> (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
> data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
> wrpr(pstate, pstate, 0);
> return (data);
385c398
< int i;
---
> u_int i, tlb;
390c403,404
< reg = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
---
> reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
> ASI_DTLB_TAG_READ_REG);
393c407
< reg = dtlb_get_data_sun4u(i);
---
> reg = dtlb_get_data_sun4u(tlb_locked, i);
414c428,429
< reg = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
---
> reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
> ASI_ITLB_TAG_READ_REG);
417c432
< reg = itlb_get_data_sun4u(i);
---
> reg = itlb_get_data_sun4u(tlb_locked, i);
461c476
< data = itlb_get_data_sun4u(0);
---
> data = itlb_get_data_sun4u(tlb_locked, 0);
468c483
< tag = ldxa(TLB_DAR_SLOT(0), ASI_ITLB_TAG_READ_REG);
---
> tag = ldxa(TLB_DAR_SLOT(tlb_locked, 0), ASI_ITLB_TAG_READ_REG);
478c493
< if ((itlb_get_data_sun4u(i) & TD_V) != 0)
---
> if ((itlb_get_data_sun4u(tlb_locked, i) & TD_V) != 0)
482c497,498
< stxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, data);
---
> stxa(TLB_DAR_SLOT(tlb_locked, i), ASI_ITLB_DATA_ACCESS_REG,
> data);
653a670,689
> switch (cpu_impl) {
> case CPU_IMPL_SPARC64:
> case CPU_IMPL_ULTRASPARCI:
> case CPU_IMPL_ULTRASPARCII:
> case CPU_IMPL_ULTRASPARCIIi:
> case CPU_IMPL_ULTRASPARCIIe:
> tlb_locked = TLB_DAR_T32;
> break;
> case CPU_IMPL_ULTRASPARCIII:
> case CPU_IMPL_ULTRASPARCIIIp:
> case CPU_IMPL_ULTRASPARCIIIi:
> case CPU_IMPL_ULTRASPARCIIIip:
> case CPU_IMPL_ULTRASPARCIV:
> case CPU_IMPL_ULTRASPARCIVp:
> tlb_locked = TLB_DAR_T16;
> break;
> case CPU_IMPL_SPARC64V:
> tlb_locked = TLB_DAR_FTLB;
> break;
> }
824c860
< tte = itlb_get_data_sun4u(i);
---
> tte = itlb_get_data_sun4u(tlb_locked, i);
828c864,865
< tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
---
> tag = ldxa(TLB_DAR_SLOT(tlb_locked, i),
> ASI_ITLB_TAG_READ_REG);
834c871
< tte = dtlb_get_data_sun4u(i);
---
> tte = dtlb_get_data_sun4u(tlb_locked, i);
838c875,876
< tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
---
> tag = ldxa(TLB_DAR_SLOT(tlb_locked, i),
> ASI_DTLB_TAG_READ_REG);