1/*-
2 * Copyright (c) 2006 Olivier Houchard
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
| 1/*-
2 * Copyright (c) 2006 Olivier Houchard
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
|
28
29#ifndef I83142_REG_H_
30#define I83142_REG_H_
31/* Physical Memory Map */
32/*
33 * 0x000000000 - 0x07FFFFFFF SDRAM
34 * 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window
35 * 0x0F0000000 - 0x0F1FFFFFF Flash
36 * 0x0F2000000 - 0x0F20FFFFF PCE1
37 * 0x0F3000000 - 0x0FFCFFFFF Compact Flash
38 * 0x0FFD00000 - 0x0FFDFFFFF MMR
39 * 0x0FFFB0000 - 0x0FFFBFFFF ATU-X Outbound I/O Window
40 * 0x0FFFD0000 - 0x0FFFDFFFF ATUe Outbound I/O Window
41 * 0x100000000 - 0x1FFFFFFFF ATU-X outbound Memory Translation Window
42 * 0x2FF000000 - 0x2FFFFFFFF ATUe Outbound Memory Translation Window
43 */
44
45#define IOP34X_VADDR 0xf0000000
46#define IOP34X_HWADDR 0xffd00000
47#define IOP34X_SIZE 0x100000
48
49#define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */
50#define IOP34X_PBBAR0_ADDRMASK 0xfffff000
51#define IOP34X_PBBAR1 0x81590
| 28
29#ifndef I83142_REG_H_
30#define I83142_REG_H_
31/* Physical Memory Map */
32/*
33 * 0x000000000 - 0x07FFFFFFF SDRAM
34 * 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window
35 * 0x0F0000000 - 0x0F1FFFFFF Flash
36 * 0x0F2000000 - 0x0F20FFFFF PCE1
37 * 0x0F3000000 - 0x0FFCFFFFF Compact Flash
38 * 0x0FFD00000 - 0x0FFDFFFFF MMR
39 * 0x0FFFB0000 - 0x0FFFBFFFF ATU-X Outbound I/O Window
40 * 0x0FFFD0000 - 0x0FFFDFFFF ATUe Outbound I/O Window
41 * 0x100000000 - 0x1FFFFFFFF ATU-X outbound Memory Translation Window
42 * 0x2FF000000 - 0x2FFFFFFFF ATUe Outbound Memory Translation Window
43 */
44
45#define IOP34X_VADDR 0xf0000000
46#define IOP34X_HWADDR 0xffd00000
47#define IOP34X_SIZE 0x100000
48
49#define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */
50#define IOP34X_PBBAR0_ADDRMASK 0xfffff000
51#define IOP34X_PBBAR1 0x81590
|
52#define IOP34X_ESSTSR0 0x82188
53#define IOP34X_CONTROLLER_ONLY (1 << 14)
54#define IOP34X_INT_SEL_PCIX (1 << 15)
55#define IOP34X_PFR 0x82180 /* Processor Frequency Register */
56#define IOP34X_FREQ_MASK ((1 << 16) | (1 << 17) | (1 << 18))
57#define IOP34X_FREQ_600 (0)
58#define IOP34X_FREQ_667 (1 << 16)
59#define IOP34X_FREQ_800 (1 << 17)
60#define IOP34X_FREQ_833 ((1 << 17) | (1 << 16))
61#define IOP34X_FREQ_1000 (1 << 18)
62#define IOP34X_FREQ_1200 ((1 << 16) | (1 << 18))
63
64#define IOP34X_UART0_VADDR IOP34X_VADDR + 0x82300
65#define IOP34X_UART0_HWADDR IOP34X_HWADDR + 0x82300
66#define IOP34X_UART1_VADDR IOP34X_VADDR + 0x82340
67#define IOP34X_UART1_HWADDR IOP34X_HWADDR + 0x82340
68#define IOP34X_PBI_HWADDR 0xffd81580
69
70/* SDRAM Memory Controller */
71#define SMC_SDBR 0x8180c /* Base Register */
72#define SMC_SDBR_BASEADDR (1 << 27)
73#define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
74 | (1 << 31))
75#define SMC_SDUBR 0x81810 /* Upper Base Register */
76#define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */
77#define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks
78 0 => 2 Banks
79 1 => 1 Bank
80 */
81#define SMC_SBSR_BANK_SZ (1 << 27) /* SDRAM Bank Size :
82 0x00000 Empty
83 0x00001 128MB
84 0x00010 256MB
85 0x00100 512MB
86 0x01000 1GB
87 */
88#define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
89 | (1 << 31))
90
91
92/* Two possible addresses for ATUe depending on configuration. */
93#define IOP34X_ATUE_ADDR(esstrsr) ((((esstrsr) & (IOP34X_CONTROLLER_ONLY | \
94 IOP34X_INT_SEL_PCIX)) == (IOP34X_CONTROLLER_ONLY | IOP34X_INT_SEL_PCIX)) ? \
95 0xffdc8000 : 0xffdcd000)
96
97/* Three possible addresses for ATU-X depending on configuration. */
98#define IOP34X_ATUX_ADDR(esstrsr) (!((esstrsr) & IOP34X_CONTROLLER_ONLY) ? \
99 0xffdcc000 : !((esstrsr) & IOP34X_INT_SEL_PCIX) ? 0xffdc8000 : 0xffdcd000)
100
101#define IOP34X_OIOBAR_SIZE 0x10000
102#define IOP34X_PCIX_OIOBAR 0xfffb0000
103#define IOP34X_PCIX_OIOBAR_VADDR 0xf01b0000
104#define IOP34X_PCIX_OMBAR 0x100000000
105#define IOP34X_PCIE_OIOBAR 0xfffd0000
106#define IOP34X_PCIE_OIOBAR_VADDR 0xf01d0000
107#define IOP34X_PCIE_OMBAR 0x200000000
108
109/* ATU Registers */
110/* Common for ATU-X and ATUe */
111#define ATU_VID 0x0000 /* ATU Vendor ID */
112#define ATU_DID 0x0002 /* ATU Device ID */
113#define ATU_CMD 0x0004 /* ATU Command Register */
114#define ATU_SR 0x0006 /* ATU Status Register */
115#define ATU_RID 0x0008 /* ATU Revision ID */
116#define ATU_CCR 0x0009 /* ATU Class Code */
117#define ATU_CLSR 0x000c /* ATU Cacheline Size */
118#define ATU_LT 0x000d /* ATU Latency Timer */
119#define ATU_HTR 0x000e /* ATU Header Type */
120#define ATU_BISTR 0x000f /* ATU BIST Register */
121#define ATU_IABAR0 0x0010 /* Inbound ATU Base Address register 0 */
122#define ATU_IAUBAR0 0x0014 /* Inbound ATU Upper Base Address Register 0 */
123#define ATU_IABAR1 0x0018 /* Inbound ATU Base Address Register 1 */
124#define ATU_IAUBAR1 0x001c /* Inbound ATU Upper Base Address Register 1 */
125#define ATU_IABAR2 0x0020 /* Inbound ATU Base Address Register 2 */
126#define ATU_IAUBAR2 0x0024 /* Inbound ATU Upper Base Address Register 2 */
127#define ATU_VSIR 0x002c /* ATU Subsystem Vendor ID Register */
128#define ATU_SIR 0x002e /* ATU Subsystem ID Register */
129#define ATU_ERBAR 0x0030 /* Expansion ROM Base Address Register */
130#define ATU_CAPPTR 0x0034 /* ATU Capabilities Pointer Register */
131#define ATU_ILR 0x003c /* ATU Interrupt Line Register */
132#define ATU_IPR 0x003d /* ATU Interrupt Pin Register */
133#define ATU_MGNT 0x003e /* ATU Minimum Grand Register */
134#define ATU_MLAT 0x003f /* ATU Maximum Latency Register */
135#define ATU_IALR0 0x0040 /* Inbound ATU Limit Register 0 */
136#define ATU_IATVR0 0x0044 /* Inbound ATU Translate Value Register 0 */
137#define ATU_IAUTVR0 0x0048 /* Inbound ATU Upper Translate Value Register 0*/
138#define ATU_IALR1 0x004c /* Inbound ATU Limit Register 1 */
139#define ATU_IATVR1 0x0050 /* Inbound ATU Translate Value Register 1 */
140#define ATU_IAUTVR1 0x0054 /* Inbound ATU Upper Translate Value Register 1*/
141#define ATU_IALR2 0x0058 /* Inbound ATU Limit Register 2 */
142#define ATU_IATVR2 0x005c /* Inbound ATU Translate Value Register 2 */
143#define ATU_IAUTVR2 0x0060 /* Inbound ATU Upper Translate Value Register 2*/
144#define ATU_ERLR 0x0064 /* Expansion ROM Limit Register */
145#define ATU_ERTVR 0x0068 /* Expansion ROM Translater Value Register */
146#define ATU_ERUTVR 0x006c /* Expansion ROM Upper Translate Value Register*/
147#define ATU_CR 0x0070 /* ATU Configuration Register */
148#define ATU_CR_OUT_EN (1 << 1)
149#define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */
150#define PCIE_BUSNO(x) ((x & 0xff000000) >> 24)
151#define ATUX_CORE_RST ((1 << 30) | (1 << 31)) /* Core Processor Reset */
152#define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */
153#define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */
154#define ATU_ISR 0x0078 /* ATU Interrupt Status Register */
155#define ATUX_ISR_PIE (1 << 18) /* PCI Interface error */
156#define ATUX_ISR_IBPR (1 << 16) /* Internal Bus Parity Error */
157#define ATUX_ISR_DCE (1 << 14) /* Detected Correctable error */
158#define ATUX_ISR_ISCE (1 << 13) /* Initiated Split Completion Error Msg */
159#define ATUX_ISR_RSCE (1 << 12) /* Received Split Completion Error Msg */
160#define ATUX_ISR_DPE (1 << 9) /* Detected Parity Error */
161#define ATUX_ISR_IBMA (1 << 7) /* Internal Bus Master Abort */
162#define ATUX_ISR_PMA (1 << 3) /* PCI Master Abort */
163#define ATUX_ISR_PTAM (1 << 2) /* PCI Target Abort (Master) */
164#define ATUX_ISR_PTAT (1 << 1) /* PCI Target Abort (Target) */
165#define ATUX_ISR_PMPE (1 << 0) /* PCI Master Parity Error */
166#define ATUX_ISR_ERRMSK (ATUX_ISR_PIE | ATUX_ISR_IBPR | ATUX_ISR_DCE | \
167 ATUX_ISR_ISCE | ATUX_ISR_RSCE | ATUX_ISR_DPE | ATUX_ISR_IBMA | ATUX_ISR_PMA\
168 | ATUX_ISR_PTAM | ATUX_ISR_PTAT | ATUX_ISR_PMPE)
169#define ATUE_ISR_HON (1 << 13) /* Halt on Error Interrupt */
170#define ATUE_ISR_RSE (1 << 12) /* Root System Error Message */
171#define ATUE_ISR_REM (1 << 11) /* Root Error Message */
172#define ATUE_ISR_PIE (1 << 10) /* PCI Interface error */
173#define ATUE_ISR_CEM (1 << 9) /* Correctable Error Message */
174#define ATUE_ISR_UEM (1 << 8) /* Uncorrectable error message */
175#define ATUE_ISR_CRS (1 << 7) /* Received Configuration Retry Status */
176#define ATUE_ISR_IBMA (1 << 5) /* Internal Bus Master Abort */
177#define ATUE_ISR_DPE (1 << 4) /* Detected Parity Error Interrupt */
178#define ATUE_ISR_MAI (1 << 3) /* Received Master Abort Interrupt */
179#define ATUE_ISR_STAI (1 << 2) /* Signaled Target Abort Interrupt */
180#define ATUE_ISR_TAI (1 << 1) /* Received Target Abort Interrupt */
181#define ATUE_ISR_MDPE (1 << 0) /* Master Data Parity Error Interrupt */
182#define ATUE_ISR_ERRMSK (ATUE_ISR_HON | ATUE_ISR_RSE | ATUE_ISR_REM | \
183 ATUE_ISR_PIE | ATUE_ISR_CEM | ATUE_ISR_UEM | ATUE_ISR_CRS | ATUE_ISR_IBMA |\
184 ATUE_ISR_DPE | ATUE_ISR_MAI | ATUE_ISR_STAI | ATUE_ISR_TAI | ATUE_ISR_MDPE)
185#define ATU_IMR 0x007c /* ATU Interrupt Mask Register */
186/* 0x0080 - 0x008f reserved */
187#define ATU_VPDCID 0x0090 /* VPD Capability Identifier Register */
188#define ATU_VPDNIP 0x0091 /* VPD Next Item Pointer Register */
189#define ATU_VPDAR 0x0092 /* VPD Address Register */
190#define ATU_VPDDR 0x0094 /* VPD Data Register */
191#define ATU_PMCID 0x0098 /* PM Capability Identifier Register */
192#define ATU_PMNIPR 0x0099 /* PM Next Item Pointer Register */
193#define ATU_PMCR 0x009a /* ATU Power Management Capabilities Register */
194#define ATU_PMCSR 0x009c /* ATU Power Management Control/Status Register*/
195#define ATU_MSICIR 0x00a0 /* MSI Capability Identifier Register */
196#define ATU_MSINIPR 0x00a1 /* MSI Next Item Pointer Register */
197#define ATU_MCR 0x00a2 /* Message Control Register */
198#define ATU_MAR 0x00a4 /* Message Address Register */
199#define ATU_MUAR 0x00a8 /* Message Upper Address Register */
200#define ATU_MDR 0x00ac /* Message Data Register */
201#define ATU_PCIXSR 0x00d4 /* PCI-X Status Register */
202#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8)
203#define ATU_IABAR3 0x0200 /* Inbound ATU Base Address Register 3 */
204#define ATU_IAUBAR3 0x0204 /* Inbound ATU Upper Base Address Register 3 */
205#define ATU_IALR3 0x0208 /* Inbound ATU Limit Register 3 */
206#define ATU_ITVR3 0x020c /* Inbound ATU Upper Translate Value Reg 3 */
207#define ATU_OIOBAR 0x0300 /* Outbound I/O Base Address Register */
208#define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */
209#define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/
210#define ATU_OUMBAR_FUNC (28)
211#define ATU_OUMBAR_EN (1 << 31)
212#define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */
213#define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/
214#define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */
215#define ATU_OUMBAR2 0x0318 /* Outbound Upper Memory Window base addr reg2*/
216#define ATU_OUMWTVR2 0x031c /* Outbount Upper 32bit Memory Window Translate Value Register 2 */
217#define ATU_OUMBAR3 0x0320 /* Outbound Upper Memory Window base addr reg3*/
218#define ATU_OUMWTVR3 0x0324 /* Outbound Upper 32bit Memory Window Translate Value Register 3 */
219
220/* ATU-X specific */
221#define ATUX_OCCAR 0x0330 /* Outbound Configuration Cycle Address Reg */
222#define ATUX_OCCDR 0x0334 /* Outbound Configuration Cycle Data Reg */
223#define ATUX_OCCFN 0x0338 /* Outbound Configuration Cycle Function Number*/
224/* ATUe specific */
225#define ATUE_OCCAR 0x032c /* Outbound Configuration Cycle Address Reg */
226#define ATUE_OCCDR 0x0330 /* Outbound Configuration Cycle Data Reg */
227#define ATUE_OCCFN 0x0334 /* Outbound Configuration Cycle Function Number*/
228/* Interrupts */
229
230/* IINTRSRC0 */
231#define ICU_INT_ADMA0_EOT (0) /* ADMA 0 End of transfer */
232#define ICU_INT_ADMA0_EOC (1) /* ADMA 0 End of Chain */
233#define ICU_INT_ADMA1_EOT (2) /* ADMA 1 End of transfer */
234#define ICU_INT_ADMA1_EOC (3) /* ADMA 1 End of chain */
235#define ICU_INT_ADMA2_EOT (4) /* ADMA 2 End of transfer */
236#define ICU_INT_ADMA2_EOC (5) /* ADMA 2 end of chain */
237#define ICU_INT_WDOG (6) /* Watchdog timer */
238/* 7 Reserved */
239#define ICU_INT_TIMER0 (8) /* Timer 0 */
240#define ICU_INT_TIMER1 (9) /* Timer 1 */
241#define ICU_INT_I2C0 (10) /* I2C bus interface 0 */
242#define ICU_INT_I2C1 (11) /* I2C bus interface 1 */
243#define ICU_INT_MU (12) /* Message Unit */
244#define ICU_INT_MU_IPQ (13) /* Message unit inbound post queue */
245#define ICU_INT_ATUE_IM (14) /* ATU-E inbound message */
246#define ICU_INT_ATU_BIST (15) /* ATU/Start BIST */
247#define ICU_INT_PMC (16) /* PMC */
248#define ICU_INT_PMU (17) /* PMU */
249#define ICU_INT_PC (18) /* Processor cache */
250/* 19-23 Reserved */
251#define ICU_INT_XINT0 (24)
252#define ICU_INT_XINT1 (25)
253#define ICU_INT_XINT2 (26)
254#define ICU_INT_XINT3 (27)
255#define ICU_INT_XINT4 (28)
256#define ICU_INT_XINT5 (29)
257#define ICU_INT_XINT6 (30)
258#define ICU_INT_XINT7 (31)
259/* IINTSRC1 */
260#define ICU_INT_XINT8 (32)
261#define ICU_INT_XINT9 (33)
262#define ICU_INT_XINT10 (34)
263#define ICU_INT_XINT11 (35)
264#define ICU_INT_XINT12 (36)
265#define ICU_INT_XINT13 (37)
266#define ICU_INT_XINT14 (38)
267#define ICU_INT_XINT15 (39)
268/* 40-50 reserved */
269#define ICU_INT_UART0 (51) /* UART 0 */
270#define ICU_INT_UART1 (52) /* UART 1 */
271#define ICU_INT_PBIUE (53) /* Peripheral bus interface unit error */
272#define ICU_INT_ATUCRW (54) /* ATU Configuration register write */
273#define ICU_INT_ATUE (55) /* ATU error */
274#define ICU_INT_MCUE (56) /* Memory controller unit error */
275#define ICU_INT_ADMA0E (57) /* ADMA Channel 0 error */
276#define ICU_INT_ADMA1E (58) /* ADMA Channel 1 error */
277#define ICU_INT_ADMA2E (59) /* ADMA Channel 2 error */
278/* 60-61 reserved */
279#define ICU_INT_MUE (62) /* Messaging Unit Error */
280/* 63 reserved */
281
282/* IINTSRC2 */
283#define ICU_INT_IP (64) /* Inter-processor */
284/* 65-93 reserved */
285#define ICU_INT_SIBBE (94) /* South internal bus bridge error */
286/* 95 reserved */
287
288/* IINTSRC3 */
289#define ICU_INT_I2C2 (96) /* I2C bus interface 2 */
290#define ICU_INT_ATUE_BIST (97) /* ATU-E/Start BIST */
291#define ICU_INT_ATUE_CRW (98) /* ATU-E Configuration register write */
292#define ICU_INT_ATUEE (99) /* ATU-E Error */
293#define ICU_INT_IMU (100) /* IMU */
294/* 101-106 reserved */
295#define ICU_INT_ATUE_MA (107) /* ATUE Interrupt message A */
296#define ICU_INT_ATUE_MB (108) /* ATUE Interrupt message B */
297#define ICU_INT_ATUE_MC (109) /* ATUE Interrupt message C */
298#define ICU_INT_ATUE_MD (110) /* ATUE Interrupt message D */
299#define ICU_INT_MU_MSIX_TW (111) /* MU MSI-X Table write */
300/* 112 reserved */
301#define ICU_INT_IMSI (113) /* Inbound MSI */
302/* 114-126 reserved */
303#define ICU_INT_HPI (127) /* HPI */
304
305
306#endif /* I81342_REG_H_ */
| 55#define IOP34X_ESSTSR0 0x82188
56#define IOP34X_CONTROLLER_ONLY (1 << 14)
57#define IOP34X_INT_SEL_PCIX (1 << 15)
58#define IOP34X_PFR 0x82180 /* Processor Frequency Register */
59#define IOP34X_FREQ_MASK ((1 << 16) | (1 << 17) | (1 << 18))
60#define IOP34X_FREQ_600 (0)
61#define IOP34X_FREQ_667 (1 << 16)
62#define IOP34X_FREQ_800 (1 << 17)
63#define IOP34X_FREQ_833 ((1 << 17) | (1 << 16))
64#define IOP34X_FREQ_1000 (1 << 18)
65#define IOP34X_FREQ_1200 ((1 << 16) | (1 << 18))
66
67#define IOP34X_UART0_VADDR IOP34X_VADDR + 0x82300
68#define IOP34X_UART0_HWADDR IOP34X_HWADDR + 0x82300
69#define IOP34X_UART1_VADDR IOP34X_VADDR + 0x82340
70#define IOP34X_UART1_HWADDR IOP34X_HWADDR + 0x82340
71#define IOP34X_PBI_HWADDR 0xffd81580
72
73/* SDRAM Memory Controller */
74#define SMC_SDBR 0x8180c /* Base Register */
75#define SMC_SDBR_BASEADDR (1 << 27)
76#define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
77 | (1 << 31))
78#define SMC_SDUBR 0x81810 /* Upper Base Register */
79#define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */
80#define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks
81 0 => 2 Banks
82 1 => 1 Bank
83 */
84#define SMC_SBSR_BANK_SZ (1 << 27) /* SDRAM Bank Size :
85 0x00000 Empty
86 0x00001 128MB
87 0x00010 256MB
88 0x00100 512MB
89 0x01000 1GB
90 */
91#define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
92 | (1 << 31))
93
94
95/* Two possible addresses for ATUe depending on configuration. */
96#define IOP34X_ATUE_ADDR(esstrsr) ((((esstrsr) & (IOP34X_CONTROLLER_ONLY | \
97 IOP34X_INT_SEL_PCIX)) == (IOP34X_CONTROLLER_ONLY | IOP34X_INT_SEL_PCIX)) ? \
98 0xffdc8000 : 0xffdcd000)
99
100/* Three possible addresses for ATU-X depending on configuration. */
101#define IOP34X_ATUX_ADDR(esstrsr) (!((esstrsr) & IOP34X_CONTROLLER_ONLY) ? \
102 0xffdcc000 : !((esstrsr) & IOP34X_INT_SEL_PCIX) ? 0xffdc8000 : 0xffdcd000)
103
104#define IOP34X_OIOBAR_SIZE 0x10000
105#define IOP34X_PCIX_OIOBAR 0xfffb0000
106#define IOP34X_PCIX_OIOBAR_VADDR 0xf01b0000
107#define IOP34X_PCIX_OMBAR 0x100000000
108#define IOP34X_PCIE_OIOBAR 0xfffd0000
109#define IOP34X_PCIE_OIOBAR_VADDR 0xf01d0000
110#define IOP34X_PCIE_OMBAR 0x200000000
111
112/* ATU Registers */
113/* Common for ATU-X and ATUe */
114#define ATU_VID 0x0000 /* ATU Vendor ID */
115#define ATU_DID 0x0002 /* ATU Device ID */
116#define ATU_CMD 0x0004 /* ATU Command Register */
117#define ATU_SR 0x0006 /* ATU Status Register */
118#define ATU_RID 0x0008 /* ATU Revision ID */
119#define ATU_CCR 0x0009 /* ATU Class Code */
120#define ATU_CLSR 0x000c /* ATU Cacheline Size */
121#define ATU_LT 0x000d /* ATU Latency Timer */
122#define ATU_HTR 0x000e /* ATU Header Type */
123#define ATU_BISTR 0x000f /* ATU BIST Register */
124#define ATU_IABAR0 0x0010 /* Inbound ATU Base Address register 0 */
125#define ATU_IAUBAR0 0x0014 /* Inbound ATU Upper Base Address Register 0 */
126#define ATU_IABAR1 0x0018 /* Inbound ATU Base Address Register 1 */
127#define ATU_IAUBAR1 0x001c /* Inbound ATU Upper Base Address Register 1 */
128#define ATU_IABAR2 0x0020 /* Inbound ATU Base Address Register 2 */
129#define ATU_IAUBAR2 0x0024 /* Inbound ATU Upper Base Address Register 2 */
130#define ATU_VSIR 0x002c /* ATU Subsystem Vendor ID Register */
131#define ATU_SIR 0x002e /* ATU Subsystem ID Register */
132#define ATU_ERBAR 0x0030 /* Expansion ROM Base Address Register */
133#define ATU_CAPPTR 0x0034 /* ATU Capabilities Pointer Register */
134#define ATU_ILR 0x003c /* ATU Interrupt Line Register */
135#define ATU_IPR 0x003d /* ATU Interrupt Pin Register */
136#define ATU_MGNT 0x003e /* ATU Minimum Grand Register */
137#define ATU_MLAT 0x003f /* ATU Maximum Latency Register */
138#define ATU_IALR0 0x0040 /* Inbound ATU Limit Register 0 */
139#define ATU_IATVR0 0x0044 /* Inbound ATU Translate Value Register 0 */
140#define ATU_IAUTVR0 0x0048 /* Inbound ATU Upper Translate Value Register 0*/
141#define ATU_IALR1 0x004c /* Inbound ATU Limit Register 1 */
142#define ATU_IATVR1 0x0050 /* Inbound ATU Translate Value Register 1 */
143#define ATU_IAUTVR1 0x0054 /* Inbound ATU Upper Translate Value Register 1*/
144#define ATU_IALR2 0x0058 /* Inbound ATU Limit Register 2 */
145#define ATU_IATVR2 0x005c /* Inbound ATU Translate Value Register 2 */
146#define ATU_IAUTVR2 0x0060 /* Inbound ATU Upper Translate Value Register 2*/
147#define ATU_ERLR 0x0064 /* Expansion ROM Limit Register */
148#define ATU_ERTVR 0x0068 /* Expansion ROM Translater Value Register */
149#define ATU_ERUTVR 0x006c /* Expansion ROM Upper Translate Value Register*/
150#define ATU_CR 0x0070 /* ATU Configuration Register */
151#define ATU_CR_OUT_EN (1 << 1)
152#define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */
153#define PCIE_BUSNO(x) ((x & 0xff000000) >> 24)
154#define ATUX_CORE_RST ((1 << 30) | (1 << 31)) /* Core Processor Reset */
155#define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */
156#define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */
157#define ATU_ISR 0x0078 /* ATU Interrupt Status Register */
158#define ATUX_ISR_PIE (1 << 18) /* PCI Interface error */
159#define ATUX_ISR_IBPR (1 << 16) /* Internal Bus Parity Error */
160#define ATUX_ISR_DCE (1 << 14) /* Detected Correctable error */
161#define ATUX_ISR_ISCE (1 << 13) /* Initiated Split Completion Error Msg */
162#define ATUX_ISR_RSCE (1 << 12) /* Received Split Completion Error Msg */
163#define ATUX_ISR_DPE (1 << 9) /* Detected Parity Error */
164#define ATUX_ISR_IBMA (1 << 7) /* Internal Bus Master Abort */
165#define ATUX_ISR_PMA (1 << 3) /* PCI Master Abort */
166#define ATUX_ISR_PTAM (1 << 2) /* PCI Target Abort (Master) */
167#define ATUX_ISR_PTAT (1 << 1) /* PCI Target Abort (Target) */
168#define ATUX_ISR_PMPE (1 << 0) /* PCI Master Parity Error */
169#define ATUX_ISR_ERRMSK (ATUX_ISR_PIE | ATUX_ISR_IBPR | ATUX_ISR_DCE | \
170 ATUX_ISR_ISCE | ATUX_ISR_RSCE | ATUX_ISR_DPE | ATUX_ISR_IBMA | ATUX_ISR_PMA\
171 | ATUX_ISR_PTAM | ATUX_ISR_PTAT | ATUX_ISR_PMPE)
172#define ATUE_ISR_HON (1 << 13) /* Halt on Error Interrupt */
173#define ATUE_ISR_RSE (1 << 12) /* Root System Error Message */
174#define ATUE_ISR_REM (1 << 11) /* Root Error Message */
175#define ATUE_ISR_PIE (1 << 10) /* PCI Interface error */
176#define ATUE_ISR_CEM (1 << 9) /* Correctable Error Message */
177#define ATUE_ISR_UEM (1 << 8) /* Uncorrectable error message */
178#define ATUE_ISR_CRS (1 << 7) /* Received Configuration Retry Status */
179#define ATUE_ISR_IBMA (1 << 5) /* Internal Bus Master Abort */
180#define ATUE_ISR_DPE (1 << 4) /* Detected Parity Error Interrupt */
181#define ATUE_ISR_MAI (1 << 3) /* Received Master Abort Interrupt */
182#define ATUE_ISR_STAI (1 << 2) /* Signaled Target Abort Interrupt */
183#define ATUE_ISR_TAI (1 << 1) /* Received Target Abort Interrupt */
184#define ATUE_ISR_MDPE (1 << 0) /* Master Data Parity Error Interrupt */
185#define ATUE_ISR_ERRMSK (ATUE_ISR_HON | ATUE_ISR_RSE | ATUE_ISR_REM | \
186 ATUE_ISR_PIE | ATUE_ISR_CEM | ATUE_ISR_UEM | ATUE_ISR_CRS | ATUE_ISR_IBMA |\
187 ATUE_ISR_DPE | ATUE_ISR_MAI | ATUE_ISR_STAI | ATUE_ISR_TAI | ATUE_ISR_MDPE)
188#define ATU_IMR 0x007c /* ATU Interrupt Mask Register */
189/* 0x0080 - 0x008f reserved */
190#define ATU_VPDCID 0x0090 /* VPD Capability Identifier Register */
191#define ATU_VPDNIP 0x0091 /* VPD Next Item Pointer Register */
192#define ATU_VPDAR 0x0092 /* VPD Address Register */
193#define ATU_VPDDR 0x0094 /* VPD Data Register */
194#define ATU_PMCID 0x0098 /* PM Capability Identifier Register */
195#define ATU_PMNIPR 0x0099 /* PM Next Item Pointer Register */
196#define ATU_PMCR 0x009a /* ATU Power Management Capabilities Register */
197#define ATU_PMCSR 0x009c /* ATU Power Management Control/Status Register*/
198#define ATU_MSICIR 0x00a0 /* MSI Capability Identifier Register */
199#define ATU_MSINIPR 0x00a1 /* MSI Next Item Pointer Register */
200#define ATU_MCR 0x00a2 /* Message Control Register */
201#define ATU_MAR 0x00a4 /* Message Address Register */
202#define ATU_MUAR 0x00a8 /* Message Upper Address Register */
203#define ATU_MDR 0x00ac /* Message Data Register */
204#define ATU_PCIXSR 0x00d4 /* PCI-X Status Register */
205#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8)
206#define ATU_IABAR3 0x0200 /* Inbound ATU Base Address Register 3 */
207#define ATU_IAUBAR3 0x0204 /* Inbound ATU Upper Base Address Register 3 */
208#define ATU_IALR3 0x0208 /* Inbound ATU Limit Register 3 */
209#define ATU_ITVR3 0x020c /* Inbound ATU Upper Translate Value Reg 3 */
210#define ATU_OIOBAR 0x0300 /* Outbound I/O Base Address Register */
211#define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */
212#define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/
213#define ATU_OUMBAR_FUNC (28)
214#define ATU_OUMBAR_EN (1 << 31)
215#define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */
216#define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/
217#define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */
218#define ATU_OUMBAR2 0x0318 /* Outbound Upper Memory Window base addr reg2*/
219#define ATU_OUMWTVR2 0x031c /* Outbount Upper 32bit Memory Window Translate Value Register 2 */
220#define ATU_OUMBAR3 0x0320 /* Outbound Upper Memory Window base addr reg3*/
221#define ATU_OUMWTVR3 0x0324 /* Outbound Upper 32bit Memory Window Translate Value Register 3 */
222
223/* ATU-X specific */
224#define ATUX_OCCAR 0x0330 /* Outbound Configuration Cycle Address Reg */
225#define ATUX_OCCDR 0x0334 /* Outbound Configuration Cycle Data Reg */
226#define ATUX_OCCFN 0x0338 /* Outbound Configuration Cycle Function Number*/
227/* ATUe specific */
228#define ATUE_OCCAR 0x032c /* Outbound Configuration Cycle Address Reg */
229#define ATUE_OCCDR 0x0330 /* Outbound Configuration Cycle Data Reg */
230#define ATUE_OCCFN 0x0334 /* Outbound Configuration Cycle Function Number*/
231/* Interrupts */
232
233/* IINTRSRC0 */
234#define ICU_INT_ADMA0_EOT (0) /* ADMA 0 End of transfer */
235#define ICU_INT_ADMA0_EOC (1) /* ADMA 0 End of Chain */
236#define ICU_INT_ADMA1_EOT (2) /* ADMA 1 End of transfer */
237#define ICU_INT_ADMA1_EOC (3) /* ADMA 1 End of chain */
238#define ICU_INT_ADMA2_EOT (4) /* ADMA 2 End of transfer */
239#define ICU_INT_ADMA2_EOC (5) /* ADMA 2 end of chain */
240#define ICU_INT_WDOG (6) /* Watchdog timer */
241/* 7 Reserved */
242#define ICU_INT_TIMER0 (8) /* Timer 0 */
243#define ICU_INT_TIMER1 (9) /* Timer 1 */
244#define ICU_INT_I2C0 (10) /* I2C bus interface 0 */
245#define ICU_INT_I2C1 (11) /* I2C bus interface 1 */
246#define ICU_INT_MU (12) /* Message Unit */
247#define ICU_INT_MU_IPQ (13) /* Message unit inbound post queue */
248#define ICU_INT_ATUE_IM (14) /* ATU-E inbound message */
249#define ICU_INT_ATU_BIST (15) /* ATU/Start BIST */
250#define ICU_INT_PMC (16) /* PMC */
251#define ICU_INT_PMU (17) /* PMU */
252#define ICU_INT_PC (18) /* Processor cache */
253/* 19-23 Reserved */
254#define ICU_INT_XINT0 (24)
255#define ICU_INT_XINT1 (25)
256#define ICU_INT_XINT2 (26)
257#define ICU_INT_XINT3 (27)
258#define ICU_INT_XINT4 (28)
259#define ICU_INT_XINT5 (29)
260#define ICU_INT_XINT6 (30)
261#define ICU_INT_XINT7 (31)
262/* IINTSRC1 */
263#define ICU_INT_XINT8 (32)
264#define ICU_INT_XINT9 (33)
265#define ICU_INT_XINT10 (34)
266#define ICU_INT_XINT11 (35)
267#define ICU_INT_XINT12 (36)
268#define ICU_INT_XINT13 (37)
269#define ICU_INT_XINT14 (38)
270#define ICU_INT_XINT15 (39)
271/* 40-50 reserved */
272#define ICU_INT_UART0 (51) /* UART 0 */
273#define ICU_INT_UART1 (52) /* UART 1 */
274#define ICU_INT_PBIUE (53) /* Peripheral bus interface unit error */
275#define ICU_INT_ATUCRW (54) /* ATU Configuration register write */
276#define ICU_INT_ATUE (55) /* ATU error */
277#define ICU_INT_MCUE (56) /* Memory controller unit error */
278#define ICU_INT_ADMA0E (57) /* ADMA Channel 0 error */
279#define ICU_INT_ADMA1E (58) /* ADMA Channel 1 error */
280#define ICU_INT_ADMA2E (59) /* ADMA Channel 2 error */
281/* 60-61 reserved */
282#define ICU_INT_MUE (62) /* Messaging Unit Error */
283/* 63 reserved */
284
285/* IINTSRC2 */
286#define ICU_INT_IP (64) /* Inter-processor */
287/* 65-93 reserved */
288#define ICU_INT_SIBBE (94) /* South internal bus bridge error */
289/* 95 reserved */
290
291/* IINTSRC3 */
292#define ICU_INT_I2C2 (96) /* I2C bus interface 2 */
293#define ICU_INT_ATUE_BIST (97) /* ATU-E/Start BIST */
294#define ICU_INT_ATUE_CRW (98) /* ATU-E Configuration register write */
295#define ICU_INT_ATUEE (99) /* ATU-E Error */
296#define ICU_INT_IMU (100) /* IMU */
297/* 101-106 reserved */
298#define ICU_INT_ATUE_MA (107) /* ATUE Interrupt message A */
299#define ICU_INT_ATUE_MB (108) /* ATUE Interrupt message B */
300#define ICU_INT_ATUE_MC (109) /* ATUE Interrupt message C */
301#define ICU_INT_ATUE_MD (110) /* ATUE Interrupt message D */
302#define ICU_INT_MU_MSIX_TW (111) /* MU MSI-X Table write */
303/* 112 reserved */
304#define ICU_INT_IMSI (113) /* Inbound MSI */
305/* 114-126 reserved */
306#define ICU_INT_HPI (127) /* HPI */
307
308
309#endif /* I81342_REG_H_ */
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