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if_cpswvar.h (245064) if_cpswvar.h (246276)
1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswvar.h 245064 2013-01-05 17:59:44Z kientzle $
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswvar.h 246276 2013-02-03 01:08:01Z kientzle $
27 */
28
29#ifndef _IF_CPSWVAR_H
30#define _IF_CPSWVAR_H
31
32#define CPSW_INTR_COUNT 4
33
34/* MII BUS */
35#define CPSW_MIIBUS_RETRIES 5
36#define CPSW_MIIBUS_DELAY 1000
37
27 */
28
29#ifndef _IF_CPSWVAR_H
30#define _IF_CPSWVAR_H
31
32#define CPSW_INTR_COUNT 4
33
34/* MII BUS */
35#define CPSW_MIIBUS_RETRIES 5
36#define CPSW_MIIBUS_DELAY 1000
37
38#define CPSW_MAX_TX_BUFFERS 128
39#define CPSW_MAX_RX_BUFFERS 128
40#define CPSW_MAX_ALE_ENTRIES 1024
41
38#define CPSW_MAX_ALE_ENTRIES 1024
39
40#define CPSW_SYSCTL_COUNT 34
41
42struct cpsw_slot {
42struct cpsw_slot {
43 uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
43 bus_dmamap_t dmamap;
44 struct mbuf *mbuf;
44 bus_dmamap_t dmamap;
45 struct mbuf *mbuf;
45 int index;
46 STAILQ_ENTRY(cpsw_slot) next;
47};
46 STAILQ_ENTRY(cpsw_slot) next;
47};
48STAILQ_HEAD(cpsw_queue, cpsw_slot);
48STAILQ_HEAD(cpsw_slots, cpsw_slot);
49
49
50struct cpsw_queue {
51 struct mtx lock;
52 int running;
53 struct cpsw_slots active;
54 struct cpsw_slots avail;
55 uint32_t queue_adds; /* total bufs added */
56 uint32_t queue_removes; /* total bufs removed */
57 uint32_t queue_removes_at_last_tick; /* Used by watchdog */
58 int queue_slots;
59 int active_queue_len;
60 int max_active_queue_len;
61 int avail_queue_len;
62 int max_avail_queue_len;
63 int longest_chain; /* Largest # segments in a single packet. */
64 int hdp_offset;
65};
66
50struct cpsw_softc {
51 struct ifnet *ifp;
52 phandle_t node;
53 device_t dev;
67struct cpsw_softc {
68 struct ifnet *ifp;
69 phandle_t node;
70 device_t dev;
71 struct bintime attach_uptime; /* system uptime when attach happened. */
72 struct bintime init_uptime; /* system uptime when init happened. */
73
74 /* TODO: We should set up a child structure for each port;
75 store mac, phy information, etc, in that structure. */
54 uint8_t mac_addr[ETHER_ADDR_LEN];
76 uint8_t mac_addr[ETHER_ADDR_LEN];
77
55 device_t miibus;
56 struct mii_data *mii;
78 device_t miibus;
79 struct mii_data *mii;
57 struct mtx tx_lock; /* transmitter lock */
58 struct mtx rx_lock; /* receiver lock */
59 struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
60 void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
80 /* We expect 1 memory resource and 4 interrupts from the device tree. */
81 struct resource *res[1 + CPSW_INTR_COUNT];
61
82
83 /* Interrupts get recorded here as we initialize them. */
84 /* Interrupt teardown just walks this list. */
85 struct {
86 struct resource *res;
87 void *ih_cookie;
88 const char *description;
89 } interrupts[CPSW_INTR_COUNT];
90 int interrupt_count;
91
62 uint32_t cpsw_if_flags;
63 int cpsw_media_status;
64
92 uint32_t cpsw_if_flags;
93 int cpsw_media_status;
94
65 struct callout wd_callout;
66 int tx_wd_timer;
95 struct {
96 int resets;
97 int timer;
98 struct callout callout;
99 } watchdog;
67
68 bus_dma_tag_t mbuf_dtag;
69
100
101 bus_dma_tag_t mbuf_dtag;
102
70 /* RX buffer tracking */
71 int rx_running;
72 struct cpsw_queue rx_active;
73 struct cpsw_queue rx_avail;
74 struct cpsw_slot _rx_slots[CPSW_MAX_RX_BUFFERS];
103 /* An mbuf full of nulls for TX padding. */
104 bus_dmamap_t null_mbuf_dmamap;
105 struct mbuf *null_mbuf;
106 bus_addr_t null_mbuf_paddr;
75
107
76 /* TX buffer tracking. */
77 int tx_running;
78 struct cpsw_queue tx_active;
79 struct cpsw_queue tx_avail;
80 struct cpsw_slot _tx_slots[CPSW_MAX_TX_BUFFERS];
108 /* RX and TX buffer tracking */
109 struct cpsw_queue rx, tx;
81
110
82 /* Statistics */
83 uint32_t tx_enqueues; /* total TX bufs added to queue */
84 uint32_t tx_retires; /* total TX bufs removed from queue */
85 uint32_t tx_retires_at_last_tick; /* used for watchdog */
86 /* Note: tx_queued != tx_enqueues - tx_retires
87 At driver reset, packets can be discarded
88 from TX queue without being retired. */
89 int tx_queued; /* Current bufs in TX queue */
90 int tx_max_queued;
91};
111 /* 64-bit versions of 32-bit hardware statistics counters */
112 uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
92
113
93#define CPDMA_BD_SOP (1<<15)
94#define CPDMA_BD_EOP (1<<14)
95#define CPDMA_BD_OWNER (1<<13)
96#define CPDMA_BD_EOQ (1<<12)
97#define CPDMA_BD_TDOWNCMPLT (1<<11)
98#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
99
100struct cpsw_cpdma_bd {
101 volatile uint32_t next;
102 volatile uint32_t bufptr;
103 volatile uint16_t buflen;
104 volatile uint16_t bufoff;
105 volatile uint16_t pktlen;
106 volatile uint16_t flags;
114 /* CPPI STATERAM has 512 slots for building TX/RX queues. */
115 /* TODO: Size here supposedly varies with different versions
116 of the controller. Check DaVinci specs and find a good
117 way to adjust this. One option is to have a separate
118 Device Tree parameter for number slots; another option
119 is to calculate it from the memory size in the device tree. */
120 struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
121 struct cpsw_slots avail;
107};
108
122};
123
109/* Read/Write macros */
110#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
111#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
112
113#define cpsw_cpdma_txbd_offset(i) \
114 (CPSW_CPPI_RAM_OFFSET + ((i)*16))
115#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
116 vtophys(rman_get_start(sc->res[0])))
117#define cpsw_cpdma_read_txbd(i, val) \
118 bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
119#define cpsw_cpdma_write_txbd(i, val) \
120 bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
121#define cpsw_cpdma_write_txbd_next(i, val) \
122 bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
123#define cpsw_cpdma_read_txbd_flags(i) \
124 bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
125
126#define cpsw_cpdma_rxbd_offset(i) \
127 (CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
128#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
129 vtophys(rman_get_start(sc->res[0])))
130#define cpsw_cpdma_read_rxbd(i, val) \
131 bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
132#define cpsw_cpdma_write_rxbd(i, val) \
133 bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
134#define cpsw_cpdma_write_rxbd_next(i, val) \
135 bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
136#define cpsw_cpdma_read_rxbd_flags(i) \
137 bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
138
139#endif /*_IF_CPSWVAR_H */
124#endif /*_IF_CPSWVAR_H */