1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 9 unchanged lines hidden (view full) ---
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswvar.h 245064 2013-01-05 17:59:44Z kientzle $
27 */
28
29#ifndef _IF_CPSWVAR_H
30#define _IF_CPSWVAR_H
31
32#define CPSW_INTR_COUNT 4
33
34/* MII BUS */
35#define CPSW_MIIBUS_RETRIES 5
36#define CPSW_MIIBUS_DELAY 1000
37
38#define CPSW_MAX_TX_BUFFERS 128
39#define CPSW_MAX_RX_BUFFERS 128
40#define CPSW_MAX_ALE_ENTRIES 1024
41
42struct cpsw_slot {
43 bus_dmamap_t dmamap;
44 struct mbuf *mbuf;
45 int index;
46 STAILQ_ENTRY(cpsw_slot) next;
47};
48STAILQ_HEAD(cpsw_queue, cpsw_slot);
49
50struct cpsw_softc {
51 struct ifnet *ifp;
52 phandle_t node;
53 device_t dev;
54 uint8_t mac_addr[ETHER_ADDR_LEN];
55 device_t miibus;
56 struct mii_data *mii;
57 struct mtx tx_lock; /* transmitter lock */
58 struct mtx rx_lock; /* receiver lock */
59 struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
60 void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
61
62 uint32_t cpsw_if_flags;
63 int cpsw_media_status;
64
65 struct callout wd_callout;
66 int tx_wd_timer;
67
68 bus_dma_tag_t mbuf_dtag;
69
70 /* RX buffer tracking */
71 int rx_running;
72 struct cpsw_queue rx_active;
73 struct cpsw_queue rx_avail;
74 struct cpsw_slot _rx_slots[CPSW_MAX_RX_BUFFERS];
75
76 /* TX buffer tracking. */
77 int tx_running;
78 struct cpsw_queue tx_active;
79 struct cpsw_queue tx_avail;
80 struct cpsw_slot _tx_slots[CPSW_MAX_TX_BUFFERS];
81
82 /* Statistics */
83 uint32_t tx_enqueues; /* total TX bufs added to queue */
84 uint32_t tx_retires; /* total TX bufs removed from queue */
85 uint32_t tx_retires_at_last_tick; /* used for watchdog */
86 /* Note: tx_queued != tx_enqueues - tx_retires
87 At driver reset, packets can be discarded
88 from TX queue without being retired. */
89 int tx_queued; /* Current bufs in TX queue */
90 int tx_max_queued;
91};
92
93#define CPDMA_BD_SOP (1<<15)
94#define CPDMA_BD_EOP (1<<14)
95#define CPDMA_BD_OWNER (1<<13)
96#define CPDMA_BD_EOQ (1<<12)
97#define CPDMA_BD_TDOWNCMPLT (1<<11)
98#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
99
100struct cpsw_cpdma_bd {
101 volatile uint32_t next;
102 volatile uint32_t bufptr;
103 volatile uint16_t buflen;
104 volatile uint16_t bufoff;
105 volatile uint16_t pktlen;
106 volatile uint16_t flags;
107};
108
109/* Read/Write macros */
110#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
111#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
112
113#define cpsw_cpdma_txbd_offset(i) \
114 (CPSW_CPPI_RAM_OFFSET + ((i)*16))
115#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
116 vtophys(rman_get_start(sc->res[0])))
117#define cpsw_cpdma_read_txbd(i, val) \
118 bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
119#define cpsw_cpdma_write_txbd(i, val) \
120 bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
121#define cpsw_cpdma_write_txbd_next(i, val) \
122 bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
123#define cpsw_cpdma_read_txbd_flags(i) \
124 bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
125
126#define cpsw_cpdma_rxbd_offset(i) \
127 (CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
128#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
129 vtophys(rman_get_start(sc->res[0])))
130#define cpsw_cpdma_read_rxbd(i, val) \
131 bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
132#define cpsw_cpdma_write_rxbd(i, val) \
133 bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
134#define cpsw_cpdma_write_rxbd_next(i, val) \
135 bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
136#define cpsw_cpdma_read_rxbd_flags(i) \
137 bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
138
139#endif /*_IF_CPSWVAR_H */
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 9 unchanged lines hidden (view full) ---
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswvar.h 245064 2013-01-05 17:59:44Z kientzle $
27 */
28
29#ifndef _IF_CPSWVAR_H
30#define _IF_CPSWVAR_H
31
32#define CPSW_INTR_COUNT 4
33
34/* MII BUS */
35#define CPSW_MIIBUS_RETRIES 5
36#define CPSW_MIIBUS_DELAY 1000
37
38#define CPSW_MAX_TX_BUFFERS 128
39#define CPSW_MAX_RX_BUFFERS 128
40#define CPSW_MAX_ALE_ENTRIES 1024
41
42struct cpsw_slot {
43 bus_dmamap_t dmamap;
44 struct mbuf *mbuf;
45 int index;
46 STAILQ_ENTRY(cpsw_slot) next;
47};
48STAILQ_HEAD(cpsw_queue, cpsw_slot);
49
50struct cpsw_softc {
51 struct ifnet *ifp;
52 phandle_t node;
53 device_t dev;
54 uint8_t mac_addr[ETHER_ADDR_LEN];
55 device_t miibus;
56 struct mii_data *mii;
57 struct mtx tx_lock; /* transmitter lock */
58 struct mtx rx_lock; /* receiver lock */
59 struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
60 void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
61
62 uint32_t cpsw_if_flags;
63 int cpsw_media_status;
64
65 struct callout wd_callout;
66 int tx_wd_timer;
67
68 bus_dma_tag_t mbuf_dtag;
69
70 /* RX buffer tracking */
71 int rx_running;
72 struct cpsw_queue rx_active;
73 struct cpsw_queue rx_avail;
74 struct cpsw_slot _rx_slots[CPSW_MAX_RX_BUFFERS];
75
76 /* TX buffer tracking. */
77 int tx_running;
78 struct cpsw_queue tx_active;
79 struct cpsw_queue tx_avail;
80 struct cpsw_slot _tx_slots[CPSW_MAX_TX_BUFFERS];
81
82 /* Statistics */
83 uint32_t tx_enqueues; /* total TX bufs added to queue */
84 uint32_t tx_retires; /* total TX bufs removed from queue */
85 uint32_t tx_retires_at_last_tick; /* used for watchdog */
86 /* Note: tx_queued != tx_enqueues - tx_retires
87 At driver reset, packets can be discarded
88 from TX queue without being retired. */
89 int tx_queued; /* Current bufs in TX queue */
90 int tx_max_queued;
91};
92
93#define CPDMA_BD_SOP (1<<15)
94#define CPDMA_BD_EOP (1<<14)
95#define CPDMA_BD_OWNER (1<<13)
96#define CPDMA_BD_EOQ (1<<12)
97#define CPDMA_BD_TDOWNCMPLT (1<<11)
98#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
99
100struct cpsw_cpdma_bd {
101 volatile uint32_t next;
102 volatile uint32_t bufptr;
103 volatile uint16_t buflen;
104 volatile uint16_t bufoff;
105 volatile uint16_t pktlen;
106 volatile uint16_t flags;
107};
108
109/* Read/Write macros */
110#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
111#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
112
113#define cpsw_cpdma_txbd_offset(i) \
114 (CPSW_CPPI_RAM_OFFSET + ((i)*16))
115#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
116 vtophys(rman_get_start(sc->res[0])))
117#define cpsw_cpdma_read_txbd(i, val) \
118 bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
119#define cpsw_cpdma_write_txbd(i, val) \
120 bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
121#define cpsw_cpdma_write_txbd_next(i, val) \
122 bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
123#define cpsw_cpdma_read_txbd_flags(i) \
124 bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
125
126#define cpsw_cpdma_rxbd_offset(i) \
127 (CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
128#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
129 vtophys(rman_get_start(sc->res[0])))
130#define cpsw_cpdma_read_rxbd(i, val) \
131 bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
132#define cpsw_cpdma_write_rxbd(i, val) \
133 bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
134#define cpsw_cpdma_write_rxbd_next(i, val) \
135 bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
136#define cpsw_cpdma_read_rxbd_flags(i) \
137 bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
138
139#endif /*_IF_CPSWVAR_H */