| if_cpswreg.h (244939) | if_cpswreg.h (246276) |
|---|---|
| 1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 244939 2013-01-01 18:55:04Z kientzle $ | 26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 246276 2013-02-03 01:08:01Z kientzle $ |
| 27 */ 28 29#ifndef _IF_CPSWREG_H 30#define _IF_CPSWREG_H 31 32#define CPSW_SS_OFFSET 0x0000 33#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 34#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 35#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 36#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) | 27 */ 28 29#ifndef _IF_CPSWREG_H 30#define _IF_CPSWREG_H 31 32#define CPSW_SS_OFFSET 0x0000 33#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 34#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 35#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 36#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) |
| 37#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24) |
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| 37 38#define CPSW_PORT_OFFSET 0x0100 | 38 39#define CPSW_PORT_OFFSET 0x0100 |
| 40#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100)) 41#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100)) |
|
| 39#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 40#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 41#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 42#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 43#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 44 45#define CPSW_CPDMA_OFFSET 0x0800 46#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) --- 32 unchanged lines hidden (view full) --- 79#define CPSW_ALE_OFFSET 0x0D00 80#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 81#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 82#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 83#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 84#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 85#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 86 | 42#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 43#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 44#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 45#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 46#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 47 48#define CPSW_CPDMA_OFFSET 0x0800 49#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) --- 32 unchanged lines hidden (view full) --- 82#define CPSW_ALE_OFFSET 0x0D00 83#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 84#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 85#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 86#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 87#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 88#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 89 |
| 90/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */ |
|
| 87#define CPSW_SL_OFFSET 0x0D80 88#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) | 91#define CPSW_SL_OFFSET 0x0D80 92#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) |
| 93#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) |
|
| 89#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 90#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) | 94#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 95#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) |
| 96#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) 97#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) |
|
| 91#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 92 93#define MDIO_OFFSET 0x1000 94#define MDIOCONTROL (MDIO_OFFSET + 0x04) 95#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 96#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 97 98#define CPSW_WR_OFFSET 0x1200 --- 5 unchanged lines hidden (view full) --- 104#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 105#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 106#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 107#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 108#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 109#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 110 111#define CPSW_CPPI_RAM_OFFSET 0x2000 | 98#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 99 100#define MDIO_OFFSET 0x1000 101#define MDIOCONTROL (MDIO_OFFSET + 0x04) 102#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 103#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 104 105#define CPSW_WR_OFFSET 0x1200 --- 5 unchanged lines hidden (view full) --- 111#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 112#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 113#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 114#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 115#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 116#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 117 118#define CPSW_CPPI_RAM_OFFSET 0x2000 |
| 119#define CPSW_CPPI_RAM_SIZE 0x2000 |
|
| 112 | 120 |
| 121#define CPDMA_BD_SOP (1<<15) 122#define CPDMA_BD_EOP (1<<14) 123#define CPDMA_BD_OWNER (1<<13) 124#define CPDMA_BD_EOQ (1<<12) 125#define CPDMA_BD_TDOWNCMPLT (1<<11) 126#define CPDMA_BD_PKT_ERR_MASK (3<< 4) 127 128struct cpsw_cpdma_bd { 129 volatile uint32_t next; 130 volatile uint32_t bufptr; 131 volatile uint16_t buflen; 132 volatile uint16_t bufoff; 133 volatile uint16_t pktlen; 134 volatile uint16_t flags; 135}; 136 |
|
| 113#endif /*_IF_CPSWREG_H */ | 137#endif /*_IF_CPSWREG_H */ |