1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 9 unchanged lines hidden (view full) ---
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 244939 2013-01-01 18:55:04Z kientzle $
27 */
28
29#ifndef _IF_CPSWREG_H
30#define _IF_CPSWREG_H
31
32#define CPSW_SS_OFFSET 0x0000
33#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37
38#define CPSW_PORT_OFFSET 0x0100
39#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
40#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
41#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
42#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
43#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
44
45#define CPSW_CPDMA_OFFSET 0x0800
46#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
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79#define CPSW_ALE_OFFSET 0x0D00
80#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
81#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
82#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
83#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
84#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
85#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
86
87#define CPSW_SL_OFFSET 0x0D80
88#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
89#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
90#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
91#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
92
93#define MDIO_OFFSET 0x1000
94#define MDIOCONTROL (MDIO_OFFSET + 0x04)
95#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
96#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
97
98#define CPSW_WR_OFFSET 0x1200
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104#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
105#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
106#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
107#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
108#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
109#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
110
111#define CPSW_CPPI_RAM_OFFSET 0x2000
112
113#endif /*_IF_CPSWREG_H */
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 9 unchanged lines hidden (view full) ---
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 244939 2013-01-01 18:55:04Z kientzle $
27 */
28
29#ifndef _IF_CPSWREG_H
30#define _IF_CPSWREG_H
31
32#define CPSW_SS_OFFSET 0x0000
33#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37
38#define CPSW_PORT_OFFSET 0x0100
39#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
40#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
41#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
42#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
43#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
44
45#define CPSW_CPDMA_OFFSET 0x0800
46#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
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79#define CPSW_ALE_OFFSET 0x0D00
80#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
81#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
82#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
83#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
84#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
85#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
86
87#define CPSW_SL_OFFSET 0x0D80
88#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
89#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
90#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
91#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
92
93#define MDIO_OFFSET 0x1000
94#define MDIOCONTROL (MDIO_OFFSET + 0x04)
95#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
96#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
97
98#define CPSW_WR_OFFSET 0x1200
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104#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
105#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
106#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
107#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
108#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
109#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
110
111#define CPSW_CPPI_RAM_OFFSET 0x2000
112
113#endif /*_IF_CPSWREG_H */