1/*-
2 * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
3 * All rights reserved.
4 *
5 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Wasabi Systems, Inc.
19 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
21 * written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1
36 *
| 1/*-
2 * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
3 * All rights reserved.
4 *
5 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Wasabi Systems, Inc.
19 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
21 * written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1
36 *
|
37 * $FreeBSD: head/sys/arm/mv/mvvar.h 186932 2009-01-09 10:20:51Z raj $
| 37 * $FreeBSD: head/sys/arm/mv/mvvar.h 196531 2009-08-25 09:30:03Z raj $
|
38 */
39
40#ifndef _MVVAR_H_
41#define _MVVAR_H_
42
43#include <sys/rman.h>
| 38 */
39
40#ifndef _MVVAR_H_
41#define _MVVAR_H_
42
43#include <sys/rman.h>
|
| 44#include <vm/vm.h>
45#include <vm/pmap.h>
46#include <machine/pmap.h>
47#include <machine/vm.h>
|
44
45#define MV_TYPE_PCI 0
46#define MV_TYPE_PCIE 1
47#define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */
48
49struct obio_softc {
50 bus_space_tag_t obio_bst; /* bus space tag */
51 struct rman obio_mem;
52 struct rman obio_irq;
53 struct rman obio_gpio;
54};
55
56struct obio_device {
57 const char *od_name;
58 u_long od_base;
59 u_long od_size;
60 u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */
61 u_int od_gpio[2 + 1]; /* as above for IRQ */
62 u_int od_pwr_mask;
63 struct resource_list od_resources;
64};
65
66struct obio_pci_irq_map {
67 int opim_slot;
68 int opim_pin;
69 int opim_irq;
70};
71
72struct obio_pci {
73 int op_type;
74
75 bus_addr_t op_base;
76 u_long op_size;
77
78 /* Note IO/MEM regions are assumed VA == PA */
79 bus_addr_t op_io_base;
80 u_long op_io_size;
81 int op_io_win_target;
82 int op_io_win_attr;
83
84 bus_addr_t op_mem_base;
85 u_long op_mem_size;
86 int op_mem_win_target;
87 int op_mem_win_attr;
88
89 const struct obio_pci_irq_map *op_pci_irq_map;
90 int op_irq; /* used if IRQ map table is NULL */
91};
92
93struct gpio_config {
94 int gc_gpio; /* GPIO number */
95 uint32_t gc_flags; /* GPIO flags */
96 int gc_output; /* GPIO output value */
97};
98
99struct decode_win {
100 int target; /* Mbus unit ID */
101 int attr; /* Attributes of the target interface */
102 vm_paddr_t base; /* Physical base addr */
103 uint32_t size;
104 int remap;
105};
106
| 48
49#define MV_TYPE_PCI 0
50#define MV_TYPE_PCIE 1
51#define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */
52
53struct obio_softc {
54 bus_space_tag_t obio_bst; /* bus space tag */
55 struct rman obio_mem;
56 struct rman obio_irq;
57 struct rman obio_gpio;
58};
59
60struct obio_device {
61 const char *od_name;
62 u_long od_base;
63 u_long od_size;
64 u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */
65 u_int od_gpio[2 + 1]; /* as above for IRQ */
66 u_int od_pwr_mask;
67 struct resource_list od_resources;
68};
69
70struct obio_pci_irq_map {
71 int opim_slot;
72 int opim_pin;
73 int opim_irq;
74};
75
76struct obio_pci {
77 int op_type;
78
79 bus_addr_t op_base;
80 u_long op_size;
81
82 /* Note IO/MEM regions are assumed VA == PA */
83 bus_addr_t op_io_base;
84 u_long op_io_size;
85 int op_io_win_target;
86 int op_io_win_attr;
87
88 bus_addr_t op_mem_base;
89 u_long op_mem_size;
90 int op_mem_win_target;
91 int op_mem_win_attr;
92
93 const struct obio_pci_irq_map *op_pci_irq_map;
94 int op_irq; /* used if IRQ map table is NULL */
95};
96
97struct gpio_config {
98 int gc_gpio; /* GPIO number */
99 uint32_t gc_flags; /* GPIO flags */
100 int gc_output; /* GPIO output value */
101};
102
103struct decode_win {
104 int target; /* Mbus unit ID */
105 int attr; /* Attributes of the target interface */
106 vm_paddr_t base; /* Physical base addr */
107 uint32_t size;
108 int remap;
109};
110
|
| 111extern const struct pmap_devmap pmap_devmap[];
|
107extern const struct obio_pci mv_pci_info[];
108extern const struct gpio_config mv_gpio_config[];
109extern bus_space_tag_t obio_tag;
110extern struct obio_device obio_devices[];
111extern const struct decode_win *cpu_wins;
112extern const struct decode_win *idma_wins;
113extern const struct decode_win *xor_wins;
114extern int cpu_wins_no;
115extern int idma_wins_no;
116extern int xor_wins_no;
117
118/* Function prototypes */
119int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
120 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep);
121void mv_gpio_intr_mask(int pin);
122void mv_gpio_intr_unmask(int pin);
123int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask);
124void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable);
125uint8_t mv_gpio_in(uint32_t pin);
126
| 112extern const struct obio_pci mv_pci_info[];
113extern const struct gpio_config mv_gpio_config[];
114extern bus_space_tag_t obio_tag;
115extern struct obio_device obio_devices[];
116extern const struct decode_win *cpu_wins;
117extern const struct decode_win *idma_wins;
118extern const struct decode_win *xor_wins;
119extern int cpu_wins_no;
120extern int idma_wins_no;
121extern int xor_wins_no;
122
123/* Function prototypes */
124int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
125 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep);
126void mv_gpio_intr_mask(int pin);
127void mv_gpio_intr_unmask(int pin);
128int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask);
129void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable);
130uint8_t mv_gpio_in(uint32_t pin);
131
|
127int platform_pmap_init(void);
| |
128void platform_mpp_init(void);
129int soc_decode_win(void);
130void soc_id(uint32_t *dev, uint32_t *rev);
131void soc_identify(void);
132void soc_dump_decode_win(void);
133uint32_t soc_power_ctrl_get(uint32_t mask);
134
135int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
136 int remap);
137int decode_win_overlap(int, int, const struct decode_win *);
138int win_cpu_can_remap(int);
139
140void decode_win_idma_dump(void);
141void decode_win_idma_setup(void);
142int decode_win_idma_valid(void);
143
144void decode_win_xor_dump(void);
145void decode_win_xor_setup(void);
146int decode_win_xor_valid(void);
147
148int ddr_is_active(int i);
149uint32_t ddr_base(int i);
150uint32_t ddr_size(int i);
151uint32_t ddr_attr(int i);
152uint32_t ddr_target(int i);
153
154uint32_t cpu_extra_feat(void);
155uint32_t get_tclk(void);
156uint32_t read_cpu_ctrl(uint32_t);
157void write_cpu_ctrl(uint32_t, uint32_t);
158
159enum mbus_device_ivars {
160 MBUS_IVAR_BASE,
161};
162
163#define MBUS_ACCESSOR(var, ivar, type) \
164 __BUS_ACCESSOR(mbus, var, MBUS, ivar, type)
165
166MBUS_ACCESSOR(base, BASE, u_long)
167
168#undef MBUS_ACCESSOR
169
170#endif /* _MVVAR_H_ */
| 132void platform_mpp_init(void);
133int soc_decode_win(void);
134void soc_id(uint32_t *dev, uint32_t *rev);
135void soc_identify(void);
136void soc_dump_decode_win(void);
137uint32_t soc_power_ctrl_get(uint32_t mask);
138
139int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
140 int remap);
141int decode_win_overlap(int, int, const struct decode_win *);
142int win_cpu_can_remap(int);
143
144void decode_win_idma_dump(void);
145void decode_win_idma_setup(void);
146int decode_win_idma_valid(void);
147
148void decode_win_xor_dump(void);
149void decode_win_xor_setup(void);
150int decode_win_xor_valid(void);
151
152int ddr_is_active(int i);
153uint32_t ddr_base(int i);
154uint32_t ddr_size(int i);
155uint32_t ddr_attr(int i);
156uint32_t ddr_target(int i);
157
158uint32_t cpu_extra_feat(void);
159uint32_t get_tclk(void);
160uint32_t read_cpu_ctrl(uint32_t);
161void write_cpu_ctrl(uint32_t, uint32_t);
162
163enum mbus_device_ivars {
164 MBUS_IVAR_BASE,
165};
166
167#define MBUS_ACCESSOR(var, ivar, type) \
168 __BUS_ACCESSOR(mbus, var, MBUS, ivar, type)
169
170MBUS_ACCESSOR(base, BASE, u_long)
171
172#undef MBUS_ACCESSOR
173
174#endif /* _MVVAR_H_ */
|