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armadaxp.c (250292) armadaxp.c (250293)
1/*-
2 * Copyright (c) 2011 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53
27 */
28
29#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 13 unchanged lines hidden (view full) ---

22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/arm/mv/armadaxp/armadaxp.c 250292 2013-05-06 13:52:49Z gber $");
30__FBSDID("$FreeBSD: head/sys/arm/mv/armadaxp/armadaxp.c 250293 2013-05-06 14:12:36Z gber $");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <machine/bus.h>
37#include <machine/armreg.h>
38

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46#include <machine/fdt.h>
47
48#define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
49 (0x07 & (sar >> 21)))
50#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
51 (0x0F & (sar >> 24)))
52
53static uint32_t count_l2clk(void);
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <machine/bus.h>
37#include <machine/armreg.h>
38

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46#include <machine/fdt.h>
47
48#define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
49 (0x07 & (sar >> 21)))
50#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
51 (0x0F & (sar >> 24)))
52
53static uint32_t count_l2clk(void);
54void armadaxp_l2_init(void);
55void armadaxp_init_coher_fabric(void);
56int platform_get_ncpus(void);
54
55#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
56#define ARMADAXP_L2_CTRL 0x100
57#define L2_ENABLE (1 << 0)
58#define ARMADAXP_L2_AUX_CTRL 0x104
59#define L2_WBWT_MODE_MASK (3 << 0)
60#define L2_WBWT_MODE_PAGE 0
61#define L2_WBWT_MODE_WB 1

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72#define ARMADAXP_L2_INT_CAUSE 0x220
73
74#define ARMADAXP_L2_SYNC_BARRIER 0x700
75#define ARMADAXP_L2_INV_WAY 0x778
76#define ARMADAXP_L2_CLEAN_WAY 0x7BC
77#define ARMADAXP_L2_FLUSH_PHYS 0x7F0
78#define ARMADAXP_L2_FLUSH_WAY 0x7FC
79
57
58#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
59#define ARMADAXP_L2_CTRL 0x100
60#define L2_ENABLE (1 << 0)
61#define ARMADAXP_L2_AUX_CTRL 0x104
62#define L2_WBWT_MODE_MASK (3 << 0)
63#define L2_WBWT_MODE_PAGE 0
64#define L2_WBWT_MODE_WB 1

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75#define ARMADAXP_L2_INT_CAUSE 0x220
76
77#define ARMADAXP_L2_SYNC_BARRIER 0x700
78#define ARMADAXP_L2_INV_WAY 0x778
79#define ARMADAXP_L2_CLEAN_WAY 0x7BC
80#define ARMADAXP_L2_FLUSH_PHYS 0x7F0
81#define ARMADAXP_L2_FLUSH_WAY 0x7FC
82
80#define COHER_FABRIC_CFU 0x228
83#define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
84#define COHER_FABRIC_CTRL 0x00
85#define COHER_FABRIC_CONF 0x04
86#define COHER_FABRIC_CFU 0x28
87#define COHER_FABRIC_CIB_CTRL 0x80
81
82/* XXX Make gpio driver optional and remove it */
83struct resource_spec mv_gpio_res[] = {
84 { SYS_RES_MEMORY, 0, RF_ACTIVE },
85 { SYS_RES_IRQ, 0, RF_ACTIVE },
86 { -1, 0 }
87};
88

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183
184 /* If get_l2clk is called first time get L2CLK value from register */
185 if (l2clk_freq == 0)
186 l2clk_freq = count_l2clk();
187
188 return (l2clk_freq);
189}
190
88
89/* XXX Make gpio driver optional and remove it */
90struct resource_spec mv_gpio_res[] = {
91 { SYS_RES_MEMORY, 0, RF_ACTIVE },
92 { SYS_RES_IRQ, 0, RF_ACTIVE },
93 { -1, 0 }
94};
95

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190
191 /* If get_l2clk is called first time get L2CLK value from register */
192 if (l2clk_freq == 0)
193 l2clk_freq = count_l2clk();
194
195 return (l2clk_freq);
196}
197
191void armadaxp_l2_init(void);
192void armadaxp_l2_idcache_inv_all(void);
198static uint32_t
199read_coher_fabric(uint32_t reg)
200{
193
201
202 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));
203}
204
205static void
206write_coher_fabric(uint32_t reg, uint32_t val)
207{
208
209 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);
210}
211
212int
213platform_get_ncpus(void)
214{
215#if !defined(SMP)
216 return (1);
217#else
218 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1);
219#endif
220}
221
222void
223armadaxp_init_coher_fabric(void)
224{
225 uint32_t val, cpus, mask;
226
227 cpus = platform_get_ncpus();
228 mask = (1 << cpus) - 1;
229 val = read_coher_fabric(COHER_FABRIC_CTRL);
230 val |= (mask << 24);
231 write_coher_fabric(COHER_FABRIC_CTRL, val);
232
233 val = read_coher_fabric(COHER_FABRIC_CONF);
234 val |= (mask << 24);
235 val |= (1 << 15);
236 write_coher_fabric(COHER_FABRIC_CONF, val);
237}
238
194#define ALL_WAYS 0xffffffff
195
196/* L2 cache configuration registers */
197static uint32_t
198read_l2_cache(uint32_t reg)
199{
200
201 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));
202}
203
204static void
205write_l2_cache(uint32_t reg, uint32_t val)
206{
207
208 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);
209}
210
239#define ALL_WAYS 0xffffffff
240
241/* L2 cache configuration registers */
242static uint32_t
243read_l2_cache(uint32_t reg)
244{
245
246 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));
247}
248
249static void
250write_l2_cache(uint32_t reg, uint32_t val)
251{
252
253 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);
254}
255
211void
256static void
212armadaxp_l2_idcache_inv_all(void)
213{
214 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS);
215}
216
217void
218armadaxp_l2_init(void)
219{

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228 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);
229
230 /* Invalidate l2 cache */
231 armadaxp_l2_idcache_inv_all();
232
233 /* Clear pending L2 interrupts */
234 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff);
235
257armadaxp_l2_idcache_inv_all(void)
258{
259 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS);
260}
261
262void
263armadaxp_l2_init(void)
264{

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273 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);
274
275 /* Invalidate l2 cache */
276 armadaxp_l2_idcache_inv_all();
277
278 /* Clear pending L2 interrupts */
279 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff);
280
236 /* Enable Cache and TLB maintenance broadcast */
237 __asm__ __volatile__ ("mrc p15, 1, %0, c15, c2, 0" : "=r"(reg));
238 reg |= (1 << 8);
239 __asm__ __volatile__ ("mcr p15, 1, %0, c15, c2, 0" : :"r"(reg));
240
241 /* Enable l2 cache */
242 reg = read_l2_cache(ARMADAXP_L2_CTRL);
243 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
244
245 /*
246 * For debug purposes
247 * Configure and enable counter
248 */
249 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2));
250 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2));
251 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303);
252
253 /*
254 * Enable Cache maintenance operation propagation in coherency fabric
255 * Change point of coherency and point of unification to DRAM.
256 */
281 /* Enable l2 cache */
282 reg = read_l2_cache(ARMADAXP_L2_CTRL);
283 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
284
285 /*
286 * For debug purposes
287 * Configure and enable counter
288 */
289 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2));
290 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2));
291 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303);
292
293 /*
294 * Enable Cache maintenance operation propagation in coherency fabric
295 * Change point of coherency and point of unification to DRAM.
296 */
257 reg = bus_space_read_4(fdtbus_bs_tag, MV_MBUS_BRIDGE_BASE,
258 COHER_FABRIC_CFU);
297 reg = read_coher_fabric(COHER_FABRIC_CFU);
259 reg |= (1 << 17) | (1 << 18);
298 reg |= (1 << 17) | (1 << 18);
260 bus_space_write_4(fdtbus_bs_tag, MV_MBUS_BRIDGE_BASE, COHER_FABRIC_CFU,
261 reg);
299 write_coher_fabric(COHER_FABRIC_CFU, reg);
300
301 /* Coherent IO Bridge initialization */
302 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL);
303 reg &= ~(7 << 16);
304 reg |= (7 << 16);
305 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg);
262}
263
306}
307