| at91_mcireg.h (185265) | at91_mcireg.h (234560) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 Berndt Walter. All rights reserved. 3 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 | 1/*- 2 * Copyright (c) 2006 Berndt Walter. All rights reserved. 3 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 |
| 27/* $FreeBSD: head/sys/arm/at91/at91_mcireg.h 185265 2008-11-25 00:13:26Z imp $ */ | 27/* $FreeBSD: head/sys/arm/at91/at91_mcireg.h 234560 2012-04-22 00:43:32Z marius $ */ |
| 28 29#ifndef ARM_AT91_AT91_MCIREG_H 30#define ARM_AT91_AT91_MCIREG_H 31 32#define MMC_MAX 30 33 34#define MCI_CR 0x00 /* MCI Control Register */ 35#define MCI_MR 0x04 /* MCI Mode Register */ --- 13 unchanged lines hidden (view full) --- 49#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */ 50#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */ 51#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */ 52#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */ 53#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */ 54/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */ 55#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */ 56#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */ | 28 29#ifndef ARM_AT91_AT91_MCIREG_H 30#define ARM_AT91_AT91_MCIREG_H 31 32#define MMC_MAX 30 33 34#define MCI_CR 0x00 /* MCI Control Register */ 35#define MCI_MR 0x04 /* MCI Mode Register */ --- 13 unchanged lines hidden (view full) --- 49#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */ 50#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */ 51#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */ 52#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */ 53#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */ 54/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */ 55#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */ 56#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */ |
| 57#define MCI_MR_RDPROOF (0x1u << 11) /* (MCI) Read Proof Enable */ 58#define MCI_MR_WRPROOF (0x1u << 12) /* (MCI) Write Proof Enable */ 59#define MCI_MR_PDCFBYTE (0x1u << 13) /* (MCI) PDC Force Byte Transfer */ |
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| 57#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */ 58#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */ 59#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */ 60/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */ 61#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */ 62#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */ 63#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */ 64#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */ --- 65 unchanged lines hidden --- | 60#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */ 61#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */ 62#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */ 63/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */ 64#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */ 65#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */ 66#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */ 67#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */ --- 65 unchanged lines hidden --- |