1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
2.\"
3.\" Redistribution and use in source and binary forms, with or without
4.\" modification, are permitted provided that the following conditions
5.\" are met:
6.\" 1. Redistributions of source code must retain the above copyright
7.\" notice, this list of conditions and the following disclaimer.
8.\" 2. Redistributions in binary form must reproduce the above copyright
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16.\" for any direct, indirect, incidental, special, exemplary, or consequential
17.\" damages (including, but not limited to, procurement of substitute goods
18.\" or services; loss of use, data, or profits; or business interruption)
19.\" however caused and on any theory of liability, whether in contract, strict
20.\" liability, or tort (including negligence or otherwise) arising in any way
21.\" out of the use of this software, even if advised of the possibility of
22.\" such damage.
23.\"
24.\" $FreeBSD: head/lib/libpmc/pmc.corei7.3 229470 2012-01-04 07:58:36Z fabient $
25.\"
26.Dd March 24, 2010
27.Dt PMC.COREI7 3
28.Os
29.Sh NAME
30.Nm pmc.corei7
31.Nd measurement events for
32.Tn Intel
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195Counts number of completed page walks due to load miss in the STLB.
196.It Li DTLB_LOAD_MISSES.STLB_HIT
197.Pq Event 08H , Umask 10H
198Number of cache load STLB hits
199.It Li DTLB_LOAD_MISSES.PDE_MISS
200.Pq Event 08H , Umask 20H
201Number of DTLB cache load misses where the low part of the linear to
202physical address translation was missed.
203.It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED
204.Pq Event 08H , Umask 80H
205Counts number of completed large page walks due to load miss in the STLB.
206.It Li MEM_INST_RETIRED.LOADS
207.Pq Event 0BH , Umask 01H
208Counts the number of instructions with an architecturally-visible store
209retired on the architected path.
210In conjunction with ld_lat facility
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637once.
638The event does not include non- memory accesses, such as I/O accesses.
639Counter 0, 1 only
640.It Li L1D_ALL_REF.CACHEABLE
641.Pq Event 43H , Umask 02H
642Counts all data reads and writes (speculated and retired) from cacheable
643memory, including locked operations.
644Counter 0, 1 only
645.It Li DTLB_MISSES.ANY
646.Pq Event 49H , Umask 01H
647Counts the number of misses in the STLB which causes a page walk.
648.It Li DTLB_MISSES.WALK_COMPLETED
649.Pq Event 49H , Umask 02H
650Counts number of misses in the STLB which resulted in a completed page walk.
651.It Li DTLB_MISSES.STLB_HIT
652.Pq Event 49H , Umask 10H
653Counts the number of DTLB first level misses that hit in the second level
654TLB. This event is only relevant if the core contains multiple DTLB levels.
655.It Li DTLB_MISSES.PDE_MISS
656.Pq Event 49H , Umask 20H
657Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE.
658.It Li DTLB_MISSES.LARGE_WALK_COMPLETED
659.Pq Event 49H , Umask 80H
660Counts number of misses in the STLB which resulted in a completed page walk for large pages.
661.It Li LOAD_HIT_PRE
662.Pq Event 4CH , Umask 01H
663Counts load operations sent to the L1 data cache while a previous SSE
664prefetch instruction to the same cache line has started prefetching but has
665not yet finished.
666.It Li L1D_PREFETCH.REQUESTS
667.Pq Event 4EH , Umask 01H
668Counts number of hardware prefetch requests dispatched out of the prefetch
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1198.Pq Event E8H , Umask 01H
1199Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken
1200branch after incorrectly assuming that it was not taken.
1201The BPU clear leads to 2 cycle bubble in the Front End.
1202.It Li BPU_CLEARS.LATE
1203.Pq Event E8H , Umask 02H
1204Counts late Branch Prediction Unit clears due to Most Recently Used
1205conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
1206.It Li L2_TRANSACTIONS.LOAD
1207.Pq Event F0H , Umask 01H
1208Counts L2 load operations due to HW prefetch or demand loads.
1209.It Li L2_TRANSACTIONS.RFO
1210.Pq Event F0H , Umask 02H
1211Counts L2 RFO operations due to HW prefetch or demand RFOs.
1212.It Li L2_TRANSACTIONS.IFETCH
1213.Pq Event F0H , Umask 04H
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2.\"
3.\" Redistribution and use in source and binary forms, with or without
4.\" modification, are permitted provided that the following conditions
5.\" are met:
6.\" 1. Redistributions of source code must retain the above copyright
7.\" notice, this list of conditions and the following disclaimer.
8.\" 2. Redistributions in binary form must reproduce the above copyright
--- 7 unchanged lines hidden (view full) ---
16.\" for any direct, indirect, incidental, special, exemplary, or consequential
17.\" damages (including, but not limited to, procurement of substitute goods
18.\" or services; loss of use, data, or profits; or business interruption)
19.\" however caused and on any theory of liability, whether in contract, strict
20.\" liability, or tort (including negligence or otherwise) arising in any way
21.\" out of the use of this software, even if advised of the possibility of
22.\" such damage.
23.\"
24.\" $FreeBSD: head/lib/libpmc/pmc.corei7.3 229470 2012-01-04 07:58:36Z fabient $
25.\"
26.Dd March 24, 2010
27.Dt PMC.COREI7 3
28.Os
29.Sh NAME
30.Nm pmc.corei7
31.Nd measurement events for
32.Tn Intel
--- 162 unchanged lines hidden (view full) ---
195Counts number of completed page walks due to load miss in the STLB.
196.It Li DTLB_LOAD_MISSES.STLB_HIT
197.Pq Event 08H , Umask 10H
198Number of cache load STLB hits
199.It Li DTLB_LOAD_MISSES.PDE_MISS
200.Pq Event 08H , Umask 20H
201Number of DTLB cache load misses where the low part of the linear to
202physical address translation was missed.
203.It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED
204.Pq Event 08H , Umask 80H
205Counts number of completed large page walks due to load miss in the STLB.
206.It Li MEM_INST_RETIRED.LOADS
207.Pq Event 0BH , Umask 01H
208Counts the number of instructions with an architecturally-visible store
209retired on the architected path.
210In conjunction with ld_lat facility
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637once.
638The event does not include non- memory accesses, such as I/O accesses.
639Counter 0, 1 only
640.It Li L1D_ALL_REF.CACHEABLE
641.Pq Event 43H , Umask 02H
642Counts all data reads and writes (speculated and retired) from cacheable
643memory, including locked operations.
644Counter 0, 1 only
645.It Li DTLB_MISSES.ANY
646.Pq Event 49H , Umask 01H
647Counts the number of misses in the STLB which causes a page walk.
648.It Li DTLB_MISSES.WALK_COMPLETED
649.Pq Event 49H , Umask 02H
650Counts number of misses in the STLB which resulted in a completed page walk.
651.It Li DTLB_MISSES.STLB_HIT
652.Pq Event 49H , Umask 10H
653Counts the number of DTLB first level misses that hit in the second level
654TLB. This event is only relevant if the core contains multiple DTLB levels.
655.It Li DTLB_MISSES.PDE_MISS
656.Pq Event 49H , Umask 20H
657Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE.
658.It Li DTLB_MISSES.LARGE_WALK_COMPLETED
659.Pq Event 49H , Umask 80H
660Counts number of misses in the STLB which resulted in a completed page walk for large pages.
661.It Li LOAD_HIT_PRE
662.Pq Event 4CH , Umask 01H
663Counts load operations sent to the L1 data cache while a previous SSE
664prefetch instruction to the same cache line has started prefetching but has
665not yet finished.
666.It Li L1D_PREFETCH.REQUESTS
667.Pq Event 4EH , Umask 01H
668Counts number of hardware prefetch requests dispatched out of the prefetch
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1198.Pq Event E8H , Umask 01H
1199Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken
1200branch after incorrectly assuming that it was not taken.
1201The BPU clear leads to 2 cycle bubble in the Front End.
1202.It Li BPU_CLEARS.LATE
1203.Pq Event E8H , Umask 02H
1204Counts late Branch Prediction Unit clears due to Most Recently Used
1205conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
1206.It Li L2_TRANSACTIONS.LOAD
1207.Pq Event F0H , Umask 01H
1208Counts L2 load operations due to HW prefetch or demand loads.
1209.It Li L2_TRANSACTIONS.RFO
1210.Pq Event F0H , Umask 02H
1211Counts L2 RFO operations due to HW prefetch or demand RFOs.
1212.It Li L2_TRANSACTIONS.IFETCH
1213.Pq Event F0H , Umask 04H
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