1/*-
2 * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
|
27__FBSDID("$FreeBSD: head/lib/libc/sparc64/sys/__sparc_utrap_emul.c 95587 2002-04-27 21:56:28Z jake $");
| 27__FBSDID("$FreeBSD: head/lib/libc/sparc64/sys/__sparc_utrap_emul.c 96422 2002-05-11 21:20:05Z jake $");
|
28
29#include <sys/types.h>
30#include <machine/cpufunc.h>
31#include <machine/frame.h>
32#include <machine/instr.h>
33
34#include <signal.h>
35
36#include "__sparc_utrap_private.h"
37#include "fpu_reg.h"
38
39int
40__emul_insn(struct utrapframe *uf)
41{
42 u_long reg, res;
43 u_long *addr;
44 u_int insn;
45 int sig;
46 int rd;
47 int i;
48
49 sig = 0;
50 insn = *(u_int *)uf->uf_pc;
51 flushw();
52 switch (IF_OP(insn)) {
53 case IOP_MISC:
54 switch (IF_F3_OP3(insn)) {
55 case INS2_POPC:
56 if (IF_F3_RS1(insn) != 0) {
57 sig = SIGILL;
58 break;
59 }
60 reg = __emul_f3_op2(uf, insn);
61 for (i = 0; i < 64; i++)
62 res += (reg >> i) & 1;
63 __emul_store_reg(uf, IF_F3_RD(insn), res);
64 break;
65 default:
66 sig = SIGILL;
67 break;
68 }
69 break;
70 case IOP_LDST:
71 switch (IF_F3_OP3(insn)) {
72 case INS3_LDQF:
| 28
29#include <sys/types.h>
30#include <machine/cpufunc.h>
31#include <machine/frame.h>
32#include <machine/instr.h>
33
34#include <signal.h>
35
36#include "__sparc_utrap_private.h"
37#include "fpu_reg.h"
38
39int
40__emul_insn(struct utrapframe *uf)
41{
42 u_long reg, res;
43 u_long *addr;
44 u_int insn;
45 int sig;
46 int rd;
47 int i;
48
49 sig = 0;
50 insn = *(u_int *)uf->uf_pc;
51 flushw();
52 switch (IF_OP(insn)) {
53 case IOP_MISC:
54 switch (IF_F3_OP3(insn)) {
55 case INS2_POPC:
56 if (IF_F3_RS1(insn) != 0) {
57 sig = SIGILL;
58 break;
59 }
60 reg = __emul_f3_op2(uf, insn);
61 for (i = 0; i < 64; i++)
62 res += (reg >> i) & 1;
63 __emul_store_reg(uf, IF_F3_RD(insn), res);
64 break;
65 default:
66 sig = SIGILL;
67 break;
68 }
69 break;
70 case IOP_LDST:
71 switch (IF_F3_OP3(insn)) {
72 case INS3_LDQF:
|
73 rd = IF_F3_RD(insn);
74 rd = (rd & ~3) | ((rd & 1) << 5);
| 73 rd = INSFPdq_RN(IF_F3_RD(insn));
|
75 addr = (u_long *)__emul_f3_memop_addr(uf, insn);
76 __fpu_setreg64(rd, addr[0]);
77 __fpu_setreg64(rd + 2, addr[1]);
78 break;
79 case INS3_STQF:
| 74 addr = (u_long *)__emul_f3_memop_addr(uf, insn);
75 __fpu_setreg64(rd, addr[0]);
76 __fpu_setreg64(rd + 2, addr[1]);
77 break;
78 case INS3_STQF:
|
80 rd = IF_F3_RD(insn);
81 rd = (rd & ~3) | ((rd & 1) << 5);
| 79 rd = INSFPdq_RN(IF_F3_RD(insn));
|
82 addr = (u_long *)__emul_f3_memop_addr(uf, insn);
83 addr[0] = __fpu_getreg64(rd);
84 addr[1] = __fpu_getreg64(rd + 2);
85 break;
86 default:
87 sig = SIGILL;
88 break;
89 }
90 break;
91 default:
92 sig = SIGILL;
93 break;
94 }
95 return (sig);
96}
97
98u_long
99__emul_fetch_reg(struct utrapframe *uf, int reg)
100{
101 struct frame *frm;
102
103 if (reg == IREG_G0)
104 return (0);
105 else if (reg < IREG_O0) /* global */
106 return (uf->uf_global[reg]);
107 else if (reg < IREG_L0) /* out */
108 return (uf->uf_out[reg - IREG_O0]);
109 else { /* local, in */
110 /*
111 * The in registers are immediately after the locals in
112 * the frame.
113 */
114 frm = (struct frame *)(uf->uf_out[6] + SPOFF);
115 return (frm->fr_local[reg - IREG_L0]);
116 }
117}
118
119void
120__emul_store_reg(struct utrapframe *uf, int reg, u_long val)
121{
122 struct frame *frm;
123
124 if (reg == IREG_G0)
125 return;
126 if (reg < IREG_O0) /* global */
127 uf->uf_global[reg] = val;
128 else if (reg < IREG_L0) /* out */
129 uf->uf_out[reg - IREG_O0] = val;
130 else {
131 /*
132 * The in registers are immediately after the locals in
133 * the frame.
134 */
135 frm = (struct frame *)(uf->uf_out[6] + SPOFF);
136 frm->fr_local[reg - IREG_L0] = val;
137 }
138}
139
140u_long
141__emul_f3_op2(struct utrapframe *uf, u_int insn)
142{
143
144 if (IF_F3_I(insn) != 0)
145 return (IF_SIMM(insn, 13));
146 else
147 return (__emul_fetch_reg(uf, IF_F3_RS2(insn)));
148}
149
150u_long
151__emul_f3_memop_addr(struct utrapframe *uf, u_int insn)
152{
153 u_long addr;
154
155 addr = __emul_f3_op2(uf, insn) + __emul_fetch_reg(uf, IF_F3_RS1(insn));
156 return (addr);
157}
| 80 addr = (u_long *)__emul_f3_memop_addr(uf, insn);
81 addr[0] = __fpu_getreg64(rd);
82 addr[1] = __fpu_getreg64(rd + 2);
83 break;
84 default:
85 sig = SIGILL;
86 break;
87 }
88 break;
89 default:
90 sig = SIGILL;
91 break;
92 }
93 return (sig);
94}
95
96u_long
97__emul_fetch_reg(struct utrapframe *uf, int reg)
98{
99 struct frame *frm;
100
101 if (reg == IREG_G0)
102 return (0);
103 else if (reg < IREG_O0) /* global */
104 return (uf->uf_global[reg]);
105 else if (reg < IREG_L0) /* out */
106 return (uf->uf_out[reg - IREG_O0]);
107 else { /* local, in */
108 /*
109 * The in registers are immediately after the locals in
110 * the frame.
111 */
112 frm = (struct frame *)(uf->uf_out[6] + SPOFF);
113 return (frm->fr_local[reg - IREG_L0]);
114 }
115}
116
117void
118__emul_store_reg(struct utrapframe *uf, int reg, u_long val)
119{
120 struct frame *frm;
121
122 if (reg == IREG_G0)
123 return;
124 if (reg < IREG_O0) /* global */
125 uf->uf_global[reg] = val;
126 else if (reg < IREG_L0) /* out */
127 uf->uf_out[reg - IREG_O0] = val;
128 else {
129 /*
130 * The in registers are immediately after the locals in
131 * the frame.
132 */
133 frm = (struct frame *)(uf->uf_out[6] + SPOFF);
134 frm->fr_local[reg - IREG_L0] = val;
135 }
136}
137
138u_long
139__emul_f3_op2(struct utrapframe *uf, u_int insn)
140{
141
142 if (IF_F3_I(insn) != 0)
143 return (IF_SIMM(insn, 13));
144 else
145 return (__emul_fetch_reg(uf, IF_F3_RS2(insn)));
146}
147
148u_long
149__emul_f3_memop_addr(struct utrapframe *uf, u_int insn)
150{
151 u_long addr;
152
153 addr = __emul_f3_op2(uf, insn) + __emul_fetch_reg(uf, IF_F3_RS1(insn));
154 return (addr);
155}
|