1//===- TableGen.cpp - Top-Level TableGen implementation -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen is a tool which can be used to build up a description of something, 11// then invoke one or more "tablegen backends" to emit information about the 12// description in some predefined format. In practice, this is used by the LLVM 13// code generators to automate generation of a code generator through a 14// high-level description of the target. 15// 16//===----------------------------------------------------------------------===// 17 |
18#include "AsmMatcherEmitter.h" 19#include "AsmWriterEmitter.h" |
20#include "CallingConvEmitter.h" |
21#include "ClangDiagnosticsEmitter.h" |
22#include "CodeEmitterGen.h" |
23#include "DAGISelEmitter.h" 24#include "FastISelEmitter.h" |
25#include "InstrEnumEmitter.h" 26#include "InstrInfoEmitter.h" |
27#include "IntrinsicEmitter.h" 28#include "LLVMCConfigurationEmitter.h" |
29#include "OptParserEmitter.h" 30#include "Record.h" 31#include "RegisterInfoEmitter.h" 32#include "SubtargetEmitter.h" 33#include "TGParser.h" |
34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/FileUtilities.h" 36#include "llvm/Support/MemoryBuffer.h" 37#include "llvm/Support/PrettyStackTrace.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/System/Signals.h" 40#include <algorithm> 41#include <cstdio> --- 4 unchanged lines hidden (view full) --- 46 GenEmitter, 47 GenRegisterEnums, GenRegister, GenRegisterHeader, 48 GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, 49 GenCallingConv, 50 GenClangDiagsDefs, 51 GenClangDiagGroups, 52 GenDAGISel, 53 GenFastISel, |
54 GenOptParserDefs, GenOptParserImpl, |
55 GenSubtarget, 56 GenIntrinsic, 57 GenTgtIntrinsic, 58 GenLLVMCConf, 59 PrintEnums 60}; 61 62namespace { --- 18 unchanged lines hidden (view full) --- 81 clEnumValN(GenAsmWriter, "gen-asm-writer", 82 "Generate assembly writer"), 83 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 84 "Generate assembly instruction matcher"), 85 clEnumValN(GenDAGISel, "gen-dag-isel", 86 "Generate a DAG instruction selector"), 87 clEnumValN(GenFastISel, "gen-fast-isel", 88 "Generate a \"fast\" instruction selector"), |
89 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 90 "Generate option definitions"), 91 clEnumValN(GenOptParserImpl, "gen-opt-parser-impl", 92 "Generate option parser implementation"), |
93 clEnumValN(GenSubtarget, "gen-subtarget", 94 "Generate subtarget enumerations"), 95 clEnumValN(GenIntrinsic, "gen-intrinsic", 96 "Generate intrinsic information"), 97 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 98 "Generate target intrinsic information"), 99 clEnumValN(GenClangDiagsDefs, "gen-clang-diags-defs", 100 "Generate Clang diagnostics definitions"), --- 121 unchanged lines hidden (view full) --- 222 case GenAsmMatcher: 223 AsmMatcherEmitter(Records).run(*Out); 224 break; 225 case GenClangDiagsDefs: 226 ClangDiagsDefsEmitter(Records, ClangComponent).run(*Out); 227 break; 228 case GenClangDiagGroups: 229 ClangDiagGroupsEmitter(Records).run(*Out); |
230 break; 231 case GenOptParserDefs: 232 OptParserEmitter(Records, true).run(*Out); 233 break; 234 case GenOptParserImpl: 235 OptParserEmitter(Records, false).run(*Out); 236 break; |
237 case GenDAGISel: 238 DAGISelEmitter(Records).run(*Out); 239 break; 240 case GenFastISel: 241 FastISelEmitter(Records).run(*Out); 242 break; 243 case GenSubtarget: 244 SubtargetEmitter(Records).run(*Out); --- 45 unchanged lines hidden --- |