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RegisterInfoEmitter.cpp (193323) RegisterInfoEmitter.cpp (195340)
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "Record.h"
20#include "llvm/ADT/StringExtras.h"
21#include "llvm/ADT/STLExtras.h"
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "Record.h"
20#include "llvm/ADT/StringExtras.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/Support/Streams.h"
23#include <set>
24#include <algorithm>
22#include <algorithm>
23#include <set>
25using namespace llvm;
26
27// runEnums - Print out enum values for all of the registers.
24using namespace llvm;
25
26// runEnums - Print out enum values for all of the registers.
28void RegisterInfoEmitter::runEnums(std::ostream &OS) {
27void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 CodeGenTarget Target;
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
36

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42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 OS << " };\n";
45 if (!Namespace.empty())
46 OS << "}\n";
47 OS << "} // End llvm namespace \n";
48}
49
28 CodeGenTarget Target;
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
30
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
32
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
35

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41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
43 OS << " };\n";
44 if (!Namespace.empty())
45 OS << "}\n";
46 OS << "} // End llvm namespace \n";
47}
48
50void RegisterInfoEmitter::runHeader(std::ostream &OS) {
49void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
51 EmitSourceFileHeader("Register Information Header Fragment", OS);
52 CodeGenTarget Target;
53 const std::string &TargetName = Target.getName();
54 std::string ClassName = TargetName + "GenRegisterInfo";
55
56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
57 OS << "#include <string>\n\n";
58

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113 return true;
114}
115
116static void addSuperReg(Record *R, Record *S,
117 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
118 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
119 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
120 if (R == S) {
50 EmitSourceFileHeader("Register Information Header Fragment", OS);
51 CodeGenTarget Target;
52 const std::string &TargetName = Target.getName();
53 std::string ClassName = TargetName + "GenRegisterInfo";
54
55 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
56 OS << "#include <string>\n\n";
57

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112 return true;
113}
114
115static void addSuperReg(Record *R, Record *S,
116 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
117 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
118 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
119 if (R == S) {
121 cerr << "Error: recursive sub-register relationship between"
122 << " register " << getQualifiedName(R)
123 << " and its sub-registers?\n";
120 errs() << "Error: recursive sub-register relationship between"
121 << " register " << getQualifiedName(R)
122 << " and its sub-registers?\n";
124 abort();
125 }
126 if (!SuperRegs[R].insert(S).second)
127 return;
128 SubRegs[S].insert(R);
129 Aliases[R].insert(S);
130 Aliases[S].insert(R);
131 if (SuperRegs.count(S))
132 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
133 E = SuperRegs[S].end(); I != E; ++I)
134 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
135}
136
137static void addSubSuperReg(Record *R, Record *S,
138 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
139 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
140 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
141 if (R == S) {
123 abort();
124 }
125 if (!SuperRegs[R].insert(S).second)
126 return;
127 SubRegs[S].insert(R);
128 Aliases[R].insert(S);
129 Aliases[S].insert(R);
130 if (SuperRegs.count(S))
131 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
132 E = SuperRegs[S].end(); I != E; ++I)
133 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
134}
135
136static void addSubSuperReg(Record *R, Record *S,
137 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
138 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
139 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
140 if (R == S) {
142 cerr << "Error: recursive sub-register relationship between"
143 << " register " << getQualifiedName(R)
144 << " and its sub-registers?\n";
141 errs() << "Error: recursive sub-register relationship between"
142 << " register " << getQualifiedName(R)
143 << " and its sub-registers?\n";
145 abort();
146 }
147
148 if (!SubRegs[R].insert(S).second)
149 return;
150 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
151 Aliases[R].insert(S);
152 Aliases[S].insert(R);

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167 bool operator()(Record *RegA, Record *RegB) {
168 // B is sub-register of A.
169 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
170 }
171};
172
173// RegisterInfoEmitter::run - Main register file description emitter.
174//
144 abort();
145 }
146
147 if (!SubRegs[R].insert(S).second)
148 return;
149 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
150 Aliases[R].insert(S);
151 Aliases[S].insert(R);

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166 bool operator()(Record *RegA, Record *RegB) {
167 // B is sub-register of A.
168 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
169 }
170};
171
172// RegisterInfoEmitter::run - Main register file description emitter.
173//
175void RegisterInfoEmitter::run(std::ostream &OS) {
174void RegisterInfoEmitter::run(raw_ostream &OS) {
176 CodeGenTarget Target;
177 EmitSourceFileHeader("Register Information Source Fragment", OS);
178
179 OS << "namespace llvm {\n\n";
180
181 // Start out by emitting each of the register classes... to do this, we build
182 // a set of registers which belong to a register class, this is to ensure that
183 // each register is only in a single register class.

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445 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
446 Record *R = Regs[i].TheDef;
447 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
448 // Add information that R aliases all of the elements in the list... and
449 // that everything in the list aliases R.
450 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
451 Record *Reg = LI[j];
452 if (RegisterAliases[R].count(Reg))
175 CodeGenTarget Target;
176 EmitSourceFileHeader("Register Information Source Fragment", OS);
177
178 OS << "namespace llvm {\n\n";
179
180 // Start out by emitting each of the register classes... to do this, we build
181 // a set of registers which belong to a register class, this is to ensure that
182 // each register is only in a single register class.

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444 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
445 Record *R = Regs[i].TheDef;
446 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
447 // Add information that R aliases all of the elements in the list... and
448 // that everything in the list aliases R.
449 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
450 Record *Reg = LI[j];
451 if (RegisterAliases[R].count(Reg))
453 cerr << "Warning: register alias between " << getQualifiedName(R)
454 << " and " << getQualifiedName(Reg)
455 << " specified multiple times!\n";
452 errs() << "Warning: register alias between " << getQualifiedName(R)
453 << " and " << getQualifiedName(Reg)
454 << " specified multiple times!\n";
456 RegisterAliases[R].insert(Reg);
457
458 if (RegisterAliases[Reg].count(R))
455 RegisterAliases[R].insert(Reg);
456
457 if (RegisterAliases[Reg].count(R))
459 cerr << "Warning: register alias between " << getQualifiedName(R)
460 << " and " << getQualifiedName(Reg)
461 << " specified multiple times!\n";
458 errs() << "Warning: register alias between " << getQualifiedName(R)
459 << " and " << getQualifiedName(Reg)
460 << " specified multiple times!\n";
462 RegisterAliases[Reg].insert(R);
463 }
464 }
465
466 // Process sub-register sets.
467 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
468 Record *R = Regs[i].TheDef;
469 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
470 // Process sub-register set and add aliases information.
471 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
472 Record *SubReg = LI[j];
473 if (RegisterSubRegs[R].count(SubReg))
461 RegisterAliases[Reg].insert(R);
462 }
463 }
464
465 // Process sub-register sets.
466 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
467 Record *R = Regs[i].TheDef;
468 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
469 // Process sub-register set and add aliases information.
470 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
471 Record *SubReg = LI[j];
472 if (RegisterSubRegs[R].count(SubReg))
474 cerr << "Warning: register " << getQualifiedName(SubReg)
475 << " specified as a sub-register of " << getQualifiedName(R)
476 << " multiple times!\n";
473 errs() << "Warning: register " << getQualifiedName(SubReg)
474 << " specified as a sub-register of " << getQualifiedName(R)
475 << " multiple times!\n";
477 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
478 RegisterAliases);
479 }
480 }
481
482 // Print the SubregHashTable, a simple quadratically probed
483 // hash table for determining if a register is a subregister
484 // of another register.

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803 // Calculate the mapping of subregister+index pairs to physical registers.
804 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
805 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
806 int subRegIndex = SubRegs[i]->getValueAsInt("index");
807 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
808 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
809
810 if (From.size() != To.size()) {
476 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
477 RegisterAliases);
478 }
479 }
480
481 // Print the SubregHashTable, a simple quadratically probed
482 // hash table for determining if a register is a subregister
483 // of another register.

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802 // Calculate the mapping of subregister+index pairs to physical registers.
803 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
804 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
805 int subRegIndex = SubRegs[i]->getValueAsInt("index");
806 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
807 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
808
809 if (From.size() != To.size()) {
811 cerr << "Error: register list and sub-register list not of equal length"
812 << " in SubRegSet\n";
810 errs() << "Error: register list and sub-register list not of equal length"
811 << " in SubRegSet\n";
813 exit(1);
814 }
815
816 // For each entry in from/to vectors, insert the to register at index
817 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
818 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
819 }
820

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853
854 // First, just pull all provided information to the map
855 unsigned maxLength = 0;
856 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
857 Record *Reg = Registers[i].TheDef;
858 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
859 maxLength = std::max((size_t)maxLength, RegNums.size());
860 if (DwarfRegNums.count(Reg))
812 exit(1);
813 }
814
815 // For each entry in from/to vectors, insert the to register at index
816 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
817 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
818 }
819

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852
853 // First, just pull all provided information to the map
854 unsigned maxLength = 0;
855 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
856 Record *Reg = Registers[i].TheDef;
857 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
858 maxLength = std::max((size_t)maxLength, RegNums.size());
859 if (DwarfRegNums.count(Reg))
861 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
862 << "specified multiple times\n";
860 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
861 << "specified multiple times\n";
863 DwarfRegNums[Reg] = RegNums;
864 }
865
866 // Now we know maximal length of number list. Append -1's, where needed
867 for (DwarfRegNumsMapTy::iterator
868 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
869 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
870 I->second.push_back(-1);

--- 37 unchanged lines hidden --- 		862 DwarfRegNums[Reg] = RegNums;
863 }
864
865 // Now we know maximal length of number list. Append -1's, where needed
866 for (DwarfRegNumsMapTy::iterator
867 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
868 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
869 I->second.push_back(-1);

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