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FastISelEmitter.cpp (193323) FastISelEmitter.cpp (195340)
1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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15// and extracts instructions with obvious-looking patterns, and it emits
16// code to look up these instructions by type and operator.
17//
18//===----------------------------------------------------------------------===//
19
20#include "FastISelEmitter.h"
21#include "Record.h"
22#include "llvm/Support/Debug.h"
1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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15// and extracts instructions with obvious-looking patterns, and it emits
16// code to look up these instructions by type and operator.
17//
18//===----------------------------------------------------------------------===//
19
20#include "FastISelEmitter.h"
21#include "Record.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/Streams.h"
24#include "llvm/ADT/VectorExtras.h"
25using namespace llvm;
26
27namespace {
28
29/// InstructionMemo - This class holds additional information about an
30/// instruction needed to emit code for it.
31///

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114 return false;
115 } else
116 DstRC = RC;
117 Operands.push_back("r");
118 }
119 return true;
120 }
121
23#include "llvm/ADT/VectorExtras.h"
24using namespace llvm;
25
26namespace {
27
28/// InstructionMemo - This class holds additional information about an
29/// instruction needed to emit code for it.
30///

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113 return false;
114 } else
115 DstRC = RC;
116 Operands.push_back("r");
117 }
118 return true;
119 }
120
122 void PrintParameters(std::ostream &OS) const {
121 void PrintParameters(raw_ostream &OS) const {
123 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
124 if (Operands[i] == "r") {
125 OS << "unsigned Op" << i;
126 } else if (Operands[i] == "i") {
127 OS << "uint64_t imm" << i;
128 } else if (Operands[i] == "f") {
129 OS << "ConstantFP *f" << i;
130 } else {
131 assert("Unknown operand kind!");
132 abort();
133 }
134 if (i + 1 != e)
135 OS << ", ";
136 }
137 }
138
122 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
123 if (Operands[i] == "r") {
124 OS << "unsigned Op" << i;
125 } else if (Operands[i] == "i") {
126 OS << "uint64_t imm" << i;
127 } else if (Operands[i] == "f") {
128 OS << "ConstantFP *f" << i;
129 } else {
130 assert("Unknown operand kind!");
131 abort();
132 }
133 if (i + 1 != e)
134 OS << ", ";
135 }
136 }
137
139 void PrintArguments(std::ostream &OS,
138 void PrintArguments(raw_ostream &OS,
140 const std::vector<std::string>& PR) const {
141 assert(PR.size() == Operands.size());
142 bool PrintedArg = false;
143 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
144 if (PR[i] != "")
145 // Implicit physical register operand.
146 continue;
147

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158 PrintedArg = true;
159 } else {
160 assert("Unknown operand kind!");
161 abort();
162 }
163 }
164 }
165
139 const std::vector<std::string>& PR) const {
140 assert(PR.size() == Operands.size());
141 bool PrintedArg = false;
142 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
143 if (PR[i] != "")
144 // Implicit physical register operand.
145 continue;
146

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157 PrintedArg = true;
158 } else {
159 assert("Unknown operand kind!");
160 abort();
161 }
162 }
163 }
164
166 void PrintArguments(std::ostream &OS) const {
165 void PrintArguments(raw_ostream &OS) const {
167 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
168 if (Operands[i] == "r") {
169 OS << "Op" << i;
170 } else if (Operands[i] == "i") {
171 OS << "imm" << i;
172 } else if (Operands[i] == "f") {
173 OS << "f" << i;
174 } else {
175 assert("Unknown operand kind!");
176 abort();
177 }
178 if (i + 1 != e)
179 OS << ", ";
180 }
181 }
182
183
166 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
167 if (Operands[i] == "r") {
168 OS << "Op" << i;
169 } else if (Operands[i] == "i") {
170 OS << "imm" << i;
171 } else if (Operands[i] == "f") {
172 OS << "f" << i;
173 } else {
174 assert("Unknown operand kind!");
175 abort();
176 }
177 if (i + 1 != e)
178 OS << ", ";
179 }
180 }
181
182
184 void PrintManglingSuffix(std::ostream &OS,
183 void PrintManglingSuffix(raw_ostream &OS,
185 const std::vector<std::string>& PR) const {
186 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
187 if (PR[i] != "")
188 // Implicit physical register operand. e.g. Instruction::Mul expect to
189 // select to a binary op. On x86, mul may take a single operand with
190 // the other operand being implicit. We must emit something that looks
191 // like a binary instruction except for the very inner FastEmitInst_*
192 // call.
193 continue;
194 OS << Operands[i];
195 }
196 }
197
184 const std::vector<std::string>& PR) const {
185 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
186 if (PR[i] != "")
187 // Implicit physical register operand. e.g. Instruction::Mul expect to
188 // select to a binary op. On x86, mul may take a single operand with
189 // the other operand being implicit. We must emit something that looks
190 // like a binary instruction except for the very inner FastEmitInst_*
191 // call.
192 continue;
193 OS << Operands[i];
194 }
195 }
196
198 void PrintManglingSuffix(std::ostream &OS) const {
197 void PrintManglingSuffix(raw_ostream &OS) const {
199 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
200 OS << Operands[i];
201 }
202 }
203};
204
205class FastISelMap {
206 typedef std::map<std::string, InstructionMemo> PredMap;

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212 OperandsOpcodeTypeRetPredMap SimplePatterns;
213
214 std::string InstNS;
215
216public:
217 explicit FastISelMap(std::string InstNS);
218
219 void CollectPatterns(CodeGenDAGPatterns &CGP);
198 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
199 OS << Operands[i];
200 }
201 }
202};
203
204class FastISelMap {
205 typedef std::map<std::string, InstructionMemo> PredMap;

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211 OperandsOpcodeTypeRetPredMap SimplePatterns;
212
213 std::string InstNS;
214
215public:
216 explicit FastISelMap(std::string InstNS);
217
218 void CollectPatterns(CodeGenDAGPatterns &CGP);
220 void PrintClass(std::ostream &OS);
221 void PrintFunctionDefinitions(std::ostream &OS);
219 void PrintClass(raw_ostream &OS);
220 void PrintFunctionDefinitions(raw_ostream &OS);
222};
223
224}
225
226static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
227 return CGP.getSDNodeInfo(Op).getEnumName();
228}
229

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363 PhysRegInputs
364 };
365 assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
366 "Duplicate pattern!");
367 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
368 }
369}
370
221};
222
223}
224
225static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
226 return CGP.getSDNodeInfo(Op).getEnumName();
227}
228

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362 PhysRegInputs
363 };
364 assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
365 "Duplicate pattern!");
366 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
367 }
368}
369
371void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
370void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
372 // Now emit code for all the patterns that we collected.
373 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
374 OE = SimplePatterns.end(); OI != OE; ++OI) {
375 const OperandsSignature &Operands = OI->first;
376 const OpcodeTypeRetPredMap &OTM = OI->second;
377
378 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
379 I != E; ++I) {

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609 }
610 OS << " default: return 0;\n";
611 OS << " }\n";
612 OS << "}\n";
613 OS << "\n";
614 }
615}
616
371 // Now emit code for all the patterns that we collected.
372 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
373 OE = SimplePatterns.end(); OI != OE; ++OI) {
374 const OperandsSignature &Operands = OI->first;
375 const OpcodeTypeRetPredMap &OTM = OI->second;
376
377 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
378 I != E; ++I) {

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608 }
609 OS << " default: return 0;\n";
610 OS << " }\n";
611 OS << "}\n";
612 OS << "\n";
613 }
614}
615
617void FastISelEmitter::run(std::ostream &OS) {
616void FastISelEmitter::run(raw_ostream &OS) {
618 const CodeGenTarget &Target = CGP.getTargetInfo();
619
620 // Determine the target's namespace name.
621 std::string InstNS = Target.getInstNamespace() + "::";
622 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
623
624 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
625 Target.getName() + " target", OS);
626
627 FastISelMap F(InstNS);
628 F.CollectPatterns(CGP);
629 F.PrintFunctionDefinitions(OS);
630}
631
632FastISelEmitter::FastISelEmitter(RecordKeeper &R)
633 : Records(R),
634 CGP(R) {
635}
636
617 const CodeGenTarget &Target = CGP.getTargetInfo();
618
619 // Determine the target's namespace name.
620 std::string InstNS = Target.getInstNamespace() + "::";
621 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
622
623 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
624 Target.getName() + " target", OS);
625
626 FastISelMap F(InstNS);
627 F.CollectPatterns(CGP);
628 F.PrintFunctionDefinitions(OS);
629}
630
631FastISelEmitter::FastISelEmitter(RecordKeeper &R)
632 : Records(R),
633 CGP(R) {
634}
635