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PPCInstrInfo.cpp (193323) PPCInstrInfo.cpp (195340)
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 430 unchanged lines hidden (view full) ---

439 FrameIdx));
440 }
441 } else if (RC == PPC::CRBITRCRegisterClass) {
442 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
443 // backend currently only uses CR1EQ as an individual bit, this should
444 // not cause any bug. If we need other uses of CR bits, the following
445 // code may be invalid.
446 unsigned Reg = 0;
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 430 unchanged lines hidden (view full) ---

439 FrameIdx));
440 }
441 } else if (RC == PPC::CRBITRCRegisterClass) {
442 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
443 // backend currently only uses CR1EQ as an individual bit, this should
444 // not cause any bug. If we need other uses of CR bits, the following
445 // code may be invalid.
446 unsigned Reg = 0;
447 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
447 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
448 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
448 Reg = PPC::CR0;
449 Reg = PPC::CR0;
449 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
450 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
451 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
450 Reg = PPC::CR1;
452 Reg = PPC::CR1;
451 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
453 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
454 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
452 Reg = PPC::CR2;
455 Reg = PPC::CR2;
453 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
456 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
457 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
454 Reg = PPC::CR3;
458 Reg = PPC::CR3;
455 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
459 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
460 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
456 Reg = PPC::CR4;
461 Reg = PPC::CR4;
457 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
462 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
463 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
458 Reg = PPC::CR5;
464 Reg = PPC::CR5;
459 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
465 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
466 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
460 Reg = PPC::CR6;
467 Reg = PPC::CR6;
461 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
468 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
469 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
462 Reg = PPC::CR7;
463
464 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
465 PPC::CRRCRegisterClass, NewMIs);
466
467 } else if (RC == PPC::VRRCRegisterClass) {
468 // We don't have indexed addressing for vector loads. Emit:
469 // R0 = ADDI FI#

--- 112 unchanged lines hidden (view full) ---

582 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
583 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
584 }
585
586 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
587 } else if (RC == PPC::CRBITRCRegisterClass) {
588
589 unsigned Reg = 0;
470 Reg = PPC::CR7;
471
472 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
473 PPC::CRRCRegisterClass, NewMIs);
474
475 } else if (RC == PPC::VRRCRegisterClass) {
476 // We don't have indexed addressing for vector loads. Emit:
477 // R0 = ADDI FI#

--- 112 unchanged lines hidden (view full) ---

590 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
591 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
592 }
593
594 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
595 } else if (RC == PPC::CRBITRCRegisterClass) {
596
597 unsigned Reg = 0;
590 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
598 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
599 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
591 Reg = PPC::CR0;
600 Reg = PPC::CR0;
592 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
601 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
602 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
593 Reg = PPC::CR1;
603 Reg = PPC::CR1;
594 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
604 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
605 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
595 Reg = PPC::CR2;
606 Reg = PPC::CR2;
596 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
607 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
608 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
597 Reg = PPC::CR3;
609 Reg = PPC::CR3;
598 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
610 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
611 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
599 Reg = PPC::CR4;
612 Reg = PPC::CR4;
600 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
613 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
614 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
601 Reg = PPC::CR5;
615 Reg = PPC::CR5;
602 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
616 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
617 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
603 Reg = PPC::CR6;
618 Reg = PPC::CR6;
604 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
619 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
620 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
605 Reg = PPC::CR7;
606
607 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
608 PPC::CRRCRegisterClass, NewMIs);
609
610 } else if (RC == PPC::VRRCRegisterClass) {
611 // We don't have indexed addressing for vector loads. Emit:
612 // R0 = ADDI FI#

--- 73 unchanged lines hidden (view full) ---

686 unsigned OpNum = Ops[0];
687
688 MachineInstr *NewMI = NULL;
689 if ((Opc == PPC::OR &&
690 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
691 if (OpNum == 0) { // move -> store
692 unsigned InReg = MI->getOperand(1).getReg();
693 bool isKill = MI->getOperand(1).isKill();
621 Reg = PPC::CR7;
622
623 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
624 PPC::CRRCRegisterClass, NewMIs);
625
626 } else if (RC == PPC::VRRCRegisterClass) {
627 // We don't have indexed addressing for vector loads. Emit:
628 // R0 = ADDI FI#

--- 73 unchanged lines hidden (view full) ---

702 unsigned OpNum = Ops[0];
703
704 MachineInstr *NewMI = NULL;
705 if ((Opc == PPC::OR &&
706 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
707 if (OpNum == 0) { // move -> store
708 unsigned InReg = MI->getOperand(1).getReg();
709 bool isKill = MI->getOperand(1).isKill();
710 bool isUndef = MI->getOperand(1).isUndef();
694 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
711 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
695 .addReg(InReg, getKillRegState(isKill)),
712 .addReg(InReg,
713 getKillRegState(isKill) |
714 getUndefRegState(isUndef)),
696 FrameIndex);
697 } else { // move -> load
698 unsigned OutReg = MI->getOperand(0).getReg();
699 bool isDead = MI->getOperand(0).isDead();
715 FrameIndex);
716 } else { // move -> load
717 unsigned OutReg = MI->getOperand(0).getReg();
718 bool isDead = MI->getOperand(0).isDead();
719 bool isUndef = MI->getOperand(0).isUndef();
700 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
701 .addReg(OutReg,
702 RegState::Define |
720 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
721 .addReg(OutReg,
722 RegState::Define |
703 getDeadRegState(isDead)),
723 getDeadRegState(isDead) |
724 getUndefRegState(isUndef)),
704 FrameIndex);
705 }
706 } else if ((Opc == PPC::OR8 &&
707 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
708 if (OpNum == 0) { // move -> store
709 unsigned InReg = MI->getOperand(1).getReg();
710 bool isKill = MI->getOperand(1).isKill();
725 FrameIndex);
726 }
727 } else if ((Opc == PPC::OR8 &&
728 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
729 if (OpNum == 0) { // move -> store
730 unsigned InReg = MI->getOperand(1).getReg();
731 bool isKill = MI->getOperand(1).isKill();
732 bool isUndef = MI->getOperand(1).isUndef();
711 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
733 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
712 .addReg(InReg, getKillRegState(isKill)),
734 .addReg(InReg,
735 getKillRegState(isKill) |
736 getUndefRegState(isUndef)),
713 FrameIndex);
714 } else { // move -> load
715 unsigned OutReg = MI->getOperand(0).getReg();
716 bool isDead = MI->getOperand(0).isDead();
737 FrameIndex);
738 } else { // move -> load
739 unsigned OutReg = MI->getOperand(0).getReg();
740 bool isDead = MI->getOperand(0).isDead();
741 bool isUndef = MI->getOperand(0).isUndef();
717 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
718 .addReg(OutReg,
719 RegState::Define |
742 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
743 .addReg(OutReg,
744 RegState::Define |
720 getDeadRegState(isDead)),
745 getDeadRegState(isDead) |
746 getUndefRegState(isUndef)),
721 FrameIndex);
722 }
723 } else if (Opc == PPC::FMRD) {
724 if (OpNum == 0) { // move -> store
725 unsigned InReg = MI->getOperand(1).getReg();
726 bool isKill = MI->getOperand(1).isKill();
747 FrameIndex);
748 }
749 } else if (Opc == PPC::FMRD) {
750 if (OpNum == 0) { // move -> store
751 unsigned InReg = MI->getOperand(1).getReg();
752 bool isKill = MI->getOperand(1).isKill();
753 bool isUndef = MI->getOperand(1).isUndef();
727 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
754 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
728 .addReg(InReg, getKillRegState(isKill)),
755 .addReg(InReg,
756 getKillRegState(isKill) |
757 getUndefRegState(isUndef)),
729 FrameIndex);
730 } else { // move -> load
731 unsigned OutReg = MI->getOperand(0).getReg();
732 bool isDead = MI->getOperand(0).isDead();
758 FrameIndex);
759 } else { // move -> load
760 unsigned OutReg = MI->getOperand(0).getReg();
761 bool isDead = MI->getOperand(0).isDead();
762 bool isUndef = MI->getOperand(0).isUndef();
733 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
734 .addReg(OutReg,
735 RegState::Define |
763 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
764 .addReg(OutReg,
765 RegState::Define |
736 getDeadRegState(isDead)),
766 getDeadRegState(isDead) |
767 getUndefRegState(isUndef)),
737 FrameIndex);
738 }
739 } else if (Opc == PPC::FMRS) {
740 if (OpNum == 0) { // move -> store
741 unsigned InReg = MI->getOperand(1).getReg();
742 bool isKill = MI->getOperand(1).isKill();
768 FrameIndex);
769 }
770 } else if (Opc == PPC::FMRS) {
771 if (OpNum == 0) { // move -> store
772 unsigned InReg = MI->getOperand(1).getReg();
773 bool isKill = MI->getOperand(1).isKill();
774 bool isUndef = MI->getOperand(1).isUndef();
743 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
775 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
744 .addReg(InReg, getKillRegState(isKill)),
776 .addReg(InReg,
777 getKillRegState(isKill) |
778 getUndefRegState(isUndef)),
745 FrameIndex);
746 } else { // move -> load
747 unsigned OutReg = MI->getOperand(0).getReg();
748 bool isDead = MI->getOperand(0).isDead();
779 FrameIndex);
780 } else { // move -> load
781 unsigned OutReg = MI->getOperand(0).getReg();
782 bool isDead = MI->getOperand(0).isDead();
783 bool isUndef = MI->getOperand(0).isUndef();
749 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
750 .addReg(OutReg,
751 RegState::Define |
784 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
785 .addReg(OutReg,
786 RegState::Define |
752 getDeadRegState(isDead)),
787 getDeadRegState(isDead) |
788 getUndefRegState(isUndef)),
753 FrameIndex);
754 }
755 }
756
757 return NewMI;
758}
759
760bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,

--- 58 unchanged lines hidden --- 		789 FrameIndex);
790 }
791 }
792
793 return NewMI;
794}
795
796bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,

--- 58 unchanged lines hidden ---