| MipsInstrInfo.cpp (193399) | MipsInstrInfo.cpp (195340) |
|---|---|
| 1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 277 unchanged lines hidden (view full) --- 286 case Mips::ADDu: 287 if ((MI->getOperand(0).isReg()) && 288 (MI->getOperand(1).isReg()) && 289 (MI->getOperand(1).getReg() == Mips::ZERO) && 290 (MI->getOperand(2).isReg())) { 291 if (Ops[0] == 0) { // COPY -> STORE 292 unsigned SrcReg = MI->getOperand(2).getReg(); 293 bool isKill = MI->getOperand(2).isKill(); | 1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 277 unchanged lines hidden (view full) --- 286 case Mips::ADDu: 287 if ((MI->getOperand(0).isReg()) && 288 (MI->getOperand(1).isReg()) && 289 (MI->getOperand(1).getReg() == Mips::ZERO) && 290 (MI->getOperand(2).isReg())) { 291 if (Ops[0] == 0) { // COPY -> STORE 292 unsigned SrcReg = MI->getOperand(2).getReg(); 293 bool isKill = MI->getOperand(2).isKill(); |
| 294 bool isUndef = MI->getOperand(2).isUndef(); |
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| 294 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) | 295 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) |
| 295 .addReg(SrcReg, getKillRegState(isKill)) | 296 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 296 .addImm(0).addFrameIndex(FI); 297 } else { // COPY -> LOAD 298 unsigned DstReg = MI->getOperand(0).getReg(); 299 bool isDead = MI->getOperand(0).isDead(); | 297 .addImm(0).addFrameIndex(FI); 298 } else { // COPY -> LOAD 299 unsigned DstReg = MI->getOperand(0).getReg(); 300 bool isDead = MI->getOperand(0).isDead(); |
| 301 bool isUndef = MI->getOperand(0).isUndef(); |
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| 300 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) | 302 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) |
| 301 .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) | 303 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | 304 getUndefRegState(isUndef)) |
| 302 .addImm(0).addFrameIndex(FI); 303 } 304 } 305 break; 306 case Mips::FMOV_S32: 307 case Mips::FMOV_D32: 308 if ((MI->getOperand(0).isReg()) && 309 (MI->getOperand(1).isReg())) { --- 6 unchanged lines hidden (view full) --- 316 } else { 317 assert(RC == Mips::AFGR64RegisterClass); 318 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1; 319 } 320 321 if (Ops[0] == 0) { // COPY -> STORE 322 unsigned SrcReg = MI->getOperand(1).getReg(); 323 bool isKill = MI->getOperand(1).isKill(); | 305 .addImm(0).addFrameIndex(FI); 306 } 307 } 308 break; 309 case Mips::FMOV_S32: 310 case Mips::FMOV_D32: 311 if ((MI->getOperand(0).isReg()) && 312 (MI->getOperand(1).isReg())) { --- 6 unchanged lines hidden (view full) --- 319 } else { 320 assert(RC == Mips::AFGR64RegisterClass); 321 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1; 322 } 323 324 if (Ops[0] == 0) { // COPY -> STORE 325 unsigned SrcReg = MI->getOperand(1).getReg(); 326 bool isKill = MI->getOperand(1).isKill(); |
| 327 bool isUndef = MI->getOperand(2).isUndef(); |
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| 324 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) | 328 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) |
| 325 .addReg(SrcReg, getKillRegState(isKill)) | 329 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 326 .addImm(0).addFrameIndex(FI) ; 327 } else { // COPY -> LOAD 328 unsigned DstReg = MI->getOperand(0).getReg(); 329 bool isDead = MI->getOperand(0).isDead(); | 330 .addImm(0).addFrameIndex(FI) ; 331 } else { // COPY -> LOAD 332 unsigned DstReg = MI->getOperand(0).getReg(); 333 bool isDead = MI->getOperand(0).isDead(); |
| 334 bool isUndef = MI->getOperand(0).isUndef(); |
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| 330 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) | 335 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) |
| 331 .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) | 336 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | 337 getUndefRegState(isUndef)) |
| 332 .addImm(0).addFrameIndex(FI); 333 } 334 } 335 break; 336 } 337 338 return NewMI; 339} --- 300 unchanged lines hidden (view full) --- 640 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 641 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 642 643 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 644 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP, 645 Mips::CPURegsRegisterClass, 646 Mips::CPURegsRegisterClass); 647 assert(Ok && "Couldn't assign to global base register!"); | 338 .addImm(0).addFrameIndex(FI); 339 } 340 } 341 break; 342 } 343 344 return NewMI; 345} --- 300 unchanged lines hidden (view full) --- 646 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 647 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 648 649 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 650 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP, 651 Mips::CPURegsRegisterClass, 652 Mips::CPURegsRegisterClass); 653 assert(Ok && "Couldn't assign to global base register!"); |
| 654 Ok = Ok; // Silence warning when assertions are turned off. |
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| 648 RegInfo.addLiveIn(Mips::GP); 649 650 MipsFI->setGlobalBaseReg(GlobalBaseReg); 651 return GlobalBaseReg; 652} | 655 RegInfo.addLiveIn(Mips::GP); 656 657 MipsFI->setGlobalBaseReg(GlobalBaseReg); 658 return GlobalBaseReg; 659} |