108c108
< { ARM::t2LDRi12,ARM::tLDR, 0, 5, 0, 1, 0, 0,0, 1 },
---
> { ARM::t2LDRi12,ARM::tLDR, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
116c116
< { ARM::t2STRi12,ARM::tSTR, 0, 5, 0, 1, 0, 0,0, 1 },
---
> { ARM::t2STRi12,ARM::tSTR, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
247,248c247,253
< if (isSPOk && Reg == ARM::SP)
< continue;
---
> if (Reg == ARM::SP) {
> if (isSPOk)
> continue;
> if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
> // Special case for these ldr / str with sp as base register.
> continue;
> }
263a269
> bool HasOffReg = true;
266a273
> uint8_t ImmLimit = Entry.Imm1Limit;
271c278,284
< case ARM::t2STRi12:
---
> case ARM::t2STRi12: {
> unsigned BaseReg = MI->getOperand(1).getReg();
> if (BaseReg == ARM::SP) {
> Opc = Entry.NarrowOpc2;
> ImmLimit = Entry.Imm2Limit;
> HasOffReg = false;
> }
274a288
> }
328c342
< unsigned MaxOffset = ((1 << Entry.Imm1Limit) - 1) * Scale;
---
> unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
340c354
< if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) {
---
> if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
348c362,363
< MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
---
> if (HasOffReg)
> MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
354a370,372
> // Transfer memoperands.
> (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
>