1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24 "ARM v4T">;
25def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26 "ARM v5T">;
27def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28 "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30 "ARM v6">;
31def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32 "ARM v6t2">;
33def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34 "ARM v7A">;
35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36 "Enable VFP2 instructions">;
37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38 "Enable VFP3 instructions">;
39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40 "Enable NEON instructions">;
41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42 "Enable Thumb2 instructions">;
43
44//===----------------------------------------------------------------------===//
45// ARM Processors supported.
46//
47
48include "ARMSchedule.td"
49
50class ProcNoItin<string Name, list<SubtargetFeature> Features>
51 : Processor<Name, GenericItineraries, Features>;
52
53// V4 Processors.
54def : ProcNoItin<"generic", []>;
55def : ProcNoItin<"arm8", []>;
56def : ProcNoItin<"arm810", []>;
57def : ProcNoItin<"strongarm", []>;
58def : ProcNoItin<"strongarm110", []>;
59def : ProcNoItin<"strongarm1100", []>;
60def : ProcNoItin<"strongarm1110", []>;
61
62// V4T Processors.
63def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
64def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
65def : ProcNoItin<"arm710t", [ArchV4T]>;
66def : ProcNoItin<"arm720t", [ArchV4T]>;
67def : ProcNoItin<"arm9", [ArchV4T]>;
68def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
69def : ProcNoItin<"arm920", [ArchV4T]>;
70def : ProcNoItin<"arm920t", [ArchV4T]>;
71def : ProcNoItin<"arm922t", [ArchV4T]>;
72def : ProcNoItin<"arm940t", [ArchV4T]>;
73def : ProcNoItin<"ep9312", [ArchV4T]>;
74
75// V5T Processors.
76def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
77def : ProcNoItin<"arm1020t", [ArchV5T]>;
78
79// V5TE Processors.
80def : ProcNoItin<"arm9e", [ArchV5TE]>;
81def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
82def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
83def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
84def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
85def : ProcNoItin<"arm10e", [ArchV5TE]>;
86def : ProcNoItin<"arm1020e", [ArchV5TE]>;
87def : ProcNoItin<"arm1022e", [ArchV5TE]>;
88def : ProcNoItin<"xscale", [ArchV5TE]>;
89def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
90
91// V6 Processors.
| 1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24 "ARM v4T">;
25def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26 "ARM v5T">;
27def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28 "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30 "ARM v6">;
31def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32 "ARM v6t2">;
33def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34 "ARM v7A">;
35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36 "Enable VFP2 instructions">;
37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38 "Enable VFP3 instructions">;
39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40 "Enable NEON instructions">;
41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42 "Enable Thumb2 instructions">;
43
44//===----------------------------------------------------------------------===//
45// ARM Processors supported.
46//
47
48include "ARMSchedule.td"
49
50class ProcNoItin<string Name, list<SubtargetFeature> Features>
51 : Processor<Name, GenericItineraries, Features>;
52
53// V4 Processors.
54def : ProcNoItin<"generic", []>;
55def : ProcNoItin<"arm8", []>;
56def : ProcNoItin<"arm810", []>;
57def : ProcNoItin<"strongarm", []>;
58def : ProcNoItin<"strongarm110", []>;
59def : ProcNoItin<"strongarm1100", []>;
60def : ProcNoItin<"strongarm1110", []>;
61
62// V4T Processors.
63def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
64def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
65def : ProcNoItin<"arm710t", [ArchV4T]>;
66def : ProcNoItin<"arm720t", [ArchV4T]>;
67def : ProcNoItin<"arm9", [ArchV4T]>;
68def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
69def : ProcNoItin<"arm920", [ArchV4T]>;
70def : ProcNoItin<"arm920t", [ArchV4T]>;
71def : ProcNoItin<"arm922t", [ArchV4T]>;
72def : ProcNoItin<"arm940t", [ArchV4T]>;
73def : ProcNoItin<"ep9312", [ArchV4T]>;
74
75// V5T Processors.
76def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
77def : ProcNoItin<"arm1020t", [ArchV5T]>;
78
79// V5TE Processors.
80def : ProcNoItin<"arm9e", [ArchV5TE]>;
81def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
82def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
83def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
84def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
85def : ProcNoItin<"arm10e", [ArchV5TE]>;
86def : ProcNoItin<"arm1020e", [ArchV5TE]>;
87def : ProcNoItin<"arm1022e", [ArchV5TE]>;
88def : ProcNoItin<"xscale", [ArchV5TE]>;
89def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
90
91// V6 Processors.
|
92def : ProcNoItin<"arm1136j-s", [ArchV6]>;
93def : ProcNoItin<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
94def : ProcNoItin<"arm1176jz-s", [ArchV6]>;
95def : ProcNoItin<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
96def : ProcNoItin<"mpcorenovfp", [ArchV6]>;
97def : ProcNoItin<"mpcore", [ArchV6, FeatureVFP2]>;
| 92def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
93def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
94def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
95def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
96def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
97def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
|
102
103// V7 Processors.
104def : Processor<"cortex-a8", CortexA8Itineraries,
105 [ArchV7A, FeatureThumb2, FeatureNEON]>;
106def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
107
108//===----------------------------------------------------------------------===//
109// Register File Description
110//===----------------------------------------------------------------------===//
111
112include "ARMRegisterInfo.td"
113
114include "ARMCallingConv.td"
115
116//===----------------------------------------------------------------------===//
117// Instruction Descriptions
118//===----------------------------------------------------------------------===//
119
120include "ARMInstrInfo.td"
121
122def ARMInstrInfo : InstrInfo {
123 // Define how we want to layout our target-specific information field.
124 let TSFlagsFields = ["AddrModeBits",
125 "SizeFlag",
126 "IndexModeBits",
127 "Form",
128 "isUnaryDataProc",
129 "canXformTo16Bit",
130 "Dom"];
131 let TSFlagsShifts = [0,
132 4,
133 7,
134 9,
135 15,
136 16,
137 17];
138}
139
140//===----------------------------------------------------------------------===//
141// Declare the target which we are implementing
142//===----------------------------------------------------------------------===//
143
144def ARM : Target {
145 // Pull in Instruction Info:
146 let InstructionSet = ARMInstrInfo;
147}
| 104
105// V7 Processors.
106def : Processor<"cortex-a8", CortexA8Itineraries,
107 [ArchV7A, FeatureThumb2, FeatureNEON]>;
108def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
109
110//===----------------------------------------------------------------------===//
111// Register File Description
112//===----------------------------------------------------------------------===//
113
114include "ARMRegisterInfo.td"
115
116include "ARMCallingConv.td"
117
118//===----------------------------------------------------------------------===//
119// Instruction Descriptions
120//===----------------------------------------------------------------------===//
121
122include "ARMInstrInfo.td"
123
124def ARMInstrInfo : InstrInfo {
125 // Define how we want to layout our target-specific information field.
126 let TSFlagsFields = ["AddrModeBits",
127 "SizeFlag",
128 "IndexModeBits",
129 "Form",
130 "isUnaryDataProc",
131 "canXformTo16Bit",
132 "Dom"];
133 let TSFlagsShifts = [0,
134 4,
135 7,
136 9,
137 15,
138 16,
139 17];
140}
141
142//===----------------------------------------------------------------------===//
143// Declare the target which we are implementing
144//===----------------------------------------------------------------------===//
145
146def ARM : Target {
147 // Pull in Instruction Info:
148 let InstructionSet = ARMInstrInfo;
149}
|