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MachineInstr.cpp (195098) MachineInstr.cpp (195340)
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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115 OpKind = MO_Immediate;
116 Contents.ImmVal = ImmVal;
117}
118
119/// ChangeToRegister - Replace this operand with a new register operand of
120/// the specified value. If an operand is known to be an register already,
121/// the setReg method should be used.
122void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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115 OpKind = MO_Immediate;
116 Contents.ImmVal = ImmVal;
117}
118
119/// ChangeToRegister - Replace this operand with a new register operand of
120/// the specified value. If an operand is known to be an register already,
121/// the setReg method should be used.
122void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
123 bool isKill, bool isDead) {
123 bool isKill, bool isDead, bool isUndef) {
124 // If this operand is already a register operand, use setReg to update the
125 // register's use/def lists.
126 if (isReg()) {
127 assert(!isEarlyClobber());
128 setReg(Reg);
129 } else {
130 // Otherwise, change this to a register and set the reg#.
131 OpKind = MO_Register;

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138 if (MachineFunction *MF = MBB->getParent())
139 AddRegOperandToRegInfo(&MF->getRegInfo());
140 }
141
142 IsDef = isDef;
143 IsImp = isImp;
144 IsKill = isKill;
145 IsDead = isDead;
124 // If this operand is already a register operand, use setReg to update the
125 // register's use/def lists.
126 if (isReg()) {
127 assert(!isEarlyClobber());
128 setReg(Reg);
129 } else {
130 // Otherwise, change this to a register and set the reg#.
131 OpKind = MO_Register;

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138 if (MachineFunction *MF = MBB->getParent())
139 AddRegOperandToRegInfo(&MF->getRegInfo());
140 }
141
142 IsDef = isDef;
143 IsImp = isImp;
144 IsKill = isKill;
145 IsDead = isDead;
146 IsUndef = isUndef;
146 IsEarlyClobber = false;
147 SubReg = 0;
148}
149
150/// isIdenticalTo - Return true if this operand is identical to the specified
151/// operand.
152bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
153 if (getType() != Other.getType() ||

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201 TM = &MF->getTarget();
202
203 if (TM)
204 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
205 else
206 OS << "%mreg" << getReg();
207 }
208
147 IsEarlyClobber = false;
148 SubReg = 0;
149}
150
151/// isIdenticalTo - Return true if this operand is identical to the specified
152/// operand.
153bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
154 if (getType() != Other.getType() ||

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202 TM = &MF->getTarget();
203
204 if (TM)
205 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
206 else
207 OS << "%mreg" << getReg();
208 }
209
209 if (getSubReg() != 0) {
210 if (getSubReg() != 0)
210 OS << ':' << getSubReg();
211 OS << ':' << getSubReg();
211 }
212
212
213 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
213 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
214 isEarlyClobber()) {
214 OS << '<';
215 bool NeedComma = false;
216 if (isImplicit()) {
217 if (NeedComma) OS << ',';
218 OS << (isDef() ? "imp-def" : "imp-use");
219 NeedComma = true;
220 } else if (isDef()) {
221 if (NeedComma) OS << ',';
222 if (isEarlyClobber())
223 OS << "earlyclobber,";
224 OS << "def";
225 NeedComma = true;
226 }
215 OS << '<';
216 bool NeedComma = false;
217 if (isImplicit()) {
218 if (NeedComma) OS << ',';
219 OS << (isDef() ? "imp-def" : "imp-use");
220 NeedComma = true;
221 } else if (isDef()) {
222 if (NeedComma) OS << ',';
223 if (isEarlyClobber())
224 OS << "earlyclobber,";
225 OS << "def";
226 NeedComma = true;
227 }
227 if (isKill() || isDead()) {
228 if (isKill() || isDead() || isUndef()) {
228 if (NeedComma) OS << ',';
229 if (isKill()) OS << "kill";
230 if (isDead()) OS << "dead";
229 if (NeedComma) OS << ',';
230 if (isKill()) OS << "kill";
231 if (isDead()) OS << "dead";
232 if (isUndef()) {
233 if (isKill() || isDead())
234 OS << ',';
235 OS << "undef";
236 }
231 }
232 OS << '>';
233 }
234 break;
235 case MachineOperand::MO_Immediate:
236 OS << getImm();
237 break;
238 case MachineOperand::MO_FPImmediate:

--- 882 unchanged lines hidden --- 		237 }
238 OS << '>';
239 }
240 break;
241 case MachineOperand::MO_Immediate:
242 OS << getImm();
243 break;
244 case MachineOperand::MO_FPImmediate:

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