1/* Subroutines used by or related to instruction recognition. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 --- 5 unchanged lines hidden (view full) --- 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23#include "config.h" 24#include "system.h" |
25#include "coretypes.h" 26#include "tm.h" |
27#include "rtl.h" 28#include "tm_p.h" 29#include "insn-config.h" 30#include "insn-attr.h" 31#include "hard-reg-set.h" 32#include "recog.h" 33#include "regs.h" 34#include "expr.h" --- 16 unchanged lines hidden (view full) --- 51#ifndef STACK_POP_CODE 52#ifdef STACK_GROWS_DOWNWARD 53#define STACK_POP_CODE POST_INC 54#else 55#define STACK_POP_CODE POST_DEC 56#endif 57#endif 58 |
59static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx); 60static rtx *find_single_use_1 (rtx, rtx *); 61static void validate_replace_src_1 (rtx *, void *); 62static rtx split_insn (rtx); |
63 64/* Nonzero means allow operands to be volatile. 65 This should be 0 if you are generating rtl, such as if you are calling 66 the functions in optabs.c and expmed.c (most of the time). 67 This should be 1 if all valid insns need to be recognized, 68 such as in regclass.c and final.c and reload.c. 69 70 init_recog and init_recog_no_volatile are responsible for setting this. */ --- 12 unchanged lines hidden (view full) --- 83int which_alternative; 84 85/* Nonzero after end of reload pass. 86 Set to 1 or 0 by toplev.c. 87 Controls the significance of (SUBREG (MEM)). */ 88 89int reload_completed; 90 |
91/* Nonzero after thread_prologue_and_epilogue_insns has run. */ 92int epilogue_completed; 93 |
94/* Initialize data used by the function `recog'. 95 This must be called once in the compilation of a function 96 before any insn recognition may be done in the function. */ 97 98void |
99init_recog_no_volatile (void) |
100{ 101 volatile_ok = 0; 102} 103 104void |
105init_recog (void) |
106{ 107 volatile_ok = 1; 108} 109 110/* Try recognizing the instruction INSN, 111 and return the code number that results. 112 Remember the code so that repeated calls do not 113 need to spend the time for actual rerecognition. 114 115 This function is the normal interface to instruction recognition. 116 The automatically-generated function `recog' is normally called 117 through this one. (The only exception is in combine.c.) */ 118 119int |
120recog_memoized_1 (rtx insn) |
121{ 122 if (INSN_CODE (insn) < 0) 123 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); 124 return INSN_CODE (insn); 125} 126 127/* Check that X is an insn-body for an `asm' with operands 128 and that the operands mentioned in it are legitimate. */ 129 130int |
131check_asm_operands (rtx x) |
132{ 133 int noperands; 134 rtx *operands; 135 const char **constraints; 136 int i; 137 138 /* Post-reload, be more strict with things. */ 139 if (reload_completed) --- 5 unchanged lines hidden (view full) --- 145 } 146 147 noperands = asm_noperands (x); 148 if (noperands < 0) 149 return 0; 150 if (noperands == 0) 151 return 1; 152 |
153 operands = alloca (noperands * sizeof (rtx)); 154 constraints = alloca (noperands * sizeof (char *)); |
155 156 decode_asm_operands (x, operands, NULL, constraints, NULL); 157 158 for (i = 0; i < noperands; i++) 159 { 160 const char *c = constraints[i]; 161 if (c[0] == '%') 162 c++; --- 36 unchanged lines hidden (view full) --- 199 function `apply_change_group' will validate and apply the changes. 200 201 If IN_GROUP is zero, this is a single change. Try to recognize the insn 202 or validate the memory reference with the change applied. If the result 203 is not valid for the machine, suppress the change and return zero. 204 Otherwise, perform the change and return 1. */ 205 206int |
207validate_change (rtx object, rtx *loc, rtx new, int in_group) |
208{ 209 rtx old = *loc; 210 211 if (old == new || rtx_equal_p (old, new)) 212 return 1; 213 214 if (in_group == 0 && num_changes != 0) 215 abort (); --- 5 unchanged lines hidden (view full) --- 221 { 222 if (changes_allocated == 0) 223 /* This value allows for repeated substitutions inside complex 224 indexed addresses, or changes in up to 5 insns. */ 225 changes_allocated = MAX_RECOG_OPERANDS * 5; 226 else 227 changes_allocated *= 2; 228 |
229 changes = xrealloc (changes, sizeof (change_t) * changes_allocated); |
230 } 231 232 changes[num_changes].object = object; 233 changes[num_changes].loc = loc; 234 changes[num_changes].old = old; 235 236 if (object && GET_CODE (object) != MEM) 237 { --- 13 unchanged lines hidden (view full) --- 251 else 252 return apply_change_group (); 253} 254 255/* This subroutine of apply_change_group verifies whether the changes to INSN 256 were valid; i.e. whether INSN can still be recognized. */ 257 258int |
259insn_invalid_p (rtx insn) |
260{ 261 rtx pat = PATTERN (insn); 262 int num_clobbers = 0; 263 /* If we are before reload and the pattern is a SET, see if we can add 264 clobbers. */ 265 int icode = recog (pat, insn, 266 (GET_CODE (pat) == SET 267 && ! reload_completed && ! reload_in_progress) --- 33 unchanged lines hidden (view full) --- 301 } 302 303 INSN_CODE (insn) = icode; 304 return 0; 305} 306 307/* Return number of changes made and not validated yet. */ 308int |
309num_changes_pending (void) |
310{ 311 return num_changes; 312} 313 314/* Apply a group of changes previously issued with `validate_change'. 315 Return 1 if all changes are valid, zero otherwise. */ 316 317int |
318apply_change_group (void) |
319{ 320 int i; 321 rtx last_validated = NULL_RTX; 322 323 /* The changes have been applied and all INSN_CODEs have been reset to force 324 rerecognition. 325 326 The changes are valid if we aren't given an object, or if we are 327 given a MEM and it still is a valid address, or if this is in insn 328 and it is recognized. In the latter case, if reload has completed, 329 we also require that the operands meet the constraints for 330 the insn. */ 331 332 for (i = 0; i < num_changes; i++) 333 { 334 rtx object = changes[i].object; 335 |
336 /* If there is no object to test or if it is the same as the one we |
337 already tested, ignore it. */ 338 if (object == 0 || object == last_validated) 339 continue; 340 341 if (GET_CODE (object) == MEM) 342 { 343 if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) 344 break; --- 66 unchanged lines hidden (view full) --- 411 cancel_changes (0); 412 return 0; 413 } 414} 415 416/* Return the number of changes so far in the current group. */ 417 418int |
419num_validated_changes (void) |
420{ 421 return num_changes; 422} 423 424/* Retract the changes numbered NUM and up. */ 425 426void |
427cancel_changes (int num) |
428{ 429 int i; 430 431 /* Back out all the changes. Do this in the opposite order in which 432 they were made. */ 433 for (i = num_changes - 1; i >= num; i--) 434 { 435 *changes[i].loc = changes[i].old; 436 if (changes[i].object && GET_CODE (changes[i].object) != MEM) 437 INSN_CODE (changes[i].object) = changes[i].old_code; 438 } 439 num_changes = num; 440} 441 442/* Replace every occurrence of FROM in X with TO. Mark each change with 443 validate_change passing OBJECT. */ 444 445static void |
446validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object) |
447{ 448 int i, j; 449 const char *fmt; 450 rtx x = *loc; 451 enum rtx_code code; 452 enum machine_mode op0_mode = VOIDmode; 453 int prev_changes = num_changes; 454 rtx new; --- 16 unchanged lines hidden (view full) --- 471 && REGNO (x) == REGNO (from)) 472 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) 473 && rtx_equal_p (x, from))) 474 { 475 validate_change (object, loc, to, 1); 476 return; 477 } 478 |
479 /* Call ourself recursively to perform the replacements. 480 We must not replace inside already replaced expression, otherwise we 481 get infinite recursion for replacements like (reg X)->(subreg (reg X)) 482 done by regmove, so we must special case shared ASM_OPERANDS. */ |
483 |
484 if (GET_CODE (x) == PARALLEL) |
485 { |
486 for (j = XVECLEN (x, 0) - 1; j >= 0; j--) 487 { 488 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET 489 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS) 490 { 491 /* Verify that operands are really shared. */ 492 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0))) != 493 ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, j)))) 494 abort (); 495 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)), 496 from, to, object); 497 } 498 else 499 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object); 500 } |
501 } |
502 else 503 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 504 { 505 if (fmt[i] == 'e') 506 validate_replace_rtx_1 (&XEXP (x, i), from, to, object); 507 else if (fmt[i] == 'E') 508 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 509 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); 510 } |
511 512 /* If we didn't substitute, there is nothing more to do. */ 513 if (num_changes == prev_changes) 514 return; 515 516 /* Allow substituted expression to have different mode. This is used by 517 regmove to change mode of pseudo register. */ 518 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) --- 122 unchanged lines hidden (view full) --- 641 } 642} 643 644/* Try replacing every occurrence of FROM in subexpression LOC of INSN 645 with TO. After all changes have been made, validate by seeing 646 if INSN is still valid. */ 647 648int |
649validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc) |
650{ 651 validate_replace_rtx_1 (loc, from, to, insn); 652 return apply_change_group (); 653} 654 655/* Try replacing every occurrence of FROM in INSN with TO. After all 656 changes have been made, validate by seeing if INSN is still valid. */ 657 658int |
659validate_replace_rtx (rtx from, rtx to, rtx insn) |
660{ 661 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); 662 return apply_change_group (); 663} 664 665/* Try replacing every occurrence of FROM in INSN with TO. */ 666 667void |
668validate_replace_rtx_group (rtx from, rtx to, rtx insn) |
669{ 670 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); 671} 672 673/* Function called by note_uses to replace used subexpressions. */ 674struct validate_replace_src_data 675{ 676 rtx from; /* Old RTX */ 677 rtx to; /* New RTX */ 678 rtx insn; /* Insn in which substitution is occurring. */ 679}; 680 681static void |
682validate_replace_src_1 (rtx *x, void *data) |
683{ 684 struct validate_replace_src_data *d 685 = (struct validate_replace_src_data *) data; 686 687 validate_replace_rtx_1 (x, d->from, d->to, d->insn); 688} 689 690/* Try replacing every occurrence of FROM in INSN with TO, avoiding 691 SET_DESTs. */ 692 693void |
694validate_replace_src_group (rtx from, rtx to, rtx insn) |
695{ 696 struct validate_replace_src_data d; 697 698 d.from = from; 699 d.to = to; 700 d.insn = insn; 701 note_uses (&PATTERN (insn), validate_replace_src_1, &d); 702} 703 |
704/* Same as validate_replace_src_group, but validate by seeing if |
705 INSN is still valid. */ 706int |
707validate_replace_src (rtx from, rtx to, rtx insn) |
708{ 709 validate_replace_src_group (from, to, insn); 710 return apply_change_group (); 711} 712 713#ifdef HAVE_cc0 714/* Return 1 if the insn using CC0 set by INSN does not contain 715 any ordered tests applied to the condition codes. 716 EQ and NE tests do not count. */ 717 718int |
719next_insn_tests_no_inequality (rtx insn) |
720{ 721 rtx next = next_cc0_user (insn); 722 723 /* If there is no next insn, we have to take the conservative choice. */ 724 if (next == 0) 725 return 0; 726 727 return ((GET_CODE (next) == JUMP_INSN 728 || GET_CODE (next) == INSN 729 || GET_CODE (next) == CALL_INSN) 730 && ! inequality_comparisons_p (PATTERN (next))); 731} |
732#endif |
733 734/* This is used by find_single_use to locate an rtx that contains exactly one 735 use of DEST, which is typically either a REG or CC0. It returns a 736 pointer to the innermost rtx expression containing DEST. Appearances of 737 DEST that are being used to totally replace it are not counted. */ 738 739static rtx * |
740find_single_use_1 (rtx dest, rtx *loc) |
741{ 742 rtx x = *loc; 743 enum rtx_code code = GET_CODE (x); 744 rtx *result = 0; 745 rtx *this_result; 746 int i; 747 const char *fmt; 748 --- 94 unchanged lines hidden (view full) --- 843 care about REG_DEAD notes or LOG_LINKS. 844 845 Otherwise, we find the single use by finding an insn that has a 846 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is 847 only referenced once in that insn, we know that it must be the first 848 and last insn referencing DEST. */ 849 850rtx * |
851find_single_use (rtx dest, rtx insn, rtx *ploc) |
852{ 853 rtx next; 854 rtx *result; 855 rtx link; 856 857#ifdef HAVE_cc0 858 if (dest == cc0_rtx) 859 { --- 46 unchanged lines hidden (view full) --- 906 907 The main use of this function is as a predicate in match_operand 908 expressions in the machine description. 909 910 For an explanation of this function's behavior for registers of 911 class NO_REGS, see the comment for `register_operand'. */ 912 913int |
914general_operand (rtx op, enum machine_mode mode) |
915{ 916 enum rtx_code code = GET_CODE (op); 917 918 if (mode == VOIDmode) 919 mode = GET_MODE (op); 920 921 /* Don't accept CONST_INT or anything similar 922 if the caller wants something floating. */ --- 38 unchanged lines hidden (view full) --- 961 might be called from cleanup_subreg_operands. 962 963 ??? This is a kludge. */ 964 if (!reload_completed && SUBREG_BYTE (op) != 0 965 && GET_CODE (sub) == MEM) 966 return 0; 967 968 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally |
969 create such rtl, and we must reject it. */ |
970 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT 971 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) 972 return 0; 973 974 op = sub; 975 code = GET_CODE (op); 976 } 977 --- 30 unchanged lines hidden (view full) --- 1008 1009/* Return 1 if OP is a valid memory address for a memory reference 1010 of mode MODE. 1011 1012 The main use of this function is as a predicate in match_operand 1013 expressions in the machine description. */ 1014 1015int |
1016address_operand (rtx op, enum machine_mode mode) |
1017{ 1018 return memory_address_p (mode, op); 1019} 1020 1021/* Return 1 if OP is a register reference of mode MODE. 1022 If MODE is VOIDmode, accept a register in any mode. 1023 1024 The main use of this function is as a predicate in match_operand 1025 expressions in the machine description. 1026 1027 As a special exception, registers whose class is NO_REGS are 1028 not accepted by `register_operand'. The reason for this change 1029 is to allow the representation of special architecture artifacts 1030 (such as a condition code register) without extending the rtl 1031 definitions. Since registers of class NO_REGS cannot be used 1032 as registers in any case where register classes are examined, 1033 it is most consistent to keep this function from accepting them. */ 1034 1035int |
1036register_operand (rtx op, enum machine_mode mode) |
1037{ 1038 if (GET_MODE (op) != mode && mode != VOIDmode) 1039 return 0; 1040 1041 if (GET_CODE (op) == SUBREG) 1042 { 1043 rtx sub = SUBREG_REG (op); 1044 --- 34 unchanged lines hidden (view full) --- 1079 return (GET_CODE (op) == REG 1080 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 1081 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 1082} 1083 1084/* Return 1 for a register in Pmode; ignore the tested mode. */ 1085 1086int |
1087pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1088{ 1089 return register_operand (op, Pmode); 1090} 1091 1092/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH 1093 or a hard register. */ 1094 1095int |
1096scratch_operand (rtx op, enum machine_mode mode) |
1097{ 1098 if (GET_MODE (op) != mode && mode != VOIDmode) 1099 return 0; 1100 1101 return (GET_CODE (op) == SCRATCH 1102 || (GET_CODE (op) == REG 1103 && REGNO (op) < FIRST_PSEUDO_REGISTER)); 1104} 1105 1106/* Return 1 if OP is a valid immediate operand for mode MODE. 1107 1108 The main use of this function is as a predicate in match_operand 1109 expressions in the machine description. */ 1110 1111int |
1112immediate_operand (rtx op, enum machine_mode mode) |
1113{ 1114 /* Don't accept CONST_INT or anything similar 1115 if the caller wants something floating. */ 1116 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1117 && GET_MODE_CLASS (mode) != MODE_INT 1118 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1119 return 0; 1120 --- 15 unchanged lines hidden (view full) --- 1136 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1137#endif 1138 && LEGITIMATE_CONSTANT_P (op)); 1139} 1140 1141/* Returns 1 if OP is an operand that is a CONST_INT. */ 1142 1143int |
1144const_int_operand (rtx op, enum machine_mode mode) |
1145{ 1146 if (GET_CODE (op) != CONST_INT) 1147 return 0; 1148 1149 if (mode != VOIDmode 1150 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1151 return 0; 1152 1153 return 1; 1154} 1155 1156/* Returns 1 if OP is an operand that is a constant integer or constant 1157 floating-point number. */ 1158 1159int |
1160const_double_operand (rtx op, enum machine_mode mode) |
1161{ 1162 /* Don't accept CONST_INT or anything similar 1163 if the caller wants something floating. */ 1164 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1165 && GET_MODE_CLASS (mode) != MODE_INT 1166 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1167 return 0; 1168 1169 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) 1170 && (mode == VOIDmode || GET_MODE (op) == mode 1171 || GET_MODE (op) == VOIDmode)); 1172} 1173 1174/* Return 1 if OP is a general operand that is not an immediate operand. */ 1175 1176int |
1177nonimmediate_operand (rtx op, enum machine_mode mode) |
1178{ 1179 return (general_operand (op, mode) && ! CONSTANT_P (op)); 1180} 1181 1182/* Return 1 if OP is a register reference or immediate value of mode MODE. */ 1183 1184int |
1185nonmemory_operand (rtx op, enum machine_mode mode) |
1186{ 1187 if (CONSTANT_P (op)) 1188 { 1189 /* Don't accept CONST_INT or anything similar 1190 if the caller wants something floating. */ 1191 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1192 && GET_MODE_CLASS (mode) != MODE_INT 1193 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) --- 37 unchanged lines hidden (view full) --- 1231 1232/* Return 1 if OP is a valid operand that stands for pushing a 1233 value of mode MODE onto the stack. 1234 1235 The main use of this function is as a predicate in match_operand 1236 expressions in the machine description. */ 1237 1238int |
1239push_operand (rtx op, enum machine_mode mode) |
1240{ 1241 unsigned int rounded_size = GET_MODE_SIZE (mode); 1242 1243#ifdef PUSH_ROUNDING 1244 rounded_size = PUSH_ROUNDING (rounded_size); 1245#endif 1246 1247 if (GET_CODE (op) != MEM) --- 13 unchanged lines hidden (view full) --- 1261 { 1262 if (GET_CODE (op) != PRE_MODIFY 1263 || GET_CODE (XEXP (op, 1)) != PLUS 1264 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) 1265 || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT 1266#ifdef STACK_GROWS_DOWNWARD 1267 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size 1268#else |
1269 || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size |
1270#endif 1271 ) 1272 return 0; 1273 } 1274 1275 return XEXP (op, 0) == stack_pointer_rtx; 1276} 1277 1278/* Return 1 if OP is a valid operand that stands for popping a 1279 value of mode MODE off the stack. 1280 1281 The main use of this function is as a predicate in match_operand 1282 expressions in the machine description. */ 1283 1284int |
1285pop_operand (rtx op, enum machine_mode mode) |
1286{ 1287 if (GET_CODE (op) != MEM) 1288 return 0; 1289 1290 if (mode != VOIDmode && GET_MODE (op) != mode) 1291 return 0; 1292 1293 op = XEXP (op, 0); 1294 1295 if (GET_CODE (op) != STACK_POP_CODE) 1296 return 0; 1297 1298 return XEXP (op, 0) == stack_pointer_rtx; 1299} 1300 1301/* Return 1 if ADDR is a valid memory address for mode MODE. */ 1302 1303int |
1304memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx addr) |
1305{ 1306 if (GET_CODE (addr) == ADDRESSOF) 1307 return 1; 1308 1309 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 1310 return 0; 1311 1312 win: 1313 return 1; 1314} 1315 1316/* Return 1 if OP is a valid memory reference with mode MODE, 1317 including a valid address. 1318 1319 The main use of this function is as a predicate in match_operand 1320 expressions in the machine description. */ 1321 1322int |
1323memory_operand (rtx op, enum machine_mode mode) |
1324{ 1325 rtx inner; 1326 1327 if (! reload_completed) 1328 /* Note that no SUBREG is a memory operand before end of reload pass, 1329 because (SUBREG (MEM...)) forces reloading into a register. */ 1330 return GET_CODE (op) == MEM && general_operand (op, mode); 1331 --- 6 unchanged lines hidden (view full) --- 1338 1339 return (GET_CODE (inner) == MEM && general_operand (op, mode)); 1340} 1341 1342/* Return 1 if OP is a valid indirect memory reference with mode MODE; 1343 that is, a memory reference whose address is a general_operand. */ 1344 1345int |
1346indirect_operand (rtx op, enum machine_mode mode) |
1347{ 1348 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ 1349 if (! reload_completed 1350 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) 1351 { 1352 int offset = SUBREG_BYTE (op); 1353 rtx inner = SUBREG_REG (op); 1354 --- 16 unchanged lines hidden (view full) --- 1371 && memory_operand (op, mode) 1372 && general_operand (XEXP (op, 0), Pmode)); 1373} 1374 1375/* Return 1 if this is a comparison operator. This allows the use of 1376 MATCH_OPERATOR to recognize all the branch insns. */ 1377 1378int |
1379comparison_operator (rtx op, enum machine_mode mode) |
1380{ 1381 return ((mode == VOIDmode || GET_MODE (op) == mode) 1382 && GET_RTX_CLASS (GET_CODE (op)) == '<'); 1383} 1384 1385/* If BODY is an insn body that uses ASM_OPERANDS, 1386 return the number of operands (both input and output) in the insn. 1387 Otherwise return -1. */ 1388 1389int |
1390asm_noperands (rtx body) |
1391{ 1392 switch (GET_CODE (body)) 1393 { 1394 case ASM_OPERANDS: 1395 /* No output operands: return number of input operands. */ 1396 return ASM_OPERANDS_INPUT_LENGTH (body); 1397 case SET: 1398 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) --- 67 unchanged lines hidden (view full) --- 1466 and the constraints for the operands into CONSTRAINTS. 1467 Write the modes of the operands into MODES. 1468 Return the assembler-template. 1469 1470 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, 1471 we don't store that info. */ 1472 1473const char * |
1474decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs, 1475 const char **constraints, enum machine_mode *modes) |
1476{ 1477 int i; 1478 int noperands; 1479 const char *template = 0; 1480 1481 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) 1482 { 1483 rtx asmop = SET_SRC (body); --- 115 unchanged lines hidden (view full) --- 1599 1600 return template; 1601} 1602 1603/* Check if an asm_operand matches it's constraints. 1604 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ 1605 1606int |
1607asm_operand_ok (rtx op, const char *constraint) |
1608{ 1609 int result = 0; 1610 1611 /* Use constrain_operands after reload. */ 1612 if (reload_completed) 1613 abort (); 1614 1615 while (*constraint) 1616 { |
1617 char c = *constraint; 1618 int len; |
1619 switch (c) 1620 { |
1621 case ',': 1622 constraint++; 1623 continue; |
1624 case '=': 1625 case '+': 1626 case '*': 1627 case '%': |
1628 case '!': 1629 case '#': 1630 case '&': |
1631 case '?': |
1632 break; 1633 1634 case '0': case '1': case '2': case '3': case '4': 1635 case '5': case '6': case '7': case '8': case '9': 1636 /* For best results, our caller should have given us the 1637 proper matching constraint, but we can't actually fail 1638 the check if they didn't. Indicate that results are 1639 inconclusive. */ |
1640 do |
1641 constraint++; |
1642 while (ISDIGIT (*constraint)); 1643 if (! result) 1644 result = -1; 1645 continue; |
1646 1647 case 'p': 1648 if (address_operand (op, VOIDmode)) |
1649 result = 1; |
1650 break; 1651 1652 case 'm': 1653 case 'V': /* non-offsettable */ 1654 if (memory_operand (op, VOIDmode)) |
1655 result = 1; |
1656 break; 1657 1658 case 'o': /* offsettable */ 1659 if (offsettable_nonstrict_memref_p (op)) |
1660 result = 1; |
1661 break; 1662 1663 case '<': 1664 /* ??? Before flow, auto inc/dec insns are not supposed to exist, 1665 excepting those that expand_call created. Further, on some 1666 machines which do not have generalized auto inc/dec, an inc/dec 1667 is not a memory_operand. 1668 1669 Match any memory and hope things are resolved after reload. */ 1670 1671 if (GET_CODE (op) == MEM 1672 && (1 1673 || GET_CODE (XEXP (op, 0)) == PRE_DEC 1674 || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
1675 result = 1; |
1676 break; 1677 1678 case '>': 1679 if (GET_CODE (op) == MEM 1680 && (1 1681 || GET_CODE (XEXP (op, 0)) == PRE_INC 1682 || GET_CODE (XEXP (op, 0)) == POST_INC)) |
1683 result = 1; |
1684 break; 1685 1686 case 'E': 1687 case 'F': 1688 if (GET_CODE (op) == CONST_DOUBLE 1689 || (GET_CODE (op) == CONST_VECTOR 1690 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)) |
1691 result = 1; |
1692 break; 1693 1694 case 'G': 1695 if (GET_CODE (op) == CONST_DOUBLE |
1696 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint)) 1697 result = 1; |
1698 break; 1699 case 'H': 1700 if (GET_CODE (op) == CONST_DOUBLE |
1701 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint)) 1702 result = 1; |
1703 break; 1704 1705 case 's': 1706 if (GET_CODE (op) == CONST_INT 1707 || (GET_CODE (op) == CONST_DOUBLE 1708 && GET_MODE (op) == VOIDmode)) 1709 break; |
1710 /* Fall through. */ |
1711 1712 case 'i': 1713 if (CONSTANT_P (op) 1714#ifdef LEGITIMATE_PIC_OPERAND_P 1715 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1716#endif 1717 ) |
1718 result = 1; |
1719 break; 1720 1721 case 'n': 1722 if (GET_CODE (op) == CONST_INT 1723 || (GET_CODE (op) == CONST_DOUBLE 1724 && GET_MODE (op) == VOIDmode)) |
1725 result = 1; |
1726 break; 1727 1728 case 'I': 1729 if (GET_CODE (op) == CONST_INT |
1730 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint)) 1731 result = 1; |
1732 break; 1733 case 'J': 1734 if (GET_CODE (op) == CONST_INT |
1735 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint)) 1736 result = 1; |
1737 break; 1738 case 'K': 1739 if (GET_CODE (op) == CONST_INT |
1740 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint)) 1741 result = 1; |
1742 break; 1743 case 'L': 1744 if (GET_CODE (op) == CONST_INT |
1745 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint)) 1746 result = 1; |
1747 break; 1748 case 'M': 1749 if (GET_CODE (op) == CONST_INT |
1750 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint)) 1751 result = 1; |
1752 break; 1753 case 'N': 1754 if (GET_CODE (op) == CONST_INT |
1755 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint)) 1756 result = 1; |
1757 break; 1758 case 'O': 1759 if (GET_CODE (op) == CONST_INT |
1760 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint)) 1761 result = 1; |
1762 break; 1763 case 'P': 1764 if (GET_CODE (op) == CONST_INT |
1765 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint)) 1766 result = 1; |
1767 break; 1768 1769 case 'X': |
1770 result = 1; 1771 break; |
1772 1773 case 'g': 1774 if (general_operand (op, VOIDmode)) |
1775 result = 1; |
1776 break; 1777 1778 default: 1779 /* For all other letters, we first check for a register class, 1780 otherwise it is an EXTRA_CONSTRAINT. */ |
1781 if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS) |
1782 { 1783 case 'r': 1784 if (GET_MODE (op) == BLKmode) 1785 break; 1786 if (register_operand (op, VOIDmode)) |
1787 result = 1; |
1788 } |
1789#ifdef EXTRA_CONSTRAINT_STR 1790 else if (EXTRA_CONSTRAINT_STR (op, c, constraint)) 1791 result = 1; 1792 else if (EXTRA_MEMORY_CONSTRAINT (c, constraint) 1793 /* Every memory operand can be reloaded to fit. */ 1794 && memory_operand (op, VOIDmode)) 1795 result = 1; 1796 else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint) 1797 /* Every address operand can be reloaded to fit. */ 1798 && address_operand (op, VOIDmode)) 1799 result = 1; |
1800#endif 1801 break; 1802 } |
1803 len = CONSTRAINT_LEN (c, constraint); 1804 do 1805 constraint++; 1806 while (--len && *constraint); 1807 if (len) 1808 return 0; |
1809 } 1810 1811 return result; 1812} 1813 1814/* Given an rtx *P, if it is a sum containing an integer constant term, 1815 return the location (type rtx *) of the pointer to that constant term. 1816 Otherwise, return a null pointer. */ 1817 1818rtx * |
1819find_constant_term_loc (rtx *p) |
1820{ 1821 rtx *tem; 1822 enum rtx_code code = GET_CODE (*p); 1823 1824 /* If *P IS such a constant term, P is its location. */ 1825 1826 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF 1827 || code == CONST) --- 36 unchanged lines hidden (view full) --- 1864 size of the object being referenced. 1865 1866 We assume that the original address is valid and do not check it. 1867 1868 This uses strict_memory_address_p as a subroutine, so 1869 don't use it before reload. */ 1870 1871int |
1872offsettable_memref_p (rtx op) |
1873{ 1874 return ((GET_CODE (op) == MEM) 1875 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); 1876} 1877 1878/* Similar, but don't require a strictly valid mem ref: 1879 consider pseudo-regs valid as index or base regs. */ 1880 1881int |
1882offsettable_nonstrict_memref_p (rtx op) |
1883{ 1884 return ((GET_CODE (op) == MEM) 1885 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); 1886} 1887 1888/* Return 1 if Y is a memory address which contains no side effects 1889 and would remain valid after the addition of a positive integer 1890 less than the size of that mode. 1891 1892 We assume that the original address is valid and do not check it. 1893 We do check that it is valid for narrower modes. 1894 1895 If STRICTP is nonzero, we require a strictly valid address, 1896 for the sake of use in reload.c. */ 1897 1898int |
1899offsettable_address_p (int strictp, enum machine_mode mode, rtx y) |
1900{ 1901 enum rtx_code ycode = GET_CODE (y); 1902 rtx z; 1903 rtx y1 = y; 1904 rtx *y2; |
1905 int (*addressp) (enum machine_mode, rtx) = |
1906 (strictp ? strict_memory_address_p : memory_address_p); 1907 unsigned int mode_sz = GET_MODE_SIZE (mode); 1908 1909 if (CONSTANT_ADDRESS_P (y)) 1910 return 1; 1911 1912 /* Adjusting an offsettable address involves changing to a narrower mode. 1913 Make sure that's OK. */ --- 49 unchanged lines hidden (view full) --- 1963 1964/* Return 1 if ADDR is an address-expression whose effect depends 1965 on the mode of the memory reference it is used in. 1966 1967 Autoincrement addressing is a typical example of mode-dependence 1968 because the amount of the increment depends on the mode. */ 1969 1970int |
1971mode_dependent_address_p (rtx addr ATTRIBUTE_UNUSED /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */) |
1972{ 1973 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); 1974 return 0; 1975 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ 1976 win: ATTRIBUTE_UNUSED_LABEL 1977 return 1; 1978} |
1979 1980/* Like extract_insn, but save insn extracted and don't extract again, when 1981 called again for the same insn expecting that recog_data still contain the 1982 valid information. This is used primary by gen_attr infrastructure that 1983 often does extract insn again and again. */ 1984void |
1985extract_insn_cached (rtx insn) |
1986{ 1987 if (recog_data.insn == insn && INSN_CODE (insn) >= 0) 1988 return; 1989 extract_insn (insn); 1990 recog_data.insn = insn; 1991} |
1992/* Do cached extract_insn, constrain_operands and complain about failures. |
1993 Used by insn_attrtab. */ 1994void |
1995extract_constrain_insn_cached (rtx insn) |
1996{ 1997 extract_insn_cached (insn); 1998 if (which_alternative == -1 1999 && !constrain_operands (reload_completed)) 2000 fatal_insn_not_found (insn); 2001} |
2002/* Do cached constrain_operands and complain about failures. */ |
2003int |
2004constrain_operands_cached (int strict) |
2005{ 2006 if (which_alternative == -1) 2007 return constrain_operands (strict); 2008 else 2009 return 1; 2010} 2011 2012/* Analyze INSN and fill in recog_data. */ 2013 2014void |
2015extract_insn (rtx insn) |
2016{ 2017 int i; 2018 int icode; 2019 int noperands; 2020 rtx body = PATTERN (insn); 2021 2022 recog_data.insn = NULL; 2023 recog_data.n_operands = 0; --- 82 unchanged lines hidden (view full) --- 2106 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) 2107 abort (); 2108} 2109 2110/* After calling extract_insn, you can use this function to extract some 2111 information from the constraint strings into a more usable form. 2112 The collected data is stored in recog_op_alt. */ 2113void |
2114preprocess_constraints (void) |
2115{ 2116 int i; 2117 |
2118 for (i = 0; i < recog_data.n_operands; i++) |
2119 memset (recog_op_alt[i], 0, (recog_data.n_alternatives 2120 * sizeof (struct operand_alternative))); 2121 2122 for (i = 0; i < recog_data.n_operands; i++) |
2123 { 2124 int j; 2125 struct operand_alternative *op_alt; 2126 const char *p = recog_data.constraints[i]; 2127 2128 op_alt = recog_op_alt[i]; 2129 2130 for (j = 0; j < recog_data.n_alternatives; j++) --- 6 unchanged lines hidden (view full) --- 2137 if (*p == '\0' || *p == ',') 2138 { 2139 op_alt[j].anything_ok = 1; 2140 continue; 2141 } 2142 2143 for (;;) 2144 { |
2145 char c = *p; |
2146 if (c == '#') 2147 do |
2148 c = *++p; |
2149 while (c != ',' && c != '\0'); 2150 if (c == ',' || c == '\0') |
2151 { 2152 p++; 2153 break; 2154 } |
2155 2156 switch (c) 2157 { 2158 case '=': case '+': case '*': case '%': 2159 case 'E': case 'F': case 'G': case 'H': 2160 case 's': case 'i': case 'n': 2161 case 'I': case 'J': case 'K': case 'L': 2162 case 'M': case 'N': case 'O': case 'P': --- 9 unchanged lines hidden (view full) --- 2172 case '&': 2173 op_alt[j].earlyclobber = 1; 2174 break; 2175 2176 case '0': case '1': case '2': case '3': case '4': 2177 case '5': case '6': case '7': case '8': case '9': 2178 { 2179 char *end; |
2180 op_alt[j].matches = strtoul (p, &end, 10); |
2181 recog_op_alt[op_alt[j].matches][j].matched = i; 2182 p = end; 2183 } |
2184 continue; |
2185 2186 case 'm': 2187 op_alt[j].memory_ok = 1; 2188 break; 2189 case '<': 2190 op_alt[j].decmem_ok = 1; 2191 break; 2192 case '>': --- 15 unchanged lines hidden (view full) --- 2208 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 2209 break; 2210 2211 case 'g': case 'r': 2212 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; 2213 break; 2214 2215 default: |
2216 if (EXTRA_MEMORY_CONSTRAINT (c, p)) |
2217 { 2218 op_alt[j].memory_ok = 1; 2219 break; 2220 } |
2221 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
2222 { 2223 op_alt[j].is_address = 1; |
2224 op_alt[j].class 2225 = (reg_class_subunion 2226 [(int) op_alt[j].class] 2227 [(int) MODE_BASE_REG_CLASS (VOIDmode)]); |
2228 break; 2229 } 2230 |
2231 op_alt[j].class 2232 = (reg_class_subunion 2233 [(int) op_alt[j].class] 2234 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); |
2235 break; 2236 } |
2237 p += CONSTRAINT_LEN (c, p); |
2238 } 2239 } 2240 } 2241} 2242 2243/* Check the operands of an insn against the insn's operand constraints 2244 and return 1 if they are valid. 2245 The information about the insn's operands, constraints, operand modes 2246 etc. is obtained from the global variables set up by extract_insn. 2247 2248 WHICH_ALTERNATIVE is set to a number which indicates which 2249 alternative of constraints was matched: 0 for the first alternative, 2250 1 for the next, etc. 2251 |
2252 In addition, when two operands are required to match |
2253 and it happens that the output operand is (reg) while the 2254 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), 2255 make the output operand look like the input. 2256 This is because the output operand is the one the template will print. 2257 2258 This is used in final, just before printing the assembler code and by 2259 the routines that determine an insn's attribute. 2260 --- 7 unchanged lines hidden (view full) --- 2268 to reload. A negative value of STRICT is used for this internal call. */ 2269 2270struct funny_match 2271{ 2272 int this, other; 2273}; 2274 2275int |
2276constrain_operands (int strict) |
2277{ 2278 const char *constraints[MAX_RECOG_OPERANDS]; 2279 int matching_operands[MAX_RECOG_OPERANDS]; 2280 int earlyclobber[MAX_RECOG_OPERANDS]; 2281 int c; 2282 2283 struct funny_match funny_match[MAX_RECOG_OPERANDS]; 2284 int funny_match_index; --- 17 unchanged lines hidden (view full) --- 2302 for (opno = 0; opno < recog_data.n_operands; opno++) 2303 { 2304 rtx op = recog_data.operand[opno]; 2305 enum machine_mode mode = GET_MODE (op); 2306 const char *p = constraints[opno]; 2307 int offset = 0; 2308 int win = 0; 2309 int val; |
2310 int len; |
2311 2312 earlyclobber[opno] = 0; 2313 2314 /* A unary operator may be accepted by the predicate, but it 2315 is irrelevant for matching constraints. */ 2316 if (GET_RTX_CLASS (GET_CODE (op)) == '1') 2317 op = XEXP (op, 0); 2318 --- 8 unchanged lines hidden (view full) --- 2327 op = SUBREG_REG (op); 2328 } 2329 2330 /* An empty constraint or empty alternative 2331 allows anything which matched the pattern. */ 2332 if (*p == 0 || *p == ',') 2333 win = 1; 2334 |
2335 do 2336 switch (c = *p, len = CONSTRAINT_LEN (c, p), c) |
2337 { |
2338 case '\0': 2339 len = 0; 2340 break; 2341 case ',': 2342 c = '\0'; 2343 break; 2344 |
2345 case '?': case '!': case '*': case '%': 2346 case '=': case '+': 2347 break; 2348 2349 case '#': 2350 /* Ignore rest of this alternative as far as 2351 constraint checking is concerned. */ |
2352 do |
2353 p++; |
2354 while (*p && *p != ','); 2355 len = 0; |
2356 break; 2357 2358 case '&': 2359 earlyclobber[opno] = 1; 2360 break; 2361 2362 case '0': case '1': case '2': case '3': case '4': 2363 case '5': case '6': case '7': case '8': case '9': --- 5 unchanged lines hidden (view full) --- 2369 Note that the lower-numbered operand is passed first. 2370 2371 If we are not testing strictly, assume that this 2372 constraint will be satisfied. */ 2373 2374 char *end; 2375 int match; 2376 |
2377 match = strtoul (p, &end, 10); |
2378 p = end; 2379 2380 if (strict < 0) 2381 val = 1; 2382 else 2383 { 2384 rtx op1 = recog_data.operand[match]; 2385 rtx op2 = recog_data.operand[opno]; --- 18 unchanged lines hidden (view full) --- 2404 to change the output to *--x as well, since the 2405 output op is the one that will be printed. */ 2406 if (val == 2 && strict > 0) 2407 { 2408 funny_match[funny_match_index].this = opno; 2409 funny_match[funny_match_index++].other = match; 2410 } 2411 } |
2412 len = 0; |
2413 break; 2414 2415 case 'p': 2416 /* p is used for address_operands. When we are called by 2417 gen_reload, no one will have checked that the address is 2418 strictly valid, i.e., that all pseudos requiring hard regs 2419 have gotten them. */ 2420 if (strict <= 0 --- 19 unchanged lines hidden (view full) --- 2440 case 'X': 2441 /* This is used for a MATCH_SCRATCH in the cases when 2442 we don't actually need anything. So anything goes 2443 any time. */ 2444 win = 1; 2445 break; 2446 2447 case 'm': |
2448 /* Memory operands must be valid, to the extent 2449 required by STRICT. */ 2450 if (GET_CODE (op) == MEM) 2451 { 2452 if (strict > 0 2453 && !strict_memory_address_p (GET_MODE (op), 2454 XEXP (op, 0))) 2455 break; 2456 if (strict == 0 2457 && !memory_address_p (GET_MODE (op), XEXP (op, 0))) 2458 break; 2459 win = 1; 2460 } 2461 /* Before reload, accept what reload can turn into mem. */ 2462 else if (strict < 0 && CONSTANT_P (op)) |
2463 win = 1; |
2464 /* During reload, accept a pseudo */ 2465 else if (reload_in_progress && GET_CODE (op) == REG 2466 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2467 win = 1; |
2468 break; 2469 2470 case '<': 2471 if (GET_CODE (op) == MEM 2472 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 2473 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 2474 win = 1; 2475 break; --- 11 unchanged lines hidden (view full) --- 2487 || (GET_CODE (op) == CONST_VECTOR 2488 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)) 2489 win = 1; 2490 break; 2491 2492 case 'G': 2493 case 'H': 2494 if (GET_CODE (op) == CONST_DOUBLE |
2495 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) |
2496 win = 1; 2497 break; 2498 2499 case 's': 2500 if (GET_CODE (op) == CONST_INT 2501 || (GET_CODE (op) == CONST_DOUBLE 2502 && GET_MODE (op) == VOIDmode)) 2503 break; --- 13 unchanged lines hidden (view full) --- 2517 case 'J': 2518 case 'K': 2519 case 'L': 2520 case 'M': 2521 case 'N': 2522 case 'O': 2523 case 'P': 2524 if (GET_CODE (op) == CONST_INT |
2525 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) |
2526 win = 1; 2527 break; 2528 2529 case 'V': 2530 if (GET_CODE (op) == MEM 2531 && ((strict > 0 && ! offsettable_memref_p (op)) 2532 || (strict < 0 2533 && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) --- 14 unchanged lines hidden (view full) --- 2548 && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2549 win = 1; 2550 break; 2551 2552 default: 2553 { 2554 enum reg_class class; 2555 |
2556 class = (c == 'r' 2557 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p)); |
2558 if (class != NO_REGS) 2559 { 2560 if (strict < 0 2561 || (strict == 0 2562 && GET_CODE (op) == REG 2563 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2564 || (strict == 0 && GET_CODE (op) == SCRATCH) 2565 || (GET_CODE (op) == REG 2566 && reg_fits_class_p (op, class, offset, mode))) 2567 win = 1; 2568 } |
2569#ifdef EXTRA_CONSTRAINT_STR 2570 else if (EXTRA_CONSTRAINT_STR (op, c, p)) |
2571 win = 1; 2572 |
2573 else if (EXTRA_MEMORY_CONSTRAINT (c, p) 2574 /* Every memory operand can be reloaded to fit. */ 2575 && ((strict < 0 && GET_CODE (op) == MEM) 2576 /* Before reload, accept what reload can turn 2577 into mem. */ 2578 || (strict < 0 && CONSTANT_P (op)) 2579 /* During reload, accept a pseudo */ 2580 || (reload_in_progress && GET_CODE (op) == REG 2581 && REGNO (op) >= FIRST_PSEUDO_REGISTER))) 2582 win = 1; 2583 else if (EXTRA_ADDRESS_CONSTRAINT (c, p) 2584 /* Every address operand can be reloaded to fit. */ 2585 && strict < 0) 2586 win = 1; |
2587#endif 2588 break; 2589 } 2590 } |
2591 while (p += len, c); |
2592 2593 constraints[opno] = p; 2594 /* If this operand did not win somehow, 2595 this alternative loses. */ 2596 if (! win) 2597 lose = 1; 2598 } 2599 /* This alternative won; the operands are ok. --- 51 unchanged lines hidden (view full) --- 2651} 2652 2653/* Return 1 iff OPERAND (assumed to be a REG rtx) 2654 is a hard reg in class CLASS when its regno is offset by OFFSET 2655 and changed to mode MODE. 2656 If REG occupies multiple hard regs, all of them must be in CLASS. */ 2657 2658int |
2659reg_fits_class_p (rtx operand, enum reg_class class, int offset, 2660 enum machine_mode mode) |
2661{ 2662 int regno = REGNO (operand); 2663 if (regno < FIRST_PSEUDO_REGISTER 2664 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], 2665 regno + offset)) 2666 { 2667 int sr; 2668 regno += offset; 2669 for (sr = HARD_REGNO_NREGS (regno, mode) - 1; 2670 sr > 0; sr--) 2671 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], 2672 regno + sr)) 2673 break; 2674 return sr == 0; 2675 } 2676 2677 return 0; 2678} 2679 |
2680/* Split single instruction. Helper function for split_all_insns and 2681 split_all_insns_noflow. Return last insn in the sequence if successful, 2682 or NULL if unsuccessful. */ 2683 |
2684static rtx |
2685split_insn (rtx insn) |
2686{ |
2687 /* Split insns here to get max fine-grain parallelism. */ 2688 rtx first = PREV_INSN (insn); 2689 rtx last = try_split (PATTERN (insn), insn, 1); |
2690 |
2691 if (last == insn) 2692 return NULL_RTX; |
2693 |
2694 /* try_split returns the NOTE that INSN became. */ 2695 PUT_CODE (insn, NOTE); 2696 NOTE_SOURCE_FILE (insn) = 0; 2697 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; |
2698 |
2699 /* ??? Coddle to md files that generate subregs in post-reload 2700 splitters instead of computing the proper hard register. */ 2701 if (reload_completed && first != last) 2702 { 2703 first = NEXT_INSN (first); 2704 for (;;) 2705 { 2706 if (INSN_P (first)) 2707 cleanup_subreg_operands (first); 2708 if (first == last) 2709 break; 2710 first = NEXT_INSN (first); |
2711 } 2712 } |
2713 return last; |
2714} |
2715 |
2716/* Split all insns in the function. If UPD_LIFE, update life info after. */ 2717 2718void |
2719split_all_insns (int upd_life) |
2720{ 2721 sbitmap blocks; 2722 bool changed; 2723 basic_block bb; 2724 2725 blocks = sbitmap_alloc (last_basic_block); 2726 sbitmap_zero (blocks); 2727 changed = false; 2728 2729 FOR_EACH_BB_REVERSE (bb) 2730 { 2731 rtx insn, next; 2732 bool finish = false; 2733 |
2734 for (insn = BB_HEAD (bb); !finish ; insn = next) |
2735 { |
2736 /* Can't use `next_real_insn' because that might go across 2737 CODE_LABELS and short-out basic blocks. */ 2738 next = NEXT_INSN (insn); |
2739 finish = (insn == BB_END (bb)); 2740 if (INSN_P (insn)) |
2741 { |
2742 rtx set = single_set (insn); |
2743 |
2744 /* Don't split no-op move insns. These should silently 2745 disappear later in final. Splitting such insns would 2746 break the code that handles REG_NO_CONFLICT blocks. */ 2747 if (set && set_noop_p (set)) 2748 { 2749 /* Nops get in the way while scheduling, so delete them 2750 now if register allocation has already been done. It 2751 is too risky to try to do this before register 2752 allocation, and there are unlikely to be very many 2753 nops then anyways. */ 2754 if (reload_completed) 2755 { 2756 /* If the no-op set has a REG_UNUSED note, we need 2757 to update liveness information. */ 2758 if (find_reg_note (insn, REG_UNUSED, NULL_RTX)) 2759 { 2760 SET_BIT (blocks, bb->index); 2761 changed = true; 2762 } 2763 /* ??? Is life info affected by deleting edges? */ 2764 delete_insn_and_edges (insn); 2765 } 2766 } 2767 else 2768 { 2769 rtx last = split_insn (insn); 2770 if (last) 2771 { 2772 /* The split sequence may include barrier, but the 2773 BB boundary we are interested in will be set to 2774 previous one. */ 2775 2776 while (GET_CODE (last) == BARRIER) 2777 last = PREV_INSN (last); 2778 SET_BIT (blocks, bb->index); 2779 changed = true; 2780 } 2781 } |
2782 } 2783 } 2784 } 2785 2786 if (changed) 2787 { 2788 int old_last_basic_block = last_basic_block; 2789 --- 10 unchanged lines hidden (view full) --- 2800#ifdef ENABLE_CHECKING 2801 verify_flow_info (); 2802#endif 2803 2804 sbitmap_free (blocks); 2805} 2806 2807/* Same as split_all_insns, but do not expect CFG to be available. |
2808 Used by machine dependent reorg passes. */ |
2809 2810void |
2811split_all_insns_noflow (void) |
2812{ 2813 rtx next, insn; 2814 2815 for (insn = get_insns (); insn; insn = next) 2816 { 2817 next = NEXT_INSN (insn); |
2818 if (INSN_P (insn)) 2819 { 2820 /* Don't split no-op move insns. These should silently 2821 disappear later in final. Splitting such insns would 2822 break the code that handles REG_NO_CONFLICT blocks. */ 2823 rtx set = single_set (insn); 2824 if (set && set_noop_p (set)) 2825 { 2826 /* Nops get in the way while scheduling, so delete them 2827 now if register allocation has already been done. It 2828 is too risky to try to do this before register 2829 allocation, and there are unlikely to be very many 2830 nops then anyways. 2831 2832 ??? Should we use delete_insn when the CFG isn't valid? */ 2833 if (reload_completed) 2834 delete_insn_and_edges (insn); 2835 } 2836 else 2837 split_insn (insn); 2838 } |
2839 } |
2840} 2841 2842#ifdef HAVE_peephole2 2843struct peep2_insn_data 2844{ 2845 rtx insn; 2846 regset live_before; 2847}; --- 6 unchanged lines hidden (view full) --- 2854 global_live_at_end for the block. */ 2855#define PEEP2_EOB pc_rtx 2856 2857/* Return the Nth non-note insn after `current', or return NULL_RTX if it 2858 does not exist. Used by the recognizer to find the next insn to match 2859 in a multi-insn pattern. */ 2860 2861rtx |
2862peep2_next_insn (int n) |
2863{ 2864 if (n >= MAX_INSNS_PER_PEEP2 + 1) 2865 abort (); 2866 2867 n += peep2_current; 2868 if (n >= MAX_INSNS_PER_PEEP2 + 1) 2869 n -= MAX_INSNS_PER_PEEP2 + 1; 2870 2871 if (peep2_insn_data[n].insn == PEEP2_EOB) 2872 return NULL_RTX; 2873 return peep2_insn_data[n].insn; 2874} 2875 2876/* Return true if REGNO is dead before the Nth non-note insn 2877 after `current'. */ 2878 2879int |
2880peep2_regno_dead_p (int ofs, int regno) |
2881{ 2882 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2883 abort (); 2884 2885 ofs += peep2_current; 2886 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2887 ofs -= MAX_INSNS_PER_PEEP2 + 1; 2888 2889 if (peep2_insn_data[ofs].insn == NULL_RTX) 2890 abort (); 2891 2892 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno); 2893} 2894 2895/* Similarly for a REG. */ 2896 2897int |
2898peep2_reg_dead_p (int ofs, rtx reg) |
2899{ 2900 int regno, n; 2901 2902 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2903 abort (); 2904 2905 ofs += peep2_current; 2906 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) --- 17 unchanged lines hidden (view full) --- 2924 before CURRENT_INSN. 2925 Registers that already have bits set in REG_SET will not be considered. 2926 2927 If an appropriate register is available, it will be returned and the 2928 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is 2929 returned. */ 2930 2931rtx |
2932peep2_find_free_register (int from, int to, const char *class_str, 2933 enum machine_mode mode, HARD_REG_SET *reg_set) |
2934{ 2935 static int search_ofs; 2936 enum reg_class class; 2937 HARD_REG_SET live; 2938 int i; 2939 2940 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1) 2941 abort (); --- 17 unchanged lines hidden (view full) --- 2959 from = 0; 2960 if (peep2_insn_data[from].insn == NULL_RTX) 2961 abort (); 2962 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); 2963 IOR_HARD_REG_SET (live, this_live); 2964 } 2965 2966 class = (class_str[0] == 'r' ? GENERAL_REGS |
2967 : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str)); |
2968 2969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2970 { 2971 int raw_regno, regno, success, j; 2972 2973 /* Distribute the free registers as much as possible. */ 2974 raw_regno = search_ofs + i; 2975 if (raw_regno >= FIRST_PSEUDO_REGISTER) --- 47 unchanged lines hidden (view full) --- 3023 3024 search_ofs = 0; 3025 return NULL_RTX; 3026} 3027 3028/* Perform the peephole2 optimization pass. */ 3029 3030void |
3031peephole2_optimize (FILE *dump_file ATTRIBUTE_UNUSED) |
3032{ 3033 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2]; 3034 rtx insn, prev; 3035 regset live; 3036 int i; 3037 basic_block bb; 3038#ifdef HAVE_conditional_execution 3039 sbitmap blocks; --- 32 unchanged lines hidden (view full) --- 3072 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); 3073 3074#ifdef HAVE_conditional_execution 3075 pbi = init_propagate_block_info (bb, live, NULL, NULL, 0); 3076#else 3077 pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES); 3078#endif 3079 |
3080 for (insn = BB_END (bb); ; insn = prev) |
3081 { 3082 prev = PREV_INSN (insn); 3083 if (INSN_P (insn)) 3084 { 3085 rtx try, before_try, x; 3086 int match_len; 3087 rtx note; 3088 bool was_call = false; --- 72 unchanged lines hidden (view full) --- 3161 i = match_len + peep2_current; 3162 if (i >= MAX_INSNS_PER_PEEP2 + 1) 3163 i -= MAX_INSNS_PER_PEEP2 + 1; 3164 3165 note = find_reg_note (peep2_insn_data[i].insn, 3166 REG_EH_REGION, NULL_RTX); 3167 3168 /* Replace the old sequence with the new. */ |
3169 try = emit_insn_after_setloc (try, peep2_insn_data[i].insn, 3170 INSN_LOCATOR (peep2_insn_data[i].insn)); |
3171 before_try = PREV_INSN (insn); 3172 delete_insn_chain (insn, peep2_insn_data[i].insn); 3173 3174 /* Re-insert the EH_REGION notes. */ 3175 if (note || (was_call && nonlocal_goto_handler_labels)) 3176 { 3177 edge eh_edge; 3178 --- 9 unchanged lines hidden (view full) --- 3188 && !find_reg_note (x, REG_EH_REGION, NULL))) 3189 { 3190 if (note) 3191 REG_NOTES (x) 3192 = gen_rtx_EXPR_LIST (REG_EH_REGION, 3193 XEXP (note, 0), 3194 REG_NOTES (x)); 3195 |
3196 if (x != BB_END (bb) && eh_edge) |
3197 { 3198 edge nfte, nehe; 3199 int flags; 3200 3201 nfte = split_block (bb, x); 3202 flags = (eh_edge->flags 3203 & (EDGE_EH | EDGE_ABNORMAL)); 3204 if (GET_CODE (x) == CALL_INSN) --- 67 unchanged lines hidden (view full) --- 3272 if (GET_CODE (x) == JUMP_INSN) 3273 { 3274 do_rebuild_jump_labels = true; 3275 break; 3276 } 3277 } 3278 } 3279 |
3280 if (insn == BB_HEAD (bb)) |
3281 break; 3282 } 3283 3284 free_propagate_block_info (pbi); 3285 } 3286 3287 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3288 FREE_REG_SET (peep2_insn_data[i].live_before); --- 24 unchanged lines hidden (view full) --- 3313/* Common predicates for use with define_bypass. */ 3314 3315/* True if the dependency between OUT_INSN and IN_INSN is on the store 3316 data not the address operand(s) of the store. IN_INSN must be 3317 single_set. OUT_INSN must be either a single_set or a PARALLEL with 3318 SETs inside. */ 3319 3320int |
3321store_data_bypass_p (rtx out_insn, rtx in_insn) |
3322{ 3323 rtx out_set, in_set; 3324 3325 in_set = single_set (in_insn); 3326 if (! in_set) 3327 abort (); 3328 3329 if (GET_CODE (SET_DEST (in_set)) != MEM) --- 33 unchanged lines hidden (view full) --- 3363} 3364 3365/* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE 3366 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single 3367 or multiple set; IN_INSN should be single_set for truth, but for convenience 3368 of insn categorization may be any JUMP or CALL insn. */ 3369 3370int |
3371if_test_bypass_p (rtx out_insn, rtx in_insn) |
3372{ 3373 rtx out_set, in_set; 3374 3375 in_set = single_set (in_insn); 3376 if (! in_set) 3377 { 3378 if (GET_CODE (in_insn) == JUMP_INSN || GET_CODE (in_insn) == CALL_INSN) 3379 return false; --- 41 unchanged lines hidden --- |