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schizo.c (266020) schizo.c (292789)
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 18 unchanged lines hidden (view full) ---

27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/schizo.c 266020 2014-05-14 14:17:51Z ian $");
35__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/schizo.c 292789 2015-12-27 19:37:47Z marius $");
36
37/*
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to
39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges
40 */
41
42#include "opt_ofw_pci.h"
43#include "opt_schizo.h"

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52#include <sys/mutex.h>
53#include <sys/pcpu.h>
54#include <sys/rman.h>
55#include <sys/sysctl.h>
56#include <sys/time.h>
57#include <sys/timetc.h>
58
59#include <dev/ofw/ofw_bus.h>
36
37/*
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to
39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges
40 */
41
42#include "opt_ofw_pci.h"
43#include "opt_schizo.h"

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52#include <sys/mutex.h>
53#include <sys/pcpu.h>
54#include <sys/rman.h>
55#include <sys/sysctl.h>
56#include <sys/time.h>
57#include <sys/timetc.h>
58
59#include <dev/ofw/ofw_bus.h>
60#include <dev/ofw/ofw_pci.h>
61#include <dev/ofw/openfirm.h>
62
63#include <machine/bus.h>
64#include <machine/bus_common.h>
65#include <machine/bus_private.h>
60#include <dev/ofw/openfirm.h>
61
62#include <machine/bus.h>
63#include <machine/bus_common.h>
64#include <machine/bus_private.h>
66#include <machine/fsr.h>
67#include <machine/iommureg.h>
68#include <machine/iommuvar.h>
69#include <machine/resource.h>
70
71#include <dev/pci/pcireg.h>
72#include <dev/pci/pcivar.h>
73
74#include <sparc64/pci/ofw_pci.h>

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103/* IOMMU support */
104static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
105
106/*
107 * Methods
108 */
109static device_probe_t schizo_probe;
110static device_attach_t schizo_attach;
65#include <machine/iommureg.h>
66#include <machine/iommuvar.h>
67#include <machine/resource.h>
68
69#include <dev/pci/pcireg.h>
70#include <dev/pci/pcivar.h>
71
72#include <sparc64/pci/ofw_pci.h>

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101/* IOMMU support */
102static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
103
104/*
105 * Methods
106 */
107static device_probe_t schizo_probe;
108static device_attach_t schizo_attach;
111static bus_read_ivar_t schizo_read_ivar;
112static bus_setup_intr_t schizo_setup_intr;
113static bus_alloc_resource_t schizo_alloc_resource;
109static bus_setup_intr_t schizo_setup_intr;
110static bus_alloc_resource_t schizo_alloc_resource;
114static bus_activate_resource_t schizo_activate_resource;
115static bus_adjust_resource_t schizo_adjust_resource;
116static bus_get_dma_tag_t schizo_get_dma_tag;
117static pcib_maxslots_t schizo_maxslots;
118static pcib_read_config_t schizo_read_config;
119static pcib_write_config_t schizo_write_config;
120static pcib_route_interrupt_t schizo_route_interrupt;
111static pcib_maxslots_t schizo_maxslots;
112static pcib_read_config_t schizo_read_config;
113static pcib_write_config_t schizo_write_config;
114static pcib_route_interrupt_t schizo_route_interrupt;
121static ofw_bus_get_node_t schizo_get_node;
122static ofw_pci_setup_device_t schizo_setup_device;
123
124static device_method_t schizo_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, schizo_probe),
127 DEVMETHOD(device_attach, schizo_attach),
128 DEVMETHOD(device_shutdown, bus_generic_shutdown),
129 DEVMETHOD(device_suspend, bus_generic_suspend),
130 DEVMETHOD(device_resume, bus_generic_resume),
131
132 /* Bus interface */
115static ofw_pci_setup_device_t schizo_setup_device;
116
117static device_method_t schizo_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, schizo_probe),
120 DEVMETHOD(device_attach, schizo_attach),
121 DEVMETHOD(device_shutdown, bus_generic_shutdown),
122 DEVMETHOD(device_suspend, bus_generic_suspend),
123 DEVMETHOD(device_resume, bus_generic_resume),
124
125 /* Bus interface */
133 DEVMETHOD(bus_read_ivar, schizo_read_ivar),
126 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
134 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
135 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
136 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
127 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
128 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
129 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
137 DEVMETHOD(bus_activate_resource, schizo_activate_resource),
130 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
138 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
131 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
139 DEVMETHOD(bus_adjust_resource, schizo_adjust_resource),
132 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
140 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
133 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
141 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
134 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
142
143 /* pcib interface */
144 DEVMETHOD(pcib_maxslots, schizo_maxslots),
145 DEVMETHOD(pcib_read_config, schizo_read_config),
146 DEVMETHOD(pcib_write_config, schizo_write_config),
147 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
148
149 /* ofw_bus interface */
135
136 /* pcib interface */
137 DEVMETHOD(pcib_maxslots, schizo_maxslots),
138 DEVMETHOD(pcib_read_config, schizo_read_config),
139 DEVMETHOD(pcib_write_config, schizo_write_config),
140 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
141
142 /* ofw_bus interface */
150 DEVMETHOD(ofw_bus_get_node, schizo_get_node),
143 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
151
152 /* ofw_pci interface */
153 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device),
154
155 DEVMETHOD_END
156};
157
158static devclass_t schizo_devclass;

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265 return (0);
266 }
267 return (ENXIO);
268}
269
270static int
271schizo_attach(device_t dev)
272{
144
145 /* ofw_pci interface */
146 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device),
147
148 DEVMETHOD_END
149};
150
151static devclass_t schizo_devclass;

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258 return (0);
259 }
260 return (ENXIO);
261}
262
263static int
264schizo_attach(device_t dev)
265{
273 struct ofw_pci_ranges *range;
274 const struct schizo_desc *desc;
275 struct schizo_softc *asc, *sc, *osc;
276 struct timecounter *tc;
266 const struct schizo_desc *desc;
267 struct schizo_softc *asc, *sc, *osc;
268 struct timecounter *tc;
269 bus_dma_tag_t dmat;
277 uint64_t ino_bitmap, reg;
278 phandle_t node;
279 uint32_t prop, prop_array[2];
280 int i, j, mode, rid, tsbsize;
281
282 sc = device_get_softc(dev);
283 node = ofw_bus_get_node(dev);
284 desc = schizo_get_desc(dev);
285 mode = desc->sd_mode;
286
287 sc->sc_dev = dev;
270 uint64_t ino_bitmap, reg;
271 phandle_t node;
272 uint32_t prop, prop_array[2];
273 int i, j, mode, rid, tsbsize;
274
275 sc = device_get_softc(dev);
276 node = ofw_bus_get_node(dev);
277 desc = schizo_get_desc(dev);
278 mode = desc->sd_mode;
279
280 sc->sc_dev = dev;
288 sc->sc_node = node;
289 sc->sc_mode = mode;
290 sc->sc_flags = 0;
291
292 /*
293 * The Schizo has three register banks:
294 * (0) per-PBM PCI configuration and status registers, but for bus B
295 * shared with the UPA64s interrupt mapping register banks
296 * (1) shared Schizo controller configuration and status registers

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342 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
343 } else {
344 if (sc->sc_mode != SCHIZO_MODE_SCZ)
345 panic("%s: no partner expected", __func__);
346 if (mtx_initialized(osc->sc_mtx) == 0)
347 panic("%s: mutex not initialized", __func__);
348 sc->sc_mtx = osc->sc_mtx;
349 }
281 sc->sc_mode = mode;
282 sc->sc_flags = 0;
283
284 /*
285 * The Schizo has three register banks:
286 * (0) per-PBM PCI configuration and status registers, but for bus B
287 * shared with the UPA64s interrupt mapping register banks
288 * (1) shared Schizo controller configuration and status registers

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334 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
335 } else {
336 if (sc->sc_mode != SCHIZO_MODE_SCZ)
337 panic("%s: no partner expected", __func__);
338 if (mtx_initialized(osc->sc_mtx) == 0)
339 panic("%s: mutex not initialized", __func__);
340 sc->sc_mtx = osc->sc_mtx;
341 }
342 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
350
351 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
352 panic("%s: could not determine IGN", __func__);
353 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
354 -1)
355 panic("%s: could not determine version", __func__);
356 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#",
357 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1)

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537 __func__, prop_array[1]);
538 /* NOTREACHED */
539 }
540 schizo_iommu_init(sc, tsbsize, prop_array[0]);
541 }
542
543#undef TSBCASE
544
343
344 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
345 panic("%s: could not determine IGN", __func__);
346 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
347 -1)
348 panic("%s: could not determine version", __func__);
349 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#",
350 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1)

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530 __func__, prop_array[1]);
531 /* NOTREACHED */
532 }
533 schizo_iommu_init(sc, tsbsize, prop_array[0]);
534 }
535
536#undef TSBCASE
537
545 /* Initialize memory and I/O rmans. */
546 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
547 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
548 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
549 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
550 panic("%s: failed to set up I/O rman", __func__);
551 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
552 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
553 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
554 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
555 panic("%s: failed to set up memory rman", __func__);
556
557 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
558 /*
559 * Make sure that the expected ranges are present. The
560 * OFW_PCI_CS_MEM64 one is not currently used though.
561 */
562 if (i != STX_NRANGE)
563 panic("%s: unsupported number of ranges", __func__);
564 /*
565 * Find the addresses of the various bus spaces.
566 * There should not be multiple ones of one kind.
567 * The physical start addresses of the ranges are the configuration,
568 * memory and I/O handles.
569 */
570 for (i = 0; i < STX_NRANGE; i++) {
571 j = OFW_PCI_RANGE_CS(&range[i]);
572 if (sc->sc_pci_bh[j] != 0)
573 panic("%s: duplicate range for space %d",
574 __func__, j);
575 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
576 }
577 free(range, M_OFWPROP);
578
579 /* Register the softc, this is needed for paired Schizos. */
580 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
581
582 /* Allocate our tags. */
583 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
584 sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL);
585 if (sc->sc_pci_iot == NULL)
586 panic("%s: could not allocate PCI I/O tag", __func__);
587 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
588 sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL);
589 if (sc->sc_pci_cfgt == NULL)
590 panic("%s: could not allocate PCI configuration space tag",
591 __func__);
538 /* Create our DMA tag. */
592 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
593 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL,
594 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL,
539 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
540 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL,
541 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL,
595 &sc->sc_pci_dmat) != 0)
542 &dmat) != 0)
596 panic("%s: could not create PCI DMA tag", __func__);
543 panic("%s: could not create PCI DMA tag", __func__);
597 /* Customize the tag. */
598 sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
599 sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods;
544 dmat->dt_cookie = &sc->sc_is;
545 dmat->dt_mt = &sc->sc_dma_methods;
600
546
601 /*
602 * Get the bus range from the firmware.
603 * NB: Tomatillos don't support PCI bus reenumeration.
604 */
605 i = OF_getprop(node, "bus-range", (void *)prop_array,
606 sizeof(prop_array));
607 if (i == -1)
608 panic("%s: could not get bus-range", __func__);
609 if (i != sizeof(prop_array))
610 panic("%s: broken bus-range (%d)", __func__, i);
611 sc->sc_pci_secbus = prop_array[0];
612 sc->sc_pci_subbus = prop_array[1];
613 if (bootverbose)
614 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
615 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
547 if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0)
548 panic("%s: ofw_pci_attach_common() failed", __func__);
616
617 /* Clear any pending PCI error bits. */
549
550 /* Clear any pending PCI error bits. */
618 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
619 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
620 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
551 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
552 STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev,
553 sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS,
554 2), 2);
621 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
622 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
623
624 /*
625 * Establish handlers for interesting interrupts...
626 * Someone at Sun clearly was smoking crack; with Schizos PCI
627 * bus error interrupts for one PBM can be routed to the other
628 * PBM though we obviously need to use the softc of the former

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740 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
741 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
742 }
743
744 /*
745 * Set the latency timer register as this isn't always done by the
746 * firmware.
747 */
555 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
556 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
557
558 /*
559 * Establish handlers for interesting interrupts...
560 * Someone at Sun clearly was smoking crack; with Schizos PCI
561 * bus error interrupts for one PBM can be routed to the other
562 * PBM though we obviously need to use the softc of the former

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674 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
675 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
676 }
677
678 /*
679 * Set the latency timer register as this isn't always done by the
680 * firmware.
681 */
748 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
749 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
682 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
683 STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
750
684
751 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
752
753#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
754 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
755 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
756 (name), CTLFLAG_RD, (arg), 0, (desc))
757
758 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
759 "DMA correctable errors");
760 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,

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867 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
868 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
869 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
870 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
871 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
872 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT);
873 else
874 xstat = 0;
685#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
686 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
687 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
688 (name), CTLFLAG_RD, (arg), 0, (desc))
689
690 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
691 "DMA correctable errors");
692 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,

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799 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
800 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
801 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
802 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
803 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
804 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT);
805 else
806 xstat = 0;
875 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
807 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus,
876 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
877
878 /*
879 * IOMMU errors are only fatal on Tomatillo and there also only if
880 * target abort was not signaled.
881 */
882 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
883 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&

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908
909 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
910 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n",
911 'A' + sc->sc_half, (unsigned long long)afar,
912 (unsigned long long)afsr, (unsigned long long)csr,
913 (unsigned long long)iommu, (unsigned long long)xstat, status);
914
915 /* Clear the error bits that we caught. */
808 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
809
810 /*
811 * IOMMU errors are only fatal on Tomatillo and there also only if
812 * target abort was not signaled.
813 */
814 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
815 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&

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840
841 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
842 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n",
843 'A' + sc->sc_half, (unsigned long long)afar,
844 (unsigned long long)afsr, (unsigned long long)csr,
845 (unsigned long long)iommu, (unsigned long long)xstat, status);
846
847 /* Clear the error bits that we caught. */
916 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
848 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
917 STX_CS_FUNC, PCIR_STATUS, status, 2);
918 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
919 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
920 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
921 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
922 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat);
923
924 mtx_unlock_spin(sc->sc_mtx);

--- 104 unchanged lines hidden (view full) ---

1029 return (PCI_SLOTMAX);
1030}
1031
1032static uint32_t
1033schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
1034 int width)
1035{
1036 struct schizo_softc *sc;
849 STX_CS_FUNC, PCIR_STATUS, status, 2);
850 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
851 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
852 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
853 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
854 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat);
855
856 mtx_unlock_spin(sc->sc_mtx);

--- 104 unchanged lines hidden (view full) ---

961 return (PCI_SLOTMAX);
962}
963
964static uint32_t
965schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
966 int width)
967{
968 struct schizo_softc *sc;
1037 bus_space_handle_t bh;
1038 u_long offset = 0;
1039 uint32_t r, wrd;
1040 int i;
1041 uint16_t shrt;
1042 uint8_t byte;
1043
1044 sc = device_get_softc(dev);
969
970 sc = device_get_softc(dev);
1045 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1046 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1047 return (-1);
1048
1049 /*
1050 * The Schizo bridges contain a dupe of their header at 0x80.
1051 */
971 /*
972 * The Schizo bridges contain a dupe of their header at 0x80.
973 */
1052 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
1053 slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
1054 reg + width > 0x80)
974 if (sc->sc_mode == SCHIZO_MODE_SCZ &&
975 bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE &&
976 func == STX_CS_FUNC && reg + width > 0x80)
1055 return (0);
1056
977 return (0);
978
1057 offset = STX_CONF_OFF(bus, slot, func, reg);
1058 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1059 switch (width) {
1060 case 1:
1061 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
1062 r = byte;
1063 break;
1064 case 2:
1065 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
1066 r = shrt;
1067 break;
1068 case 4:
1069 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
1070 r = wrd;
1071 break;
1072 default:
1073 panic("%s: bad width", __func__);
1074 /* NOTREACHED */
1075 }
1076
1077 if (i) {
1078#ifdef SCHIZO_DEBUG
1079 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
1080 __func__, bus, slot, func, reg);
1081#endif
1082 r = -1;
1083 }
1084 return (r);
979 return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus,
980 slot, func, reg), bus, slot, func, reg, width));
1085}
1086
1087static void
1088schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1089 u_int reg, uint32_t val, int width)
1090{
981}
982
983static void
984schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
985 u_int reg, uint32_t val, int width)
986{
1091 struct schizo_softc *sc;
1092 bus_space_handle_t bh;
1093 u_long offset = 0;
1094
987
1095 sc = device_get_softc(dev);
1096 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1097 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1098 return;
1099
1100 offset = STX_CONF_OFF(bus, slot, func, reg);
1101 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1102 switch (width) {
1103 case 1:
1104 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1105 break;
1106 case 2:
1107 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1108 break;
1109 case 4:
1110 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1111 break;
1112 default:
1113 panic("%s: bad width", __func__);
1114 /* NOTREACHED */
1115 }
988 ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot,
989 func, reg), bus, slot, func, reg, val, width);
1116}
1117
1118static int
1119schizo_route_interrupt(device_t bridge, device_t dev, int pin)
1120{
990}
991
992static int
993schizo_route_interrupt(device_t bridge, device_t dev, int pin)
994{
1121 struct schizo_softc *sc;
1122 struct ofw_pci_register reg;
1123 ofw_pci_intr_t pintr, mintr;
995 ofw_pci_intr_t mintr;
1124
996
1125 sc = device_get_softc(bridge);
1126 pintr = pin;
1127 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1128 &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1129 NULL))
1130 return (mintr);
1131
1132 device_printf(bridge, "could not route pin %d for device %d.%d\n",
1133 pin, pci_get_slot(dev), pci_get_function(dev));
1134 return (PCI_INVALID_IRQ);
997 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
998 if (!PCI_INTERRUPT_VALID(mintr))
999 device_printf(bridge,
1000 "could not route pin %d for device %d.%d\n",
1001 pin, pci_get_slot(dev), pci_get_function(dev));
1002 return (mintr);
1135}
1136
1003}
1004
1137static int
1138schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1139{
1140 struct schizo_softc *sc;
1141
1142 sc = device_get_softc(dev);
1143 switch (which) {
1144 case PCIB_IVAR_DOMAIN:
1145 *result = device_get_unit(dev);
1146 return (0);
1147 case PCIB_IVAR_BUS:
1148 *result = sc->sc_pci_secbus;
1149 return (0);
1150 }
1151 return (ENOENT);
1152}
1153
1154static void
1155schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1156{
1157 struct timeval cur, end;
1158 struct schizo_iommu_state *sis = dt->dt_cookie;
1159 struct schizo_softc *sc = sis->sis_sc;
1160 int i, res;
1161#ifdef INVARIANTS

--- 49 unchanged lines hidden (view full) ---

1211
1212 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1213 membar(Sync);
1214}
1215
1216static void
1217ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1218{
1005static void
1006schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1007{
1008 struct timeval cur, end;
1009 struct schizo_iommu_state *sis = dt->dt_cookie;
1010 struct schizo_softc *sc = sis->sis_sc;
1011 int i, res;
1012#ifdef INVARIANTS

--- 49 unchanged lines hidden (view full) ---

1062
1063 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1064 membar(Sync);
1065}
1066
1067static void
1068ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1069{
1219 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
1220 struct timeval cur, end;
1221 struct schizo_iommu_state *sis = dt->dt_cookie;
1222 struct schizo_softc *sc = sis->sis_sc;
1070 struct timeval cur, end;
1071 struct schizo_iommu_state *sis = dt->dt_cookie;
1072 struct schizo_softc *sc = sis->sis_sc;
1223 register_t reg, s;
1073 uint64_t reg;
1224
1225 if ((map->dm_flags & DMF_STREAMED) != 0) {
1226 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1227 return;
1228 }
1229
1230 if ((map->dm_flags & DMF_LOADED) == 0)
1231 return;

--- 11 unchanged lines hidden (view full) ---

1243 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 &&
1244 timevalcmp(&cur, &end, <=);)
1245 microuptime(&cur);
1246 if ((reg & sc->sc_sync_val) != 0)
1247 panic("%s: DMA does not sync", __func__);
1248 if (sc->sc_mode == SCHIZO_MODE_XMS)
1249 mtx_unlock_spin(&sc->sc_sync_mtx);
1250 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1074
1075 if ((map->dm_flags & DMF_STREAMED) != 0) {
1076 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1077 return;
1078 }
1079
1080 if ((map->dm_flags & DMF_LOADED) == 0)
1081 return;

--- 11 unchanged lines hidden (view full) ---

1093 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 &&
1094 timevalcmp(&cur, &end, <=);)
1095 microuptime(&cur);
1096 if ((reg & sc->sc_sync_val) != 0)
1097 panic("%s: DMA does not sync", __func__);
1098 if (sc->sc_mode == SCHIZO_MODE_XMS)
1099 mtx_unlock_spin(&sc->sc_sync_mtx);
1100 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1251 s = intr_disable();
1252 reg = rd(fprs);
1253 wr(fprs, reg | FPRS_FEF, 0);
1254 __asm __volatile("stda %%f0, [%0] %1"
1255 : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
1256 membar(Sync);
1257 wr(fprs, reg, 0);
1258 intr_restore(s);
1101 ofw_pci_dmamap_sync_stst_order_common();
1259 return;
1260 }
1261 }
1262
1263 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1264 membar(Sync);
1265}
1266

--- 84 unchanged lines hidden (view full) ---

1351 arg, cookiep));
1352}
1353
1354static struct resource *
1355schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1356 u_long start, u_long end, u_long count, u_int flags)
1357{
1358 struct schizo_softc *sc;
1102 return;
1103 }
1104 }
1105
1106 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1107 membar(Sync);
1108}
1109

--- 84 unchanged lines hidden (view full) ---

1194 arg, cookiep));
1195}
1196
1197static struct resource *
1198schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1199 u_long start, u_long end, u_long count, u_int flags)
1200{
1201 struct schizo_softc *sc;
1359 struct resource *rv;
1360 struct rman *rm;
1361
1202
1362 sc = device_get_softc(bus);
1363 switch (type) {
1364 case SYS_RES_IRQ:
1365 /*
1366 * XXX: Don't accept blank ranges for now, only single
1367 * interrupts. The other case should not happen with
1368 * the MI PCI code...
1369 * XXX: This may return a resource that is out of the
1370 * range that was specified. Is this correct...?
1371 */
1372 if (start != end)
1373 panic("%s: XXX: interrupt range", __func__);
1203 if (type == SYS_RES_IRQ) {
1204 sc = device_get_softc(bus);
1374 start = end = INTMAP_VEC(sc->sc_ign, end);
1205 start = end = INTMAP_VEC(sc->sc_ign, end);
1375 return (bus_generic_alloc_resource(bus, child, type, rid,
1376 start, end, count, flags));
1377 case SYS_RES_MEMORY:
1378 rm = &sc->sc_pci_mem_rman;
1379 break;
1380 case SYS_RES_IOPORT:
1381 rm = &sc->sc_pci_io_rman;
1382 break;
1383 default:
1384 return (NULL);
1385 }
1206 }
1386
1387 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
1388 child);
1389 if (rv == NULL)
1390 return (NULL);
1391 rman_set_rid(rv, *rid);
1392
1393 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
1394 *rid, rv) != 0) {
1395 rman_release_resource(rv);
1396 return (NULL);
1397 }
1398 return (rv);
1207 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1208 count, flags));
1399}
1400
1209}
1210
1401static int
1402schizo_activate_resource(device_t bus, device_t child, int type, int rid,
1403 struct resource *r)
1404{
1405 struct schizo_softc *sc;
1406 struct bus_space_tag *tag;
1407
1408 sc = device_get_softc(bus);
1409 switch (type) {
1410 case SYS_RES_IRQ:
1411 return (bus_generic_activate_resource(bus, child, type, rid,
1412 r));
1413 case SYS_RES_MEMORY:
1414 tag = sparc64_alloc_bus_tag(r, rman_get_bustag(
1415 sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL);
1416 if (tag == NULL)
1417 return (ENOMEM);
1418 rman_set_bustag(r, tag);
1419 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
1420 rman_get_start(r));
1421 break;
1422 case SYS_RES_IOPORT:
1423 rman_set_bustag(r, sc->sc_pci_iot);
1424 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
1425 rman_get_start(r));
1426 break;
1427 }
1428 return (rman_activate_resource(r));
1429}
1430
1431static int
1432schizo_adjust_resource(device_t bus, device_t child, int type,
1433 struct resource *r, u_long start, u_long end)
1434{
1435 struct schizo_softc *sc;
1436 struct rman *rm;
1437
1438 sc = device_get_softc(bus);
1439 switch (type) {
1440 case SYS_RES_IRQ:
1441 return (bus_generic_adjust_resource(bus, child, type, r,
1442 start, end));
1443 case SYS_RES_MEMORY:
1444 rm = &sc->sc_pci_mem_rman;
1445 break;
1446 case SYS_RES_IOPORT:
1447 rm = &sc->sc_pci_io_rman;
1448 break;
1449 default:
1450 return (EINVAL);
1451 }
1452 if (rman_is_region_manager(r, rm) == 0)
1453 return (EINVAL);
1454 return (rman_adjust_resource(r, start, end));
1455}
1456
1457static bus_dma_tag_t
1458schizo_get_dma_tag(device_t bus, device_t child __unused)
1459{
1460 struct schizo_softc *sc;
1461
1462 sc = device_get_softc(bus);
1463 return (sc->sc_pci_dmat);
1464}
1465
1466static phandle_t
1467schizo_get_node(device_t bus, device_t child __unused)
1468{
1469 struct schizo_softc *sc;
1470
1471 sc = device_get_softc(bus);
1472 /* We only have one child, the PCI bus, which needs our own node. */
1473 return (sc->sc_node);
1474}
1475
1476static void
1477schizo_setup_device(device_t bus, device_t child)
1478{
1479 struct schizo_softc *sc;
1480 uint64_t reg;
1481 int capreg;
1482
1483 sc = device_get_softc(bus);

--- 38 unchanged lines hidden --- 		1211static void
1212schizo_setup_device(device_t bus, device_t child)
1213{
1214 struct schizo_softc *sc;
1215 uint64_t reg;
1216 int capreg;
1217
1218 sc = device_get_softc(bus);

--- 38 unchanged lines hidden ---