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psycho.c (266020) psycho.c (292789)
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 17 unchanged lines hidden (view full) ---

26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 17 unchanged lines hidden (view full) ---

26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 266020 2014-05-14 14:17:51Z ian $");
34__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 292789 2015-12-27 19:37:47Z marius $");
35
36/*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41#include "opt_ofw_pci.h"
42#include "opt_psycho.h"

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52#include <sys/module.h>
53#include <sys/mutex.h>
54#include <sys/pcpu.h>
55#include <sys/reboot.h>
56#include <sys/rman.h>
57#include <sys/sysctl.h>
58
59#include <dev/ofw/ofw_bus.h>
35
36/*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41#include "opt_ofw_pci.h"
42#include "opt_psycho.h"

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52#include <sys/module.h>
53#include <sys/mutex.h>
54#include <sys/pcpu.h>
55#include <sys/reboot.h>
56#include <sys/rman.h>
57#include <sys/sysctl.h>
58
59#include <dev/ofw/ofw_bus.h>
60#include <dev/ofw/ofw_pci.h>
61#include <dev/ofw/openfirm.h>
62
63#include <machine/bus.h>
64#include <machine/bus_common.h>
65#include <machine/bus_private.h>
66#include <machine/iommureg.h>
67#include <machine/iommuvar.h>
68#include <machine/resource.h>

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105/* IOMMU support */
106static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
107
108/*
109 * Methods
110 */
111static device_probe_t psycho_probe;
112static device_attach_t psycho_attach;
60#include <dev/ofw/openfirm.h>
61
62#include <machine/bus.h>
63#include <machine/bus_common.h>
64#include <machine/bus_private.h>
65#include <machine/iommureg.h>
66#include <machine/iommuvar.h>
67#include <machine/resource.h>

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104/* IOMMU support */
105static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
106
107/*
108 * Methods
109 */
110static device_probe_t psycho_probe;
111static device_attach_t psycho_attach;
113static bus_read_ivar_t psycho_read_ivar;
114static bus_setup_intr_t psycho_setup_intr;
115static bus_alloc_resource_t psycho_alloc_resource;
112static bus_setup_intr_t psycho_setup_intr;
113static bus_alloc_resource_t psycho_alloc_resource;
116static bus_activate_resource_t psycho_activate_resource;
117static bus_adjust_resource_t psycho_adjust_resource;
118static bus_get_dma_tag_t psycho_get_dma_tag;
119static pcib_maxslots_t psycho_maxslots;
120static pcib_read_config_t psycho_read_config;
121static pcib_write_config_t psycho_write_config;
122static pcib_route_interrupt_t psycho_route_interrupt;
114static pcib_maxslots_t psycho_maxslots;
115static pcib_read_config_t psycho_read_config;
116static pcib_write_config_t psycho_write_config;
117static pcib_route_interrupt_t psycho_route_interrupt;
123static ofw_bus_get_node_t psycho_get_node;
124static ofw_pci_setup_device_t psycho_setup_device;
125
126static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
133
134 /* Bus interface */
118static ofw_pci_setup_device_t psycho_setup_device;
119
120static device_method_t psycho_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, psycho_probe),
123 DEVMETHOD(device_attach, psycho_attach),
124 DEVMETHOD(device_shutdown, bus_generic_shutdown),
125 DEVMETHOD(device_suspend, bus_generic_suspend),
126 DEVMETHOD(device_resume, bus_generic_resume),
127
128 /* Bus interface */
135 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
129 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
136 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
137 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
130 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
131 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
132 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
139 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
133 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
140 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
141 DEVMETHOD(bus_adjust_resource, psycho_adjust_resource),
135 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
142 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
136 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
137 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
144
145 /* pcib interface */
146 DEVMETHOD(pcib_maxslots, psycho_maxslots),
147 DEVMETHOD(pcib_read_config, psycho_read_config),
148 DEVMETHOD(pcib_write_config, psycho_write_config),
149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
150
151 /* ofw_bus interface */
138
139 /* pcib interface */
140 DEVMETHOD(pcib_maxslots, psycho_maxslots),
141 DEVMETHOD(pcib_read_config, psycho_read_config),
142 DEVMETHOD(pcib_write_config, psycho_write_config),
143 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
144
145 /* ofw_bus interface */
152 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
146 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
153
154 /* ofw_pci interface */
155 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
156
157 DEVMETHOD_END
158};
159
160static devclass_t psycho_devclass;

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283 return (ENXIO);
284}
285
286static int
287psycho_attach(device_t dev)
288{
289 struct psycho_icarg *pica;
290 struct psycho_softc *asc, *sc, *osc;
147
148 /* ofw_pci interface */
149 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
150
151 DEVMETHOD_END
152};
153
154static devclass_t psycho_devclass;

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277 return (ENXIO);
278}
279
280static int
281psycho_attach(device_t dev)
282{
283 struct psycho_icarg *pica;
284 struct psycho_softc *asc, *sc, *osc;
291 struct ofw_pci_ranges *range;
292 const struct psycho_desc *desc;
293 bus_addr_t intrclr, intrmap;
285 const struct psycho_desc *desc;
286 bus_addr_t intrclr, intrmap;
287 bus_dma_tag_t dmat;
294 uint64_t csr, dr;
295 phandle_t node;
288 uint64_t csr, dr;
289 phandle_t node;
296 uint32_t dvmabase, prop, prop_array[2];
290 uint32_t dvmabase, prop;
297 u_int rerun, ver;
298 int i, j;
299
300 node = ofw_bus_get_node(dev);
301 sc = device_get_softc(dev);
302 desc = psycho_get_desc(dev);
303
291 u_int rerun, ver;
292 int i, j;
293
294 node = ofw_bus_get_node(dev);
295 sc = device_get_softc(dev);
296 desc = psycho_get_desc(dev);
297
304 sc->sc_node = node;
305 sc->sc_dev = dev;
306 sc->sc_mode = desc->pd_mode;
307
308 /*
309 * The Psycho gets three register banks:
310 * (0) per-PBM configuration and status registers
311 * (1) per-PBM PCI configuration space, containing only the
312 * PBM 256-byte PCI header

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362 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
363 } else {
364 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
365 panic("%s: no partner expected", __func__);
366 if (mtx_initialized(osc->sc_mtx) == 0)
367 panic("%s: mutex not initialized", __func__);
368 sc->sc_mtx = osc->sc_mtx;
369 }
298 sc->sc_dev = dev;
299 sc->sc_mode = desc->pd_mode;
300
301 /*
302 * The Psycho gets three register banks:
303 * (0) per-PBM configuration and status registers
304 * (1) per-PBM PCI configuration space, containing only the
305 * PBM 256-byte PCI header

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355 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
356 } else {
357 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
358 panic("%s: no partner expected", __func__);
359 if (mtx_initialized(osc->sc_mtx) == 0)
360 panic("%s: mutex not initialized", __func__);
361 sc->sc_mtx = osc->sc_mtx;
362 }
363 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
370
371 csr = PSYCHO_READ8(sc, PSR_CS);
372 ver = PSYCHO_GCSR_VERS(csr);
373 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
374 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
375 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
376 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
377 prop = 33000000;

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430 csr = PCICTL_READ8(sc, PCR_TAS);
431 if (csr == 0)
432 panic("%s: Hummingbird/Sabre TAS not initialized.",
433 __func__);
434 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
435 } else
436 dvmabase = -1;
437
364
365 csr = PSYCHO_READ8(sc, PSR_CS);
366 ver = PSYCHO_GCSR_VERS(csr);
367 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
368 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
369 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
370 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
371 prop = 33000000;

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424 csr = PCICTL_READ8(sc, PCR_TAS);
425 if (csr == 0)
426 panic("%s: Hummingbird/Sabre TAS not initialized.",
427 __func__);
428 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
429 } else
430 dvmabase = -1;
431
438 /* Initialize memory and I/O rmans. */
439 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
440 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
441 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
442 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
443 panic("%s: failed to set up I/O rman", __func__);
444 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
445 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
446 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
447 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
448 panic("%s: failed to set up memory rman", __func__);
449
450 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
451 /*
432 /*
452 * Make sure that the expected ranges are present. The
453 * OFW_PCI_CS_MEM64 one is not currently used though.
454 */
455 if (i != PSYCHO_NRANGE)
456 panic("%s: unsupported number of ranges", __func__);
457 /*
458 * Find the addresses of the various bus spaces.
459 * There should not be multiple ones of one kind.
460 * The physical start addresses of the ranges are the configuration,
461 * memory and I/O handles.
462 */
463 for (i = 0; i < PSYCHO_NRANGE; i++) {
464 j = OFW_PCI_RANGE_CS(&range[i]);
465 if (sc->sc_pci_bh[j] != 0)
466 panic("%s: duplicate range for space %d",
467 __func__, j);
468 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
469 }
470 free(range, M_OFWPROP);
471
472 /* Register the softc, this is needed for paired Psychos. */
473 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
474
475 /*
476 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
477 * to arrive here, do the interrupt setup and start up the IOMMU.
478 */
479 if (osc == NULL) {
480 /*
481 * Hunt through all the interrupt mapping regs and register
482 * our interrupt controller for the corresponding interrupt
483 * vectors. We do this early in order to be able to catch

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567 /* Just copy IOMMU state, config tag and address. */
568 sc->sc_dma_methods = &iommu_dma_methods;
569 sc->sc_is = osc->sc_is;
570 if (OF_getproplen(node, "no-streaming-cache") < 0)
571 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
572 iommu_reset(sc->sc_is);
573 }
574
433 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
434 * to arrive here, do the interrupt setup and start up the IOMMU.
435 */
436 if (osc == NULL) {
437 /*
438 * Hunt through all the interrupt mapping regs and register
439 * our interrupt controller for the corresponding interrupt
440 * vectors. We do this early in order to be able to catch

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524 /* Just copy IOMMU state, config tag and address. */
525 sc->sc_dma_methods = &iommu_dma_methods;
526 sc->sc_is = osc->sc_is;
527 if (OF_getproplen(node, "no-streaming-cache") < 0)
528 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
529 iommu_reset(sc->sc_is);
530 }
531
575 /* Allocate our tags. */
576 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
577 sc->sc_mem_res), PCI_IO_BUS_SPACE, NULL);
578 if (sc->sc_pci_iot == NULL)
579 panic("%s: could not allocate PCI I/O tag", __func__);
580 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
581 sc->sc_mem_res), PCI_CONFIG_BUS_SPACE, NULL);
582 if (sc->sc_pci_cfgt == NULL)
583 panic("%s: could not allocate PCI configuration space tag",
584 __func__);
532 /* Create our DMA tag. */
585 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
586 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
533 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
534 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
587 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
535 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
588 panic("%s: could not create PCI DMA tag", __func__);
536 panic("%s: could not create PCI DMA tag", __func__);
589 /* Customize the tag. */
590 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
591 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
537 dmat->dt_cookie = sc->sc_is;
538 dmat->dt_mt = sc->sc_dma_methods;
592
539
593 i = OF_getprop(node, "bus-range", (void *)prop_array,
594 sizeof(prop_array));
595 if (i == -1)
596 panic("%s: could not get bus-range", __func__);
597 if (i != sizeof(prop_array))
598 panic("%s: broken bus-range (%d)", __func__, i);
599 sc->sc_pci_secbus = prop_array[0];
600 sc->sc_pci_subbus = prop_array[1];
601 if (bootverbose)
602 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
603 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
540 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
541 PSYCHO_MEM_SIZE) != 0)
542 panic("%s: ofw_pci_attach_common() failed", __func__);
604
605 /* Clear any pending PCI error bits. */
543
544 /* Clear any pending PCI error bits. */
606 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
607 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
545 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
546 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
608 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
609 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
610 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
611
612 if (osc == NULL) {
613 /*
614 * Establish handlers for interesting interrupts...
615 *

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662 */
663 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
664 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
665
666 /*
667 * Set the latency timer register as this isn't always done by the
668 * firmware.
669 */
547 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
548 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
549 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
550
551 if (osc == NULL) {
552 /*
553 * Establish handlers for interesting interrupts...
554 *

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601 */
602 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
603 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
604
605 /*
606 * Set the latency timer register as this isn't always done by the
607 * firmware.
608 */
670 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
609 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
671 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
672
673 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
610 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
611
612 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
674 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
675 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
676 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
613 le16enc(&sc->sc_pci_hpbcfg[i],
614 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
615 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
616 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
677 PCS_FUNC, i)));
678 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
617 PCS_FUNC, i)));
618 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
679 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
680 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
681 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
619 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
620 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
621 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
682
622
683 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
684 /*
685 * On E250 the interrupt map entry for the EBus bridge is wrong,
686 * causing incorrect interrupts to be assigned to some devices on
687 * the EBus. Work around it by changing our copy of the interrupt
688 * map mask to perform a full comparison of the INO. That way
689 * the interrupt map entry for the EBus bridge won't match at all
690 * and the INOs specified in the "interrupts" properties of the
691 * EBus devices will be used directly instead.
692 */
693 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
623 /*
624 * On E250 the interrupt map entry for the EBus bridge is wrong,
625 * causing incorrect interrupts to be assigned to some devices on
626 * the EBus. Work around it by changing our copy of the interrupt
627 * map mask to perform a full comparison of the INO. That way
628 * the interrupt map entry for the EBus bridge won't match at all
629 * and the INOs specified in the "interrupts" properties of the
630 * EBus devices will be used directly instead.
631 */
632 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
694 sc->sc_pci_iinfo.opi_imapmsk != NULL)
695 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
696 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
633 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
634 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
635 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
697
698 device_add_child(dev, "pci", -1);
699 return (bus_generic_attach(dev));
700}
701
702static void
703psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
704 driver_filter_t filt, driver_intr_t intr)

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922 return (PCI_SLOTMAX);
923}
924
925static uint32_t
926psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
927 int width)
928{
929 struct psycho_softc *sc;
636
637 device_add_child(dev, "pci", -1);
638 return (bus_generic_attach(dev));
639}
640
641static void
642psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
643 driver_filter_t filt, driver_intr_t intr)

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861 return (PCI_SLOTMAX);
862}
863
864static uint32_t
865psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
866 int width)
867{
868 struct psycho_softc *sc;
930 bus_space_handle_t bh;
931 u_long offset = 0;
932 uint8_t byte;
933 uint16_t shrt;
934 uint32_t r, wrd;
935 int i;
936
937 sc = device_get_softc(dev);
869
870 sc = device_get_softc(dev);
938 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
939 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
940 return (-1);
941
942 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
943
944 /*
945 * The Hummingbird and Sabre bridges are picky in that they
946 * only allow their config space to be accessed using the
947 * "native" width of the respective register being accessed
948 * and return semi-random other content of their config space
949 * otherwise. Given that the PCI specs don't say anything
950 * about such a (unusual) limitation and lots of stuff expects
951 * to be able to access the contents of the config space at
952 * any width we allow just that. We do this by using a copy
953 * of the header of the bridge (the rest is all zero anyway)
954 * read during attach (expect for PCIR_STATUS) in order to
955 * simplify things.
956 * The Psycho bridges contain a dupe of their header at 0x80
957 * which we nullify that way also.
958 */
871 /*
872 * The Hummingbird and Sabre bridges are picky in that they
873 * only allow their config space to be accessed using the
874 * "native" width of the respective register being accessed
875 * and return semi-random other content of their config space
876 * otherwise. Given that the PCI specs don't say anything
877 * about such a (unusual) limitation and lots of stuff expects
878 * to be able to access the contents of the config space at
879 * any width we allow just that. We do this by using a copy
880 * of the header of the bridge (the rest is all zero anyway)
881 * read during attach (expect for PCIR_STATUS) in order to
882 * simplify things.
883 * The Psycho bridges contain a dupe of their header at 0x80
884 * which we nullify that way also.
885 */
959 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
886 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
960 func == PCS_FUNC) {
887 func == PCS_FUNC) {
961 if (offset % width != 0)
888 if (reg % width != 0)
962 return (-1);
963
964 if (reg >= sizeof(sc->sc_pci_hpbcfg))
965 return (0);
966
967 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
968 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
969 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
889 return (-1);
890
891 if (reg >= sizeof(sc->sc_pci_hpbcfg))
892 return (0);
893
894 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
895 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
896 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
970 bus_space_read_2(sc->sc_pci_cfgt, bh,
971 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
897 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
898 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
899 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
972 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
973
974 switch (width) {
975 case 1:
976 return (sc->sc_pci_hpbcfg[reg]);
977 case 2:
978 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
979 case 4:
980 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
981 }
982 }
983
900 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
901
902 switch (width) {
903 case 1:
904 return (sc->sc_pci_hpbcfg[reg]);
905 case 2:
906 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
907 case 4:
908 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
909 }
910 }
911
984 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
985 switch (width) {
986 case 1:
987 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
988 r = byte;
989 break;
990 case 2:
991 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
992 r = shrt;
993 break;
994 case 4:
995 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
996 r = wrd;
997 break;
998 default:
999 panic("%s: bad width", __func__);
1000 /* NOTREACHED */
1001 }
1002
1003 if (i) {
1004#ifdef PSYCHO_DEBUG
1005 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
1006 __func__, bus, slot, func, reg);
1007#endif
1008 r = -1;
1009 }
1010 return (r);
912 return (ofw_pci_read_config_common(dev, PCI_REGMAX,
913 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
914 width));
1011}
1012
1013static void
1014psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1015 u_int reg, uint32_t val, int width)
1016{
915}
916
917static void
918psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
919 u_int reg, uint32_t val, int width)
920{
1017 struct psycho_softc *sc;
1018 bus_space_handle_t bh;
1019 u_long offset = 0;
1020
921
1021 sc = device_get_softc(dev);
1022 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1023 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1024 return;
1025
1026 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1027 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1028 switch (width) {
1029 case 1:
1030 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1031 break;
1032 case 2:
1033 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1034 break;
1035 case 4:
1036 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1037 break;
1038 default:
1039 panic("%s: bad width", __func__);
1040 /* NOTREACHED */
1041 }
922 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
923 slot, func, reg), bus, slot, func, reg, val, width);
1042}
1043
1044static int
1045psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1046{
1047 struct psycho_softc *sc;
924}
925
926static int
927psycho_route_interrupt(device_t bridge, device_t dev, int pin)
928{
929 struct psycho_softc *sc;
1048 struct ofw_pci_register reg;
1049 bus_addr_t intrmap;
930 bus_addr_t intrmap;
1050 ofw_pci_intr_t pintr, mintr;
931 ofw_pci_intr_t mintr;
1051
932
1052 sc = device_get_softc(bridge);
1053 pintr = pin;
1054 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1055 &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1056 NULL))
933 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
934 if (PCI_INTERRUPT_VALID(mintr))
1057 return (mintr);
1058 /*
1059 * If this is outside of the range for an intpin, it's likely a full
1060 * INO, and no mapping is required at all; this happens on the U30,
1061 * where there's no interrupt map at the Psycho node. Fortunately,
1062 * there seem to be no INOs in the intpin range on this boxen, so
1063 * this easy heuristics will do.
1064 */
1065 if (pin > 4)
1066 return (pin);
1067 /*
1068 * Guess the INO; we always assume that this is a non-OBIO
1069 * device, and that pin is a "real" intpin number. Determine
1070 * the mapping register to be used by the slot number.
1071 * We only need to do this on E450s, it seems; here, the slot numbers
1072 * for bus A are one-based, while those for bus B seemingly have an
1073 * offset of 2 (hence the factor of 3 below).
1074 */
935 return (mintr);
936 /*
937 * If this is outside of the range for an intpin, it's likely a full
938 * INO, and no mapping is required at all; this happens on the U30,
939 * where there's no interrupt map at the Psycho node. Fortunately,
940 * there seem to be no INOs in the intpin range on this boxen, so
941 * this easy heuristics will do.
942 */
943 if (pin > 4)
944 return (pin);
945 /*
946 * Guess the INO; we always assume that this is a non-OBIO
947 * device, and that pin is a "real" intpin number. Determine
948 * the mapping register to be used by the slot number.
949 * We only need to do this on E450s, it seems; here, the slot numbers
950 * for bus A are one-based, while those for bus B seemingly have an
951 * offset of 2 (hence the factor of 3 below).
952 */
953 sc = device_get_softc(dev);
1075 intrmap = PSR_PCIA0_INT_MAP +
1076 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1077 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1078 device_printf(bridge,
1079 "guessing interrupt %d for device %d.%d pin %d\n",
1080 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1081 return (mintr);
1082}
1083
954 intrmap = PSR_PCIA0_INT_MAP +
955 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
956 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
957 device_printf(bridge,
958 "guessing interrupt %d for device %d.%d pin %d\n",
959 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
960 return (mintr);
961}
962
1084static int
1085psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1086{
1087 struct psycho_softc *sc;
1088
1089 sc = device_get_softc(dev);
1090 switch (which) {
1091 case PCIB_IVAR_DOMAIN:
1092 *result = device_get_unit(dev);
1093 return (0);
1094 case PCIB_IVAR_BUS:
1095 *result = sc->sc_pci_secbus;
1096 return (0);
1097 }
1098 return (ENOENT);
1099}
1100
1101static void
1102sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1103{
1104 struct iommu_state *is = dt->dt_cookie;
1105
1106 if ((map->dm_flags & DMF_LOADED) == 0)
1107 return;
1108

--- 66 unchanged lines hidden (view full) ---

1175 arg, cookiep));
1176}
1177
1178static struct resource *
1179psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1180 u_long start, u_long end, u_long count, u_int flags)
1181{
1182 struct psycho_softc *sc;
963static void
964sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
965{
966 struct iommu_state *is = dt->dt_cookie;
967
968 if ((map->dm_flags & DMF_LOADED) == 0)
969 return;
970

--- 66 unchanged lines hidden (view full) ---

1037 arg, cookiep));
1038}
1039
1040static struct resource *
1041psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1042 u_long start, u_long end, u_long count, u_int flags)
1043{
1044 struct psycho_softc *sc;
1183 struct resource *rv;
1184 struct rman *rm;
1185
1045
1186 sc = device_get_softc(bus);
1187 switch (type) {
1188 case SYS_RES_IRQ:
1189 /*
1190 * XXX: Don't accept blank ranges for now, only single
1191 * interrupts. The other case should not happen with
1192 * the MI PCI code...
1193 * XXX: This may return a resource that is out of the
1194 * range that was specified. Is this correct...?
1195 */
1196 if (start != end)
1197 panic("%s: XXX: interrupt range", __func__);
1046 if (type == SYS_RES_IRQ) {
1047 sc = device_get_softc(bus);
1198 start = end = INTMAP_VEC(sc->sc_ign, end);
1048 start = end = INTMAP_VEC(sc->sc_ign, end);
1199 return (bus_generic_alloc_resource(bus, child, type, rid,
1200 start, end, count, flags));
1201 case SYS_RES_MEMORY:
1202 rm = &sc->sc_pci_mem_rman;
1203 break;
1204 case SYS_RES_IOPORT:
1205 rm = &sc->sc_pci_io_rman;
1206 break;
1207 default:
1208 return (NULL);
1209 }
1049 }
1210
1211 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
1212 child);
1213 if (rv == NULL)
1214 return (NULL);
1215 rman_set_rid(rv, *rid);
1216
1217 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
1218 *rid, rv) != 0) {
1219 rman_release_resource(rv);
1220 return (NULL);
1221 }
1222 return (rv);
1050 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1051 count, flags));
1223}
1224
1052}
1053
1225static int
1226psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1227 struct resource *r)
1228{
1229 struct psycho_softc *sc;
1230 struct bus_space_tag *tag;
1231
1232 sc = device_get_softc(bus);
1233 switch (type) {
1234 case SYS_RES_IRQ:
1235 return (bus_generic_activate_resource(bus, child, type, rid,
1236 r));
1237 case SYS_RES_MEMORY:
1238 tag = sparc64_alloc_bus_tag(r, rman_get_bustag(
1239 sc->sc_mem_res), PCI_MEMORY_BUS_SPACE, NULL);
1240 if (tag == NULL)
1241 return (ENOMEM);
1242 rman_set_bustag(r, tag);
1243 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
1244 rman_get_start(r));
1245 break;
1246 case SYS_RES_IOPORT:
1247 rman_set_bustag(r, sc->sc_pci_iot);
1248 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
1249 rman_get_start(r));
1250 break;
1251 }
1252 return (rman_activate_resource(r));
1253}
1254
1255static int
1256psycho_adjust_resource(device_t bus, device_t child, int type,
1257 struct resource *r, u_long start, u_long end)
1258{
1259 struct psycho_softc *sc;
1260 struct rman *rm;
1261
1262 sc = device_get_softc(bus);
1263 switch (type) {
1264 case SYS_RES_IRQ:
1265 return (bus_generic_adjust_resource(bus, child, type, r,
1266 start, end));
1267 case SYS_RES_MEMORY:
1268 rm = &sc->sc_pci_mem_rman;
1269 break;
1270 case SYS_RES_IOPORT:
1271 rm = &sc->sc_pci_io_rman;
1272 break;
1273 default:
1274 return (EINVAL);
1275 }
1276 if (rman_is_region_manager(r, rm) == 0)
1277 return (EINVAL);
1278 return (rman_adjust_resource(r, start, end));
1279}
1280
1281static bus_dma_tag_t
1282psycho_get_dma_tag(device_t bus, device_t child __unused)
1283{
1284 struct psycho_softc *sc;
1285
1286 sc = device_get_softc(bus);
1287 return (sc->sc_pci_dmat);
1288}
1289
1290static phandle_t
1291psycho_get_node(device_t bus, device_t child __unused)
1292{
1293 struct psycho_softc *sc;
1294
1295 sc = device_get_softc(bus);
1296 /* We only have one child, the PCI bus, which needs our own node. */
1297 return (sc->sc_node);
1298}
1299
1300static void
1301psycho_setup_device(device_t bus, device_t child)
1302{
1303 struct psycho_softc *sc;
1304 uint32_t rev;
1305
1306 sc = device_get_softc(bus);
1307 /*
1308 * Revision 0 EBus bridges have a bug which prevents them from
1309 * working when bus parking is enabled.
1310 */
1311 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1312 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1313 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1314 sizeof(rev)) > 0 && rev == 0)
1315 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1316 ~PCICTL_ARB_PARK);
1317}
1054static void
1055psycho_setup_device(device_t bus, device_t child)
1056{
1057 struct psycho_softc *sc;
1058 uint32_t rev;
1059
1060 sc = device_get_softc(bus);
1061 /*
1062 * Revision 0 EBus bridges have a bug which prevents them from
1063 * working when bus parking is enabled.
1064 */
1065 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1066 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1067 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1068 sizeof(rev)) > 0 && rev == 0)
1069 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1070 ~PCICTL_ARB_PARK);
1071}