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1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 266020 2014-05-14 14:17:51Z ian $");
34__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 292789 2015-12-27 19:37:47Z marius $");
35
36/*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41#include "opt_ofw_pci.h"
42#include "opt_psycho.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/bus.h>
47#include <sys/endian.h>
48#include <sys/kdb.h>
49#include <sys/kernel.h>
50#include <sys/lock.h>
51#include <sys/malloc.h>
52#include <sys/module.h>
53#include <sys/mutex.h>
54#include <sys/pcpu.h>
55#include <sys/reboot.h>
56#include <sys/rman.h>
57#include <sys/sysctl.h>
58
59#include <dev/ofw/ofw_bus.h>
60#include <dev/ofw/ofw_pci.h>
60#include <dev/ofw/openfirm.h>
61
62#include <machine/bus.h>
63#include <machine/bus_common.h>
64#include <machine/bus_private.h>
65#include <machine/iommureg.h>
66#include <machine/iommuvar.h>
67#include <machine/resource.h>
68#include <machine/ver.h>
69
70#include <dev/pci/pcireg.h>
71#include <dev/pci/pcivar.h>
72
73#include <sparc64/pci/ofw_pci.h>
74#include <sparc64/pci/psychoreg.h>
75#include <sparc64/pci/psychovar.h>
76
77#include "pcib_if.h"
78
79static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
80 const char *);
81static const struct psycho_desc *psycho_get_desc(device_t);
82static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
87 bus_dmasync_op_t op);
88static void psycho_intr_enable(void *);
89static void psycho_intr_disable(void *);
90static void psycho_intr_assign(void *);
91static void psycho_intr_clear(void *);
92
93/* Interrupt handlers */
94static driver_filter_t psycho_ue;
95static driver_filter_t psycho_ce;
96static driver_filter_t psycho_pci_bus;
97static driver_filter_t psycho_powerdebug;
98static driver_intr_t psycho_powerdown;
99static driver_intr_t psycho_overtemp;
100#ifdef PSYCHO_MAP_WAKEUP
101static driver_filter_t psycho_wakeup;
102#endif
103
104/* IOMMU support */
105static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
106
107/*
108 * Methods
109 */
110static device_probe_t psycho_probe;
111static device_attach_t psycho_attach;
113static bus_read_ivar_t psycho_read_ivar;
112static bus_setup_intr_t psycho_setup_intr;
113static bus_alloc_resource_t psycho_alloc_resource;
116static bus_activate_resource_t psycho_activate_resource;
117static bus_adjust_resource_t psycho_adjust_resource;
118static bus_get_dma_tag_t psycho_get_dma_tag;
114static pcib_maxslots_t psycho_maxslots;
115static pcib_read_config_t psycho_read_config;
116static pcib_write_config_t psycho_write_config;
117static pcib_route_interrupt_t psycho_route_interrupt;
123static ofw_bus_get_node_t psycho_get_node;
118static ofw_pci_setup_device_t psycho_setup_device;
119
120static device_method_t psycho_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, psycho_probe),
123 DEVMETHOD(device_attach, psycho_attach),
124 DEVMETHOD(device_shutdown, bus_generic_shutdown),
125 DEVMETHOD(device_suspend, bus_generic_suspend),
126 DEVMETHOD(device_resume, bus_generic_resume),
127
128 /* Bus interface */
135 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
129 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
130 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
131 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
132 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
139 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
133 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
141 DEVMETHOD(bus_adjust_resource, psycho_adjust_resource),
135 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
136 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
137 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
138
139 /* pcib interface */
140 DEVMETHOD(pcib_maxslots, psycho_maxslots),
141 DEVMETHOD(pcib_read_config, psycho_read_config),
142 DEVMETHOD(pcib_write_config, psycho_write_config),
143 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
144
145 /* ofw_bus interface */
152 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
146 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
147
148 /* ofw_pci interface */
149 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
150
151 DEVMETHOD_END
152};
153
154static devclass_t psycho_devclass;
155
156DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
157 sizeof(struct psycho_softc));
158EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL,
159 BUS_PASS_BUS);
160
161static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters");
162
163static u_int psycho_powerfail = 1;
164TUNABLE_INT("hw.psycho.powerfail", &psycho_powerfail);
165SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail,
166 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)");
167
168static SLIST_HEAD(, psycho_softc) psycho_softcs =
169 SLIST_HEAD_INITIALIZER(psycho_softcs);
170
171static const struct intr_controller psycho_ic = {
172 psycho_intr_enable,
173 psycho_intr_disable,
174 psycho_intr_assign,
175 psycho_intr_clear
176};
177
178struct psycho_icarg {
179 struct psycho_softc *pica_sc;
180 bus_addr_t pica_map;
181 bus_addr_t pica_clr;
182};
183
184#define PSYCHO_READ8(sc, off) \
185 bus_read_8((sc)->sc_mem_res, (off))
186#define PSYCHO_WRITE8(sc, off, v) \
187 bus_write_8((sc)->sc_mem_res, (off), (v))
188#define PCICTL_READ8(sc, off) \
189 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
190#define PCICTL_WRITE8(sc, off, v) \
191 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
192
193/*
194 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
195 * single PCI bus and does not have a streaming buffer. It often has an APB
196 * (advanced PCI bridge) connected to it, which was designed specifically for
197 * the IIi. The APB lets the IIi handle two independent PCI buses, and
198 * appears as two "Simba"'s underneath the Sabre.
199 *
200 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
201 * basically the same as Sabre but without an APB underneath it.
202 *
203 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
204 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
205 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
206 * will usually find a "Psycho+" since I don't think the original "Psycho"
207 * ever shipped, and if it did it would be in the U30.
208 *
209 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
210 * both part of the same IC, they only have a single register space. As such,
211 * they need to be configured together, even though the autoconfiguration will
212 * attach them separately.
213 *
214 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
215 * as pci1 and pci2, although they have been implemented with other PCI bus
216 * numbers on some machines.
217 *
218 * On UltraII machines, there can be any number of "Psycho+" ICs, each
219 * providing two PCI buses.
220 */
221
222struct psycho_desc {
223 const char *pd_string;
224 int pd_mode;
225 const char *pd_name;
226};
227
228static const struct psycho_desc psycho_compats[] = {
229 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
230 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
231 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
232 { NULL, 0, NULL }
233};
234
235static const struct psycho_desc psycho_models[] = {
236 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
237 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
238 { NULL, 0, NULL }
239};
240
241static const struct psycho_desc *
242psycho_find_desc(const struct psycho_desc *table, const char *string)
243{
244 const struct psycho_desc *desc;
245
246 if (string == NULL)
247 return (NULL);
248 for (desc = table; desc->pd_string != NULL; desc++)
249 if (strcmp(desc->pd_string, string) == 0)
250 return (desc);
251 return (NULL);
252}
253
254static const struct psycho_desc *
255psycho_get_desc(device_t dev)
256{
257 const struct psycho_desc *rv;
258
259 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
260 if (rv == NULL)
261 rv = psycho_find_desc(psycho_compats,
262 ofw_bus_get_compat(dev));
263 return (rv);
264}
265
266static int
267psycho_probe(device_t dev)
268{
269 const char *dtype;
270
271 dtype = ofw_bus_get_type(dev);
272 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
273 psycho_get_desc(dev) != NULL) {
274 device_set_desc(dev, "U2P UPA-PCI bridge");
275 return (0);
276 }
277 return (ENXIO);
278}
279
280static int
281psycho_attach(device_t dev)
282{
283 struct psycho_icarg *pica;
284 struct psycho_softc *asc, *sc, *osc;
291 struct ofw_pci_ranges *range;
285 const struct psycho_desc *desc;
286 bus_addr_t intrclr, intrmap;
287 bus_dma_tag_t dmat;
288 uint64_t csr, dr;
289 phandle_t node;
296 uint32_t dvmabase, prop, prop_array[2];
290 uint32_t dvmabase, prop;
291 u_int rerun, ver;
292 int i, j;
293
294 node = ofw_bus_get_node(dev);
295 sc = device_get_softc(dev);
296 desc = psycho_get_desc(dev);
297
304 sc->sc_node = node;
298 sc->sc_dev = dev;
299 sc->sc_mode = desc->pd_mode;
300
301 /*
302 * The Psycho gets three register banks:
303 * (0) per-PBM configuration and status registers
304 * (1) per-PBM PCI configuration space, containing only the
305 * PBM 256-byte PCI header
306 * (2) the shared Psycho configuration registers
307 */
308 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
309 i = 2;
310 sc->sc_pcictl =
311 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
312 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
313 switch (sc->sc_pcictl) {
314 case PSR_PCICTL0:
315 sc->sc_half = 0;
316 break;
317 case PSR_PCICTL1:
318 sc->sc_half = 1;
319 break;
320 default:
321 panic("%s: bogus PCI control register location",
322 __func__);
323 /* NOTREACHED */
324 }
325 } else {
326 i = 0;
327 sc->sc_pcictl = PSR_PCICTL0;
328 sc->sc_half = 0;
329 }
330 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
331 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
332 RF_ACTIVE);
333 if (sc->sc_mem_res == NULL)
334 panic("%s: could not allocate registers", __func__);
335
336 /*
337 * Match other Psychos that are already configured against
338 * the base physical address. This will be the same for a
339 * pair of devices that share register space.
340 */
341 osc = NULL;
342 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
343 if (rman_get_start(asc->sc_mem_res) ==
344 rman_get_start(sc->sc_mem_res)) {
345 /* Found partner. */
346 osc = asc;
347 break;
348 }
349 }
350 if (osc == NULL) {
351 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
352 M_NOWAIT | M_ZERO);
353 if (sc->sc_mtx == NULL)
354 panic("%s: could not malloc mutex", __func__);
355 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
356 } else {
357 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
358 panic("%s: no partner expected", __func__);
359 if (mtx_initialized(osc->sc_mtx) == 0)
360 panic("%s: mutex not initialized", __func__);
361 sc->sc_mtx = osc->sc_mtx;
362 }
363 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
364
365 csr = PSYCHO_READ8(sc, PSR_CS);
366 ver = PSYCHO_GCSR_VERS(csr);
367 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
368 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
369 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
370 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
371 prop = 33000000;
372
373 device_printf(dev,
374 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
375 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
376 'A' + sc->sc_half, prop / 1000 / 1000);
377
378 /* Set up the PCI control and PCI diagnostic registers. */
379
380 csr = PCICTL_READ8(sc, PCR_CS);
381 csr &= ~PCICTL_ARB_PARK;
382 if (OF_getproplen(node, "no-bus-parking") < 0)
383 csr |= PCICTL_ARB_PARK;
384
385 /* Workarounds for version specific bugs. */
386 dr = PCICTL_READ8(sc, PCR_DIAG);
387 switch (ver) {
388 case 0:
389 dr |= DIAG_RTRY_DIS;
390 dr &= ~DIAG_DWSYNC_DIS;
391 rerun = 0;
392 break;
393 case 1:
394 csr &= ~PCICTL_ARB_PARK;
395 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
396 rerun = 0;
397 break;
398 default:
399 dr |= DIAG_DWSYNC_DIS;
400 dr &= ~DIAG_RTRY_DIS;
401 rerun = 1;
402 break;
403 }
404
405 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
406 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
407#ifdef PSYCHO_DEBUG
408 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
409 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
410 (unsigned long long)csr);
411#endif
412 PCICTL_WRITE8(sc, PCR_CS, csr);
413
414 dr &= ~DIAG_ISYNC_DIS;
415#ifdef PSYCHO_DEBUG
416 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
417 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
418 (unsigned long long)dr);
419#endif
420 PCICTL_WRITE8(sc, PCR_DIAG, dr);
421
422 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
423 /* Use the PROM preset for now. */
424 csr = PCICTL_READ8(sc, PCR_TAS);
425 if (csr == 0)
426 panic("%s: Hummingbird/Sabre TAS not initialized.",
427 __func__);
428 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
429 } else
430 dvmabase = -1;
431
438 /* Initialize memory and I/O rmans. */
439 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
440 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
441 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
442 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
443 panic("%s: failed to set up I/O rman", __func__);
444 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
445 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
446 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
447 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
448 panic("%s: failed to set up memory rman", __func__);
449
450 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
432 /*
452 * Make sure that the expected ranges are present. The
453 * OFW_PCI_CS_MEM64 one is not currently used though.
454 */
455 if (i != PSYCHO_NRANGE)
456 panic("%s: unsupported number of ranges", __func__);
457 /*
458 * Find the addresses of the various bus spaces.
459 * There should not be multiple ones of one kind.
460 * The physical start addresses of the ranges are the configuration,
461 * memory and I/O handles.
462 */
463 for (i = 0; i < PSYCHO_NRANGE; i++) {
464 j = OFW_PCI_RANGE_CS(&range[i]);
465 if (sc->sc_pci_bh[j] != 0)
466 panic("%s: duplicate range for space %d",
467 __func__, j);
468 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
469 }
470 free(range, M_OFWPROP);
471
472 /* Register the softc, this is needed for paired Psychos. */
473 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
474
475 /*
433 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
434 * to arrive here, do the interrupt setup and start up the IOMMU.
435 */
436 if (osc == NULL) {
437 /*
438 * Hunt through all the interrupt mapping regs and register
439 * our interrupt controller for the corresponding interrupt
440 * vectors. We do this early in order to be able to catch
441 * stray interrupts.
442 */
443 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
444 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
445 NULL) == 0)
446 continue;
447 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
448 if (pica == NULL)
449 panic("%s: could not allocate interrupt "
450 "controller argument", __func__);
451 pica->pica_sc = sc;
452 pica->pica_map = intrmap;
453 pica->pica_clr = intrclr;
454#ifdef PSYCHO_DEBUG
455 /*
456 * Enable all interrupts and clear all interrupt
457 * states. This aids the debugging of interrupt
458 * routing problems.
459 */
460 device_printf(dev,
461 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
462 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
463 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
464 intrmap), (u_long)intrclr);
465 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
466 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
467 PSYCHO_WRITE8(sc, intrmap,
468 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
469 PCPU_GET(mid)));
470#endif
471 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
472 i), &psycho_ic, pica);
473 if (j != 0)
474 device_printf(dev, "could not register "
475 "interrupt controller for INO %d (%d)\n",
476 i, j);
477 }
478
479 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
480 sparc64_counter_init(device_get_nameunit(dev),
481 rman_get_bustag(sc->sc_mem_res),
482 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
483
484 /*
485 * Set up IOMMU and PCI configuration if we're the first
486 * of a pair of Psychos to arrive here or a Hummingbird
487 * or Sabre.
488 *
489 * We should calculate a TSB size based on amount of RAM
490 * and number of bus controllers and number and type of
491 * child devices.
492 *
493 * For the moment, 32KB should be more than enough.
494 */
495 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
496 M_ZERO);
497 if (sc->sc_is == NULL)
498 panic("%s: could not malloc IOMMU state", __func__);
499 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
500 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
501 sc->sc_dma_methods =
502 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
503 M_NOWAIT);
504 if (sc->sc_dma_methods == NULL)
505 panic("%s: could not malloc DMA methods",
506 __func__);
507 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
508 sizeof(*sc->sc_dma_methods));
509 sc->sc_dma_methods->dm_dmamap_sync =
510 sabre_dmamap_sync;
511 sc->sc_is->is_pmaxaddr =
512 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
513 } else {
514 sc->sc_dma_methods = &iommu_dma_methods;
515 sc->sc_is->is_pmaxaddr =
516 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
517 }
518 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
519 if (OF_getproplen(node, "no-streaming-cache") < 0)
520 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
521 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
522 psycho_iommu_init(sc, 3, dvmabase);
523 } else {
524 /* Just copy IOMMU state, config tag and address. */
525 sc->sc_dma_methods = &iommu_dma_methods;
526 sc->sc_is = osc->sc_is;
527 if (OF_getproplen(node, "no-streaming-cache") < 0)
528 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
529 iommu_reset(sc->sc_is);
530 }
531
575 /* Allocate our tags. */
576 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
577 sc->sc_mem_res), PCI_IO_BUS_SPACE, NULL);
578 if (sc->sc_pci_iot == NULL)
579 panic("%s: could not allocate PCI I/O tag", __func__);
580 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
581 sc->sc_mem_res), PCI_CONFIG_BUS_SPACE, NULL);
582 if (sc->sc_pci_cfgt == NULL)
583 panic("%s: could not allocate PCI configuration space tag",
584 __func__);
532 /* Create our DMA tag. */
533 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
534 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
587 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
535 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
536 panic("%s: could not create PCI DMA tag", __func__);
589 /* Customize the tag. */
590 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
591 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
537 dmat->dt_cookie = sc->sc_is;
538 dmat->dt_mt = sc->sc_dma_methods;
539
593 i = OF_getprop(node, "bus-range", (void *)prop_array,
594 sizeof(prop_array));
595 if (i == -1)
596 panic("%s: could not get bus-range", __func__);
597 if (i != sizeof(prop_array))
598 panic("%s: broken bus-range (%d)", __func__, i);
599 sc->sc_pci_secbus = prop_array[0];
600 sc->sc_pci_subbus = prop_array[1];
601 if (bootverbose)
602 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
603 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
540 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
541 PSYCHO_MEM_SIZE) != 0)
542 panic("%s: ofw_pci_attach_common() failed", __func__);
543
544 /* Clear any pending PCI error bits. */
606 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
607 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
545 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
546 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
547 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
548 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
549 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
550
551 if (osc == NULL) {
552 /*
553 * Establish handlers for interesting interrupts...
554 *
555 * XXX We need to remember these and remove this to support
556 * hotplug on the UPA/FHC bus.
557 *
558 * XXX Not all controllers have these, but installing them
559 * is better than trying to sort through this mess.
560 */
561 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
562 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
563 switch (psycho_powerfail) {
564 case 0:
565 break;
566 case 2:
567 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP,
568 psycho_powerdebug, NULL);
569 break;
570 default:
571 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
572 psycho_powerdown);
573 break;
574 }
575 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
576 /*
577 * Hummingbirds/Sabres do not have the following two
578 * interrupts.
579 */
580
581 /*
582 * The spare hardware interrupt is used for the
583 * over-temperature interrupt.
584 */
585 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL,
586 psycho_overtemp);
587#ifdef PSYCHO_MAP_WAKEUP
588 /*
589 * psycho_wakeup() doesn't do anything useful right
590 * now.
591 */
592 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
593 psycho_wakeup, NULL);
594#endif /* PSYCHO_MAP_WAKEUP */
595 }
596 }
597 /*
598 * Register a PCI bus error interrupt handler according to which
599 * half this is. Hummingbird/Sabre don't have a PCI bus B error
600 * interrupt but they are also only used for PCI bus A.
601 */
602 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
603 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
604
605 /*
606 * Set the latency timer register as this isn't always done by the
607 * firmware.
608 */
670 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
609 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
610 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
611
612 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
674 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
675 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
676 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
613 le16enc(&sc->sc_pci_hpbcfg[i],
614 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
615 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
616 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
617 PCS_FUNC, i)));
618 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
679 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
680 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
681 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
619 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
620 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
621 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
622
683 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
623 /*
624 * On E250 the interrupt map entry for the EBus bridge is wrong,
625 * causing incorrect interrupts to be assigned to some devices on
626 * the EBus. Work around it by changing our copy of the interrupt
627 * map mask to perform a full comparison of the INO. That way
628 * the interrupt map entry for the EBus bridge won't match at all
629 * and the INOs specified in the "interrupts" properties of the
630 * EBus devices will be used directly instead.
631 */
632 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
694 sc->sc_pci_iinfo.opi_imapmsk != NULL)
695 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
696 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
633 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
634 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
635 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
636
637 device_add_child(dev, "pci", -1);
638 return (bus_generic_attach(dev));
639}
640
641static void
642psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
643 driver_filter_t filt, driver_intr_t intr)
644{
645 u_long vec;
646 int rid;
647
648 rid = index;
649 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
650 SYS_RES_IRQ, &rid, RF_ACTIVE);
651 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
652 /*
653 * These interrupts aren't mandatory and not available
654 * with all controllers (not even Psychos).
655 */
656 return;
657 }
658 if (sc->sc_irq_res[index] == NULL ||
659 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
660 sc->sc_ign ||
661 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
662 intr_vectors[vec].iv_ic != &psycho_ic ||
663 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
664 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
665 &sc->sc_ihand[index]) != 0)
666 panic("%s: failed to set up interrupt %d", __func__, index);
667}
668
669static int
670psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
671 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
672{
673 bus_addr_t intrclr, intrmap;
674 uint64_t diag;
675 int found;
676
677 /*
678 * XXX we only compare INOs rather than INRs since the firmware may
679 * not provide the IGN and the IGN is constant for all devices on
680 * that PCI controller.
681 * This could cause problems for the FFB/external interrupt which
682 * has a full vector that can be set arbitrarily.
683 */
684
685 if (ino > PSYCHO_MAX_INO) {
686 device_printf(sc->sc_dev, "out of range INO %d requested\n",
687 ino);
688 return (0);
689 }
690
691 found = 0;
692 /* Hunt through OBIO first. */
693 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
694 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
695 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
696 diag >>= 2) {
697 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
698 (intrmap == PSR_TIMER0_INT_MAP ||
699 intrmap == PSR_TIMER1_INT_MAP ||
700 intrmap == PSR_PCIBERR_INT_MAP ||
701 intrmap == PSR_PWRMGT_INT_MAP))
702 continue;
703 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
704 diag &= 2;
705 found = 1;
706 break;
707 }
708 }
709
710 if (!found) {
711 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
712 /* Now do PCI interrupts. */
713 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
714 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
715 diag >>= 8) {
716 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
717 (intrmap == PSR_PCIA2_INT_MAP ||
718 intrmap == PSR_PCIA3_INT_MAP))
719 continue;
720 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
721 intrclr += 8 * (ino & 3);
722 diag = (diag >> ((ino & 3) * 2)) & 2;
723 found = 1;
724 break;
725 }
726 }
727 }
728 if (intrmapptr != NULL)
729 *intrmapptr = intrmap;
730 if (intrclrptr != NULL)
731 *intrclrptr = intrclr;
732 if (intrdiagptr != NULL)
733 *intrdiagptr = diag;
734 return (found);
735}
736
737/*
738 * Interrupt handlers
739 */
740static int
741psycho_ue(void *arg)
742{
743 struct psycho_softc *sc = arg;
744 uint64_t afar, afsr;
745
746 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
747 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
748 /*
749 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
750 * the AFAR to be set to the physical address of the TTE entry that
751 * was invalid/write protected. Call into the IOMMU code to have
752 * them decoded to virtual I/O addresses.
753 */
754 if ((afsr & UEAFSR_P_DTE) != 0)
755 iommu_decode_fault(sc->sc_is, afar);
756 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
757 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
758 return (FILTER_HANDLED);
759}
760
761static int
762psycho_ce(void *arg)
763{
764 struct psycho_softc *sc = arg;
765 uint64_t afar, afsr;
766
767 mtx_lock_spin(sc->sc_mtx);
768 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
769 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
770 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
771 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
772 /* Clear the error bits that we caught. */
773 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
774 mtx_unlock_spin(sc->sc_mtx);
775 return (FILTER_HANDLED);
776}
777
778static int
779psycho_pci_bus(void *arg)
780{
781 struct psycho_softc *sc = arg;
782 uint64_t afar, afsr;
783
784 afar = PCICTL_READ8(sc, PCR_AFA);
785 afsr = PCICTL_READ8(sc, PCR_AFS);
786 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
787 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
788 (u_long)afsr);
789 return (FILTER_HANDLED);
790}
791
792static int
793psycho_powerdebug(void *arg __unused)
794{
795
796 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
797 return (FILTER_HANDLED);
798}
799
800static void
801psycho_powerdown(void *arg __unused)
802{
803 static int shutdown;
804
805 /* As the interrupt is cleared we may be called multiple times. */
806 if (shutdown != 0)
807 return;
808 shutdown++;
809 printf("Power Failure Detected: Shutting down NOW.\n");
810 shutdown_nice(RB_POWEROFF);
811}
812
813static void
814psycho_overtemp(void *arg __unused)
815{
816 static int shutdown;
817
818 /* As the interrupt is cleared we may be called multiple times. */
819 if (shutdown != 0)
820 return;
821 shutdown++;
822 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
823 shutdown_nice(RB_POWEROFF);
824}
825
826#ifdef PSYCHO_MAP_WAKEUP
827static int
828psycho_wakeup(void *arg)
829{
830 struct psycho_softc *sc = arg;
831
832 /* We don't really have a framework to deal with this properly. */
833 device_printf(sc->sc_dev, "power management wakeup\n");
834 return (FILTER_HANDLED);
835}
836#endif /* PSYCHO_MAP_WAKEUP */
837
838static void
839psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
840{
841 struct iommu_state *is = sc->sc_is;
842
843 /* Punch in our copies. */
844 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
845 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
846 is->is_iommu = PSR_IOMMU;
847 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
848 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
849 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
850 is->is_dva = PSR_IOMMU_SVADIAG;
851 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
852
853 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
854}
855
856static int
857psycho_maxslots(device_t dev)
858{
859
860 /* XXX: is this correct? */
861 return (PCI_SLOTMAX);
862}
863
864static uint32_t
865psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
866 int width)
867{
868 struct psycho_softc *sc;
930 bus_space_handle_t bh;
931 u_long offset = 0;
932 uint8_t byte;
933 uint16_t shrt;
934 uint32_t r, wrd;
935 int i;
869
870 sc = device_get_softc(dev);
938 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
939 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
940 return (-1);
941
942 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
943
871 /*
872 * The Hummingbird and Sabre bridges are picky in that they
873 * only allow their config space to be accessed using the
874 * "native" width of the respective register being accessed
875 * and return semi-random other content of their config space
876 * otherwise. Given that the PCI specs don't say anything
877 * about such a (unusual) limitation and lots of stuff expects
878 * to be able to access the contents of the config space at
879 * any width we allow just that. We do this by using a copy
880 * of the header of the bridge (the rest is all zero anyway)
881 * read during attach (expect for PCIR_STATUS) in order to
882 * simplify things.
883 * The Psycho bridges contain a dupe of their header at 0x80
884 * which we nullify that way also.
885 */
959 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
886 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
887 func == PCS_FUNC) {
961 if (offset % width != 0)
888 if (reg % width != 0)
889 return (-1);
890
891 if (reg >= sizeof(sc->sc_pci_hpbcfg))
892 return (0);
893
894 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
895 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
896 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
970 bus_space_read_2(sc->sc_pci_cfgt, bh,
971 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
897 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
898 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
899 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
900 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
901
902 switch (width) {
903 case 1:
904 return (sc->sc_pci_hpbcfg[reg]);
905 case 2:
906 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
907 case 4:
908 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
909 }
910 }
911
984 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
985 switch (width) {
986 case 1:
987 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
988 r = byte;
989 break;
990 case 2:
991 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
992 r = shrt;
993 break;
994 case 4:
995 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
996 r = wrd;
997 break;
998 default:
999 panic("%s: bad width", __func__);
1000 /* NOTREACHED */
1001 }
1002
1003 if (i) {
1004#ifdef PSYCHO_DEBUG
1005 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
1006 __func__, bus, slot, func, reg);
1007#endif
1008 r = -1;
1009 }
1010 return (r);
912 return (ofw_pci_read_config_common(dev, PCI_REGMAX,
913 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
914 width));
915}
916
917static void
918psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
919 u_int reg, uint32_t val, int width)
920{
1017 struct psycho_softc *sc;
1018 bus_space_handle_t bh;
1019 u_long offset = 0;
921
1021 sc = device_get_softc(dev);
1022 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1023 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1024 return;
1025
1026 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1027 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1028 switch (width) {
1029 case 1:
1030 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1031 break;
1032 case 2:
1033 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1034 break;
1035 case 4:
1036 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1037 break;
1038 default:
1039 panic("%s: bad width", __func__);
1040 /* NOTREACHED */
1041 }
922 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
923 slot, func, reg), bus, slot, func, reg, val, width);
924}
925
926static int
927psycho_route_interrupt(device_t bridge, device_t dev, int pin)
928{
929 struct psycho_softc *sc;
1048 struct ofw_pci_register reg;
930 bus_addr_t intrmap;
1050 ofw_pci_intr_t pintr, mintr;
931 ofw_pci_intr_t mintr;
932
1052 sc = device_get_softc(bridge);
1053 pintr = pin;
1054 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1055 &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1056 NULL))
933 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
934 if (PCI_INTERRUPT_VALID(mintr))
935 return (mintr);
936 /*
937 * If this is outside of the range for an intpin, it's likely a full
938 * INO, and no mapping is required at all; this happens on the U30,
939 * where there's no interrupt map at the Psycho node. Fortunately,
940 * there seem to be no INOs in the intpin range on this boxen, so
941 * this easy heuristics will do.
942 */
943 if (pin > 4)
944 return (pin);
945 /*
946 * Guess the INO; we always assume that this is a non-OBIO
947 * device, and that pin is a "real" intpin number. Determine
948 * the mapping register to be used by the slot number.
949 * We only need to do this on E450s, it seems; here, the slot numbers
950 * for bus A are one-based, while those for bus B seemingly have an
951 * offset of 2 (hence the factor of 3 below).
952 */
953 sc = device_get_softc(dev);
954 intrmap = PSR_PCIA0_INT_MAP +
955 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
956 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
957 device_printf(bridge,
958 "guessing interrupt %d for device %d.%d pin %d\n",
959 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
960 return (mintr);
961}
962
1084static int
1085psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1086{
1087 struct psycho_softc *sc;
1088
1089 sc = device_get_softc(dev);
1090 switch (which) {
1091 case PCIB_IVAR_DOMAIN:
1092 *result = device_get_unit(dev);
1093 return (0);
1094 case PCIB_IVAR_BUS:
1095 *result = sc->sc_pci_secbus;
1096 return (0);
1097 }
1098 return (ENOENT);
1099}
1100
963static void
964sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
965{
966 struct iommu_state *is = dt->dt_cookie;
967
968 if ((map->dm_flags & DMF_LOADED) == 0)
969 return;
970
971 if ((op & BUS_DMASYNC_POSTREAD) != 0)
972 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
973 PSR_DMA_WRITE_SYNC);
974
975 if ((op & BUS_DMASYNC_PREWRITE) != 0)
976 membar(Sync);
977}
978
979static void
980psycho_intr_enable(void *arg)
981{
982 struct intr_vector *iv = arg;
983 struct psycho_icarg *pica = iv->iv_icarg;
984
985 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
986 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
987}
988
989static void
990psycho_intr_disable(void *arg)
991{
992 struct intr_vector *iv = arg;
993 struct psycho_icarg *pica = iv->iv_icarg;
994
995 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
996}
997
998static void
999psycho_intr_assign(void *arg)
1000{
1001 struct intr_vector *iv = arg;
1002 struct psycho_icarg *pica = iv->iv_icarg;
1003
1004 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1005 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1006}
1007
1008static void
1009psycho_intr_clear(void *arg)
1010{
1011 struct intr_vector *iv = arg;
1012 struct psycho_icarg *pica = iv->iv_icarg;
1013
1014 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1015}
1016
1017static int
1018psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1019 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1020 void **cookiep)
1021{
1022 struct psycho_softc *sc;
1023 u_long vec;
1024
1025 sc = device_get_softc(dev);
1026 /*
1027 * Make sure the vector is fully specified and we registered
1028 * our interrupt controller for it.
1029 */
1030 vec = rman_get_start(ires);
1031 if (INTIGN(vec) != sc->sc_ign ||
1032 intr_vectors[vec].iv_ic != &psycho_ic) {
1033 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1034 return (EINVAL);
1035 }
1036 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1037 arg, cookiep));
1038}
1039
1040static struct resource *
1041psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1042 u_long start, u_long end, u_long count, u_int flags)
1043{
1044 struct psycho_softc *sc;
1183 struct resource *rv;
1184 struct rman *rm;
1045
1186 sc = device_get_softc(bus);
1187 switch (type) {
1188 case SYS_RES_IRQ:
1189 /*
1190 * XXX: Don't accept blank ranges for now, only single
1191 * interrupts. The other case should not happen with
1192 * the MI PCI code...
1193 * XXX: This may return a resource that is out of the
1194 * range that was specified. Is this correct...?
1195 */
1196 if (start != end)
1197 panic("%s: XXX: interrupt range", __func__);
1046 if (type == SYS_RES_IRQ) {
1047 sc = device_get_softc(bus);
1048 start = end = INTMAP_VEC(sc->sc_ign, end);
1199 return (bus_generic_alloc_resource(bus, child, type, rid,
1200 start, end, count, flags));
1201 case SYS_RES_MEMORY:
1202 rm = &sc->sc_pci_mem_rman;
1203 break;
1204 case SYS_RES_IOPORT:
1205 rm = &sc->sc_pci_io_rman;
1206 break;
1207 default:
1208 return (NULL);
1049 }
1210
1211 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
1212 child);
1213 if (rv == NULL)
1214 return (NULL);
1215 rman_set_rid(rv, *rid);
1216
1217 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
1218 *rid, rv) != 0) {
1219 rman_release_resource(rv);
1220 return (NULL);
1221 }
1222 return (rv);
1050 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1051 count, flags));
1052}
1053
1225static int
1226psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1227 struct resource *r)
1228{
1229 struct psycho_softc *sc;
1230 struct bus_space_tag *tag;
1231
1232 sc = device_get_softc(bus);
1233 switch (type) {
1234 case SYS_RES_IRQ:
1235 return (bus_generic_activate_resource(bus, child, type, rid,
1236 r));
1237 case SYS_RES_MEMORY:
1238 tag = sparc64_alloc_bus_tag(r, rman_get_bustag(
1239 sc->sc_mem_res), PCI_MEMORY_BUS_SPACE, NULL);
1240 if (tag == NULL)
1241 return (ENOMEM);
1242 rman_set_bustag(r, tag);
1243 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
1244 rman_get_start(r));
1245 break;
1246 case SYS_RES_IOPORT:
1247 rman_set_bustag(r, sc->sc_pci_iot);
1248 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
1249 rman_get_start(r));
1250 break;
1251 }
1252 return (rman_activate_resource(r));
1253}
1254
1255static int
1256psycho_adjust_resource(device_t bus, device_t child, int type,
1257 struct resource *r, u_long start, u_long end)
1258{
1259 struct psycho_softc *sc;
1260 struct rman *rm;
1261
1262 sc = device_get_softc(bus);
1263 switch (type) {
1264 case SYS_RES_IRQ:
1265 return (bus_generic_adjust_resource(bus, child, type, r,
1266 start, end));
1267 case SYS_RES_MEMORY:
1268 rm = &sc->sc_pci_mem_rman;
1269 break;
1270 case SYS_RES_IOPORT:
1271 rm = &sc->sc_pci_io_rman;
1272 break;
1273 default:
1274 return (EINVAL);
1275 }
1276 if (rman_is_region_manager(r, rm) == 0)
1277 return (EINVAL);
1278 return (rman_adjust_resource(r, start, end));
1279}
1280
1281static bus_dma_tag_t
1282psycho_get_dma_tag(device_t bus, device_t child __unused)
1283{
1284 struct psycho_softc *sc;
1285
1286 sc = device_get_softc(bus);
1287 return (sc->sc_pci_dmat);
1288}
1289
1290static phandle_t
1291psycho_get_node(device_t bus, device_t child __unused)
1292{
1293 struct psycho_softc *sc;
1294
1295 sc = device_get_softc(bus);
1296 /* We only have one child, the PCI bus, which needs our own node. */
1297 return (sc->sc_node);
1298}
1299
1054static void
1055psycho_setup_device(device_t bus, device_t child)
1056{
1057 struct psycho_softc *sc;
1058 uint32_t rev;
1059
1060 sc = device_get_softc(bus);
1061 /*
1062 * Revision 0 EBus bridges have a bug which prevents them from
1063 * working when bus parking is enabled.
1064 */
1065 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1066 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1067 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1068 sizeof(rev)) > 0 && rev == 0)
1069 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1070 ~PCICTL_ARB_PARK);
1071}