1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 17 unchanged lines hidden (view full) --- 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> |
34__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 292789 2015-12-27 19:37:47Z marius $"); |
35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" --- 9 unchanged lines hidden (view full) --- 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57#include <sys/sysctl.h> 58 59#include <dev/ofw/ofw_bus.h> |
60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/resource.h> --- 36 unchanged lines hidden (view full) --- 104/* IOMMU support */ 105static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 106 107/* 108 * Methods 109 */ 110static device_probe_t psycho_probe; 111static device_attach_t psycho_attach; |
112static bus_setup_intr_t psycho_setup_intr; 113static bus_alloc_resource_t psycho_alloc_resource; |
114static pcib_maxslots_t psycho_maxslots; 115static pcib_read_config_t psycho_read_config; 116static pcib_write_config_t psycho_write_config; 117static pcib_route_interrupt_t psycho_route_interrupt; |
118static ofw_pci_setup_device_t psycho_setup_device; 119 120static device_method_t psycho_methods[] = { 121 /* Device interface */ 122 DEVMETHOD(device_probe, psycho_probe), 123 DEVMETHOD(device_attach, psycho_attach), 124 DEVMETHOD(device_shutdown, bus_generic_shutdown), 125 DEVMETHOD(device_suspend, bus_generic_suspend), 126 DEVMETHOD(device_resume, bus_generic_resume), 127 128 /* Bus interface */ |
129 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar), |
130 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 131 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 132 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), |
133 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource), |
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), |
135 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource), |
136 DEVMETHOD(bus_release_resource, bus_generic_release_resource), |
137 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag), |
138 139 /* pcib interface */ 140 DEVMETHOD(pcib_maxslots, psycho_maxslots), 141 DEVMETHOD(pcib_read_config, psycho_read_config), 142 DEVMETHOD(pcib_write_config, psycho_write_config), 143 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 144 145 /* ofw_bus interface */ |
146 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node), |
147 148 /* ofw_pci interface */ 149 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device), 150 151 DEVMETHOD_END 152}; 153 154static devclass_t psycho_devclass; --- 122 unchanged lines hidden (view full) --- 277 return (ENXIO); 278} 279 280static int 281psycho_attach(device_t dev) 282{ 283 struct psycho_icarg *pica; 284 struct psycho_softc *asc, *sc, *osc; |
285 const struct psycho_desc *desc; 286 bus_addr_t intrclr, intrmap; |
287 bus_dma_tag_t dmat; |
288 uint64_t csr, dr; 289 phandle_t node; |
290 uint32_t dvmabase, prop; |
291 u_int rerun, ver; 292 int i, j; 293 294 node = ofw_bus_get_node(dev); 295 sc = device_get_softc(dev); 296 desc = psycho_get_desc(dev); 297 |
298 sc->sc_dev = dev; 299 sc->sc_mode = desc->pd_mode; 300 301 /* 302 * The Psycho gets three register banks: 303 * (0) per-PBM configuration and status registers 304 * (1) per-PBM PCI configuration space, containing only the 305 * PBM 256-byte PCI header --- 49 unchanged lines hidden (view full) --- 355 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 356 } else { 357 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 358 panic("%s: no partner expected", __func__); 359 if (mtx_initialized(osc->sc_mtx) == 0) 360 panic("%s: mutex not initialized", __func__); 361 sc->sc_mtx = osc->sc_mtx; 362 } |
363 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); |
364 365 csr = PSYCHO_READ8(sc, PSR_CS); 366 ver = PSYCHO_GCSR_VERS(csr); 367 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 368 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 369 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 370 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 371 prop = 33000000; --- 52 unchanged lines hidden (view full) --- 424 csr = PCICTL_READ8(sc, PCR_TAS); 425 if (csr == 0) 426 panic("%s: Hummingbird/Sabre TAS not initialized.", 427 __func__); 428 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 429 } else 430 dvmabase = -1; 431 |
432 /* |
433 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 434 * to arrive here, do the interrupt setup and start up the IOMMU. 435 */ 436 if (osc == NULL) { 437 /* 438 * Hunt through all the interrupt mapping regs and register 439 * our interrupt controller for the corresponding interrupt 440 * vectors. We do this early in order to be able to catch --- 83 unchanged lines hidden (view full) --- 524 /* Just copy IOMMU state, config tag and address. */ 525 sc->sc_dma_methods = &iommu_dma_methods; 526 sc->sc_is = osc->sc_is; 527 if (OF_getproplen(node, "no-streaming-cache") < 0) 528 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 529 iommu_reset(sc->sc_is); 530 } 531 |
532 /* Create our DMA tag. */ |
533 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 534 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, |
535 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0) |
536 panic("%s: could not create PCI DMA tag", __func__); |
537 dmat->dt_cookie = sc->sc_is; 538 dmat->dt_mt = sc->sc_dma_methods; |
539 |
540 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE, 541 PSYCHO_MEM_SIZE) != 0) 542 panic("%s: ofw_pci_attach_common() failed", __func__); |
543 544 /* Clear any pending PCI error bits. */ |
545 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 546 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus, |
547 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 548 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 549 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 550 551 if (osc == NULL) { 552 /* 553 * Establish handlers for interesting interrupts... 554 * --- 46 unchanged lines hidden (view full) --- 601 */ 602 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 603 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 604 605 /* 606 * Set the latency timer register as this isn't always done by the 607 * firmware. 608 */ |
609 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, |
610 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 611 612 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t)) |
613 le16enc(&sc->sc_pci_hpbcfg[i], 614 bus_space_read_2(sc->sc_ops.sc_pci_cfgt, 615 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], 616 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE, |
617 PCS_FUNC, i))); 618 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t)) |
619 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt, 620 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 621 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i)); |
622 |
623 /* 624 * On E250 the interrupt map entry for the EBus bridge is wrong, 625 * causing incorrect interrupts to be assigned to some devices on 626 * the EBus. Work around it by changing our copy of the interrupt 627 * map mask to perform a full comparison of the INO. That way 628 * the interrupt map entry for the EBus bridge won't match at all 629 * and the INOs specified in the "interrupts" properties of the 630 * EBus devices will be used directly instead. 631 */ 632 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && |
633 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL) 634 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[ 635 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; |
636 637 device_add_child(dev, "pci", -1); 638 return (bus_generic_attach(dev)); 639} 640 641static void 642psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 643 driver_filter_t filt, driver_intr_t intr) --- 217 unchanged lines hidden (view full) --- 861 return (PCI_SLOTMAX); 862} 863 864static uint32_t 865psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 866 int width) 867{ 868 struct psycho_softc *sc; |
869 870 sc = device_get_softc(dev); |
871 /* 872 * The Hummingbird and Sabre bridges are picky in that they 873 * only allow their config space to be accessed using the 874 * "native" width of the respective register being accessed 875 * and return semi-random other content of their config space 876 * otherwise. Given that the PCI specs don't say anything 877 * about such a (unusual) limitation and lots of stuff expects 878 * to be able to access the contents of the config space at 879 * any width we allow just that. We do this by using a copy 880 * of the header of the bridge (the rest is all zero anyway) 881 * read during attach (expect for PCIR_STATUS) in order to 882 * simplify things. 883 * The Psycho bridges contain a dupe of their header at 0x80 884 * which we nullify that way also. 885 */ |
886 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE && |
887 func == PCS_FUNC) { |
888 if (reg % width != 0) |
889 return (-1); 890 891 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 892 return (0); 893 894 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 895 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 896 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], |
897 bus_space_read_2(sc->sc_ops.sc_pci_cfgt, 898 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], 899 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, |
900 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 901 902 switch (width) { 903 case 1: 904 return (sc->sc_pci_hpbcfg[reg]); 905 case 2: 906 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 907 case 4: 908 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 909 } 910 } 911 |
912 return (ofw_pci_read_config_common(dev, PCI_REGMAX, 913 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg, 914 width)); |
915} 916 917static void 918psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 919 u_int reg, uint32_t val, int width) 920{ |
921 |
922 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus, 923 slot, func, reg), bus, slot, func, reg, val, width); |
924} 925 926static int 927psycho_route_interrupt(device_t bridge, device_t dev, int pin) 928{ 929 struct psycho_softc *sc; |
930 bus_addr_t intrmap; |
931 ofw_pci_intr_t mintr; |
932 |
933 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin); 934 if (PCI_INTERRUPT_VALID(mintr)) |
935 return (mintr); 936 /* 937 * If this is outside of the range for an intpin, it's likely a full 938 * INO, and no mapping is required at all; this happens on the U30, 939 * where there's no interrupt map at the Psycho node. Fortunately, 940 * there seem to be no INOs in the intpin range on this boxen, so 941 * this easy heuristics will do. 942 */ 943 if (pin > 4) 944 return (pin); 945 /* 946 * Guess the INO; we always assume that this is a non-OBIO 947 * device, and that pin is a "real" intpin number. Determine 948 * the mapping register to be used by the slot number. 949 * We only need to do this on E450s, it seems; here, the slot numbers 950 * for bus A are one-based, while those for bus B seemingly have an 951 * offset of 2 (hence the factor of 3 below). 952 */ |
953 sc = device_get_softc(dev); |
954 intrmap = PSR_PCIA0_INT_MAP + 955 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 956 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 957 device_printf(bridge, 958 "guessing interrupt %d for device %d.%d pin %d\n", 959 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 960 return (mintr); 961} 962 |
963static void 964sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 965{ 966 struct iommu_state *is = dt->dt_cookie; 967 968 if ((map->dm_flags & DMF_LOADED) == 0) 969 return; 970 --- 66 unchanged lines hidden (view full) --- 1037 arg, cookiep)); 1038} 1039 1040static struct resource * 1041psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1042 u_long start, u_long end, u_long count, u_int flags) 1043{ 1044 struct psycho_softc *sc; |
1045 |
1046 if (type == SYS_RES_IRQ) { 1047 sc = device_get_softc(bus); |
1048 start = end = INTMAP_VEC(sc->sc_ign, end); |
1049 } |
1050 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end, 1051 count, flags)); |
1052} 1053 |
1054static void 1055psycho_setup_device(device_t bus, device_t child) 1056{ 1057 struct psycho_softc *sc; 1058 uint32_t rev; 1059 1060 sc = device_get_softc(bus); 1061 /* 1062 * Revision 0 EBus bridges have a bug which prevents them from 1063 * working when bus parking is enabled. 1064 */ 1065 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 || 1066 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) && 1067 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev, 1068 sizeof(rev)) > 0 && rev == 0) 1069 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) & 1070 ~PCICTL_ARB_PARK); 1071} |