1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/sparc64/pci/ofw_pcibus.c 152684 2005-11-22 16:39:44Z marius $");
32
33#include "opt_ofw_pci.h"
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/libkern.h>
39#include <sys/module.h>
40#include <sys/pciio.h>
41
42#include <dev/ofw/ofw_bus.h>
43#include <dev/ofw/ofw_bus_subr.h>
44#include <dev/ofw/ofw_pci.h>
45#include <dev/ofw/openfirm.h>
46
47#include <machine/bus.h>
48#include <machine/bus_common.h>
49#include <machine/cache.h>
50#include <machine/iommureg.h>
51#include <machine/resource.h>
52
53#include <dev/pci/pcireg.h>
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pci_private.h>
56
57#include <sparc64/pci/ofw_pci.h>
58
59#include "pcib_if.h"
60#include "pci_if.h"
61
62/* Helper functions. */
63static void ofw_pcibus_setup_device(device_t, u_int, u_int, u_int);
64
65/* Methods. */
66static device_probe_t ofw_pcibus_probe;
67static device_attach_t ofw_pcibus_attach;
68static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
69static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
70
71static device_method_t ofw_pcibus_methods[] = {
72 /* Device interface */
73 DEVMETHOD(device_probe, ofw_pcibus_probe),
74 DEVMETHOD(device_attach, ofw_pcibus_attach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 DEVMETHOD(device_suspend, bus_generic_suspend),
77 DEVMETHOD(device_resume, bus_generic_resume),
78
79 /* Bus interface */
80 DEVMETHOD(bus_print_child, pci_print_child),
81 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
82 DEVMETHOD(bus_read_ivar, pci_read_ivar),
83 DEVMETHOD(bus_write_ivar, pci_write_ivar),
84 DEVMETHOD(bus_driver_added, pci_driver_added),
85 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
86 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
87
88 DEVMETHOD(bus_get_resource_list, pci_get_resource_list),
89 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
90 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
91 DEVMETHOD(bus_delete_resource, pci_delete_resource),
92 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
93 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
94 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
95 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
96 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
97 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
98
99 /* PCI interface */
100 DEVMETHOD(pci_read_config, pci_read_config_method),
101 DEVMETHOD(pci_write_config, pci_write_config_method),
102 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
103 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
104 DEVMETHOD(pci_enable_io, pci_enable_io_method),
105 DEVMETHOD(pci_disable_io, pci_disable_io_method),
106 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
107 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
108 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
109
110 /* ofw_bus interface */
111 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
112 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
113 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
114 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
115 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
116 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
117
118 { 0, 0 }
119};
120
121struct ofw_pcibus_devinfo {
122 struct pci_devinfo opd_dinfo;
123 struct ofw_bus_devinfo opd_obdinfo;
124};
125
126struct ofw_pcibus_softc {
127 phandle_t ops_node;
128};
129
130static driver_t ofw_pcibus_driver = {
131 "pci",
132 ofw_pcibus_methods,
133 sizeof(struct ofw_pcibus_softc),
134};
135
136DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0);
137MODULE_VERSION(ofw_pcibus, 1);
138MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
139
140static int
141ofw_pcibus_probe(device_t dev)
142{
143
144 if (ofw_bus_get_node(dev) == 0)
145 return (ENXIO);
146 device_set_desc(dev, "OFW PCI bus");
147
148 return (0);
149}
150
151/*
152 * Perform miscellaneous setups the firmware usually does not do for us.
153 */
154static void
155ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func)
156{
157 u_int lat, clnsz;
158
159 /*
160 * Initialize the latency timer register for busmaster devices to work
161 * properly. This is another task which the firmware does not always
162 * perform. The Min_Gnt register can be used to compute it's recommended
163 * value: it contains the desired latency in units of 1/4 us. To
164 * calculate the correct latency timer value, a bus clock of 33MHz and
165 * no wait states should be assumed.
166 */
167 lat = PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_MINGNT, 1) *
168 33 / 4;
169 if (lat != 0) {
170#ifdef OFW_PCI_DEBUG
171 device_printf(bridge, "device %d/%d/%d: latency timer %d -> "
172 "%d\n", busno, slot, func,
173 PCIB_READ_CONFIG(bridge, busno, slot, func,
174 PCIR_LATTIMER, 1), lat);
175#endif /* OFW_PCI_DEBUG */
176 PCIB_WRITE_CONFIG(bridge, busno, slot, func,
177 PCIR_LATTIMER, min(lat, 255), 1);
178 }
179
180 /*
181 * Compute a value to write into the cache line size register.
182 * The role of the streaming cache is unclear in write invalidate
183 * transfers, so it is made sure that it's line size is always reached.
184 */
185 clnsz = max(cache.ec_linesize, STRBUF_LINESZ);
186 KASSERT((clnsz / STRBUF_LINESZ) * STRBUF_LINESZ == clnsz &&
187 (clnsz / cache.ec_linesize) * cache.ec_linesize == clnsz &&
188 (clnsz / 4) * 4 == clnsz, ("bogus cache line size %d", clnsz));
189 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
190 clnsz / 4, 1);
191
192 /*
193 * The preset in the intline register is usually wrong. Reset it to 255,
194 * so that the PCI code will reroute the interrupt if needed.
195 */
196 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
197 PCI_INVALID_IRQ, 1);
198}
199
200static int
201ofw_pcibus_attach(device_t dev)
202{
203 device_t pcib = device_get_parent(dev);
204 struct ofw_pci_register pcir;
205 struct ofw_pcibus_devinfo *dinfo;
206 phandle_t node, child;
207 u_int slot, busno, func;
208
209 /*
210 * Ask the bridge for the bus number - in some cases, we need to
211 * renumber buses, so the firmware information cannot be trusted.
212 */
213 busno = pcib_get_bus(dev);
214 if (bootverbose)
215 device_printf(dev, "physical bus=%d\n", busno);
216
217 node = ofw_bus_get_node(dev);
218 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
219 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
220 continue;
221 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
222 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
223 ofw_pcibus_setup_device(pcib, busno, slot, func);
224 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
225 busno, slot, func, sizeof(*dinfo));
226 if (dinfo == NULL)
227 continue;
228 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
229 0) {
230 pci_freecfg((struct pci_devinfo *)dinfo);
231 continue;
232 }
233 pci_add_child(dev, (struct pci_devinfo *)dinfo);
234 }
235
236 return (bus_generic_attach(dev));
237}
238
239static int
240ofw_pcibus_assign_interrupt(device_t dev, device_t child)
241{
242 ofw_pci_intr_t intr;
243 int isz;
244
245 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
246 sizeof(intr));
247 if (isz != sizeof(intr)) {
248 /* No property; our best guess is the intpin. */
249 intr = pci_get_intpin(child);
250 } else if (intr >= 255) {
251 /*
252 * A fully specified interrupt (including IGN), as present on
253 * SPARCengine Ultra AX and e450. Extract the INO and return it.
254 */
255 return (INTINO(intr));
256 }
257 /*
258 * If we got intr from a property, it may or may not be an intpin.
259 * For on-board devices, it frequently is not, and is completely out
260 * of the valid intpin range. For PCI slots, it hopefully is, otherwise
261 * we will have trouble interfacing with non-OFW buses such as cardbus.
262 * Since we cannot tell which it is without violating layering, we
263 * will always use the route_interrupt method, and treat exceptions on
264 * the level they become apparent.
265 */
266 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
267}
268
269static const struct ofw_bus_devinfo *
270ofw_pcibus_get_devinfo(device_t bus, device_t dev)
271{
272 struct ofw_pcibus_devinfo *dinfo;
273
274 dinfo = device_get_ivars(dev);
275 return (&dinfo->opd_obdinfo);
276}