1/*-
2 * Copyright (c) 2009 Marius Strobl <marius@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
33#define FIRE_NREG 2
34
35#define FIRE_PCI 0
36#define FIRE_CTRL 1
37
38/* PCI configuration and status registers */
39#define FO_PCI_INT_MAP_BASE 0x01000
40#define FO_PCI_INT_CLR_BASE 0x01400
41#define FO_PCI_EQ_BASE_ADDR 0x10000
42#define FO_PCI_EQ_CTRL_SET_BASE 0x11000
43#define FO_PCI_EQ_CTRL_CLR_BASE 0x11200
44#define FO_PCI_EQ_TL_BASE 0x11600
45#define FO_PCI_EQ_HD_BASE 0x11800
46#define FO_PCI_MSI_MAP_BASE 0x20000
47#define FO_PCI_MSI_CLR_BASE 0x28000
48#define FO_PCI_ERR_COR 0x30000
49#define FO_PCI_ERR_NONFATAL 0x30008
50#define FO_PCI_ERR_FATAL 0x30010
51#define FO_PCI_PM_PME 0x30018
52#define FO_PCI_PME_TO_ACK 0x30020
53#define FO_PCI_IMU_INT_EN 0x31008
54#define FO_PCI_IMU_INT_STAT 0x31010
55#define FO_PCI_IMU_ERR_STAT_CLR 0x31018
56#define FO_PCI_IMU_RDS_ERR_LOG 0x31028
57#define FO_PCI_IMU_SCS_ERR_LOG 0x31030
58#define FO_PCI_IMU_EQS_ERR_LOG 0x31038
59#define FO_PCI_DMC_CORE_BLOCK_INT_EN 0x31800
60#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT 0x31808
61#define FO_PCI_MULTI_CORE_ERR_STAT 0x31810
62#define FO_PCI_MSI_32_BIT_ADDR 0x34000
63#define FO_PCI_MSI_64_BIT_ADDR 0x34008
64#define FO_PCI_MMU 0x40000
65#define FO_PCI_MMU_INT_EN 0x41008
66#define FO_PCI_MMU_INT_STAT 0x41010
67#define FO_PCI_MMU_ERR_STAT_CLR 0x41018
68#define FO_PCI_MMU_TRANS_FAULT_ADDR 0x41028
69#define FO_PCI_MMU_TRANS_FAULT_STAT 0x41030
70#define FO_PCI_ILU_INT_EN 0x51008
71#define FO_PCI_ILU_INT_STAT 0x51010
72#define FO_PCI_ILU_ERR_STAT_CLR 0x51018
73#define FO_PCI_DMC_DBG_SEL_PORTA 0x53000
74#define FO_PCI_DMC_DBG_SEL_PORTB 0x53008
75#define FO_PCI_PEC_CORE_BLOCK_INT_EN 0x51800
76#define FO_PCI_PEC_CORE_BLOCK_INT_STAT 0x51808
77#define FO_PCI_TLU_CTRL 0x80000
78#define FO_PCI_TLU_OEVENT_INT_EN 0x81008
79#define FO_PCI_TLU_OEVENT_INT_STAT 0x81010
80#define FO_PCI_TLU_OEVENT_STAT_CLR 0x81018
81#define FO_PCI_TLU_RX_OEVENT_HDR1_LOG 0x81028
82#define FO_PCI_TLU_RX_OEVENT_HDR2_LOG 0x81030
83#define FO_PCI_TLU_TX_OEVENT_HDR1_LOG 0x81038
84#define FO_PCI_TLU_TX_OEVENT_HDR2_LOG 0x81040
85#define FO_PCI_TLU_DEV_CTRL 0x90008
86#define FO_PCI_TLU_LNK_CTRL 0x90020
87#define FO_PCI_TLU_LNK_STAT 0x90028
88#define FO_PCI_TLU_UERR_INT_EN 0x91008
89#define FO_PCI_TLU_UERR_INT_STAT 0x91010
90#define FO_PCI_TLU_UERR_STAT_CLR 0x91018
91#define FO_PCI_TLU_RX_UERR_HDR1_LOG 0x91028
92#define FO_PCI_TLU_RX_UERR_HDR2_LOG 0x91030
93#define FO_PCI_TLU_TX_UERR_HDR1_LOG 0x91038
94#define FO_PCI_TLU_TX_UERR_HDR2_LOG 0x91040
95#define FO_PCI_TLU_CERR_INT_EN 0xa1008
96#define FO_PCI_TLU_CERR_INT_STAT 0xa1010
97#define FO_PCI_TLU_CERR_STAT_CLR 0xa1018
98#define FO_PCI_LPU_RST 0xe2008
99#define FO_PCI_LPU_INT_STAT 0xe2040
100#define FO_PCI_LPU_INT_MASK 0xe0248
101#define FO_PCI_LPU_LNK_LYR_CFG 0xe2200
102#define FO_PCI_LPU_LNK_LYR_INT_STAT 0xe2210
103#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL 0xe2240
104#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS 0xe2400
105#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS 0xe2410
106#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR 0xe2430
107#define FO_PCI_LPU_PHY_LYR_INT_STAT 0xe2610
108#define FO_PCI_LPU_LTSSM_CFG2 0xe2788
109#define FO_PCI_LPU_LTSSM_CFG3 0xe2790
110#define FO_PCI_LPU_LTSSM_CFG4 0xe2798
111#define FO_PCI_LPU_LTSSM_CFG5 0xe27a0
112
113/* PCI interrupt mapping registers */
114#define FO_PCI_IMAP_MDO_MODE 0x8000000000000000ULL
115#define FO_PCI_IMAP_V 0x0000000080000000ULL
116#define FIRE_PCI_IMAP_T_JPID_MASK 0x000000007c000000ULL
117#define FIRE_PCI_IMAP_T_JPID_SHFT 26
118#define OBERON_PCI_IMAP_T_DESTID_MASK 0x000000007fe00000ULL
119#define OBERON_PCI_IMAP_T_DESTID_SHFT 21
120#define FO_PCI_IMAP_INT_CTRL_NUM_MASK 0x00000000000003c0ULL
121#define FO_PCI_IMAP_INT_CTRL_NUM_SHFT 6
122
123/* PCI interrupt clear registers - use INTCLR_* from <machine/bus_common.h> */
124
125/* PCI event queue base address register */
126#define FO_PCI_EQ_BASE_ADDR_BYPASS 0xfffc000000000000ULL
127#define FO_PCI_EQ_BASE_ADDR_MASK 0xfffffffffff80000ULL
128#define FO_PCI_EQ_BASE_ADDR_SHFT 19
129
130/* PCI event queue control set registers */
131#define FO_PCI_EQ_CTRL_SET_ENOVERR 0x0200000000000000ULL
132#define FO_PCI_EQ_CTRL_SET_EN 0x0000100000000000ULL
133
134/* PCI event queue control clear registers */
135#define FO_PCI_EQ_CTRL_CLR_COVERR 0x0200000000000000ULL
136#define FO_PCI_EQ_CTRL_CLR_E2I 0x0000800000000000ULL
137#define FO_PCI_EQ_CTRL_CLR_DIS 0x0000100000000000ULL
138
139/* PCI event queue tail registers */
140#define FO_PCI_EQ_TL_OVERR 0x0200000000000000ULL
141#define FO_PCI_EQ_TL_MASK 0x000000000000007fULL
142#define FO_PCI_EQ_TL_SHFT 0
143
144/* PCI event queue head registers */
145#define FO_PCI_EQ_HD_MASK 0x000000000000007fULL
146#define FO_PCI_EQ_HD_SHFT 0
147
148/* PCI MSI mapping registers */
149#define FO_PCI_MSI_MAP_V 0x8000000000000000ULL
150#define FO_PCI_MSI_MAP_EQWR_N 0x4000000000000000ULL
151#define FO_PCI_MSI_MAP_EQNUM_MASK 0x000000000000003fULL
152#define FO_PCI_MSI_MAP_EQNUM_SHFT 0
153
154/* PCI MSI clear registers */
155#define FO_PCI_MSI_CLR_EQWR_N 0x4000000000000000ULL
156
157/*
158 * PCI IMU interrupt enable, interrupt status and error status clear
159 * registers
160 */
161#define FO_PCI_IMU_ERR_INT_SPARE_S_MASK 0x00007c0000000000ULL
162#define FO_PCI_IMU_ERR_INT_SPARE_S_SHFT 42
163#define FO_PCI_IMU_ERR_INT_EQ_OVER_S 0x0000020000000000ULL
164#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_S 0x0000010000000000ULL
165#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_S 0x0000008000000000ULL
166#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_S 0x0000004000000000ULL
167#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_S 0x0000002000000000ULL
168#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_S 0x0000001000000000ULL
169#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_S 0x0000000800000000ULL
170#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_S 0x0000000400000000ULL
171#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_S 0x0000000200000000ULL
172#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_S 0x0000000100000000ULL
173#define FO_PCI_IMU_ERR_INT_SPARE_P_MASK 0x0000000000007c00ULL
174#define FO_PCI_IMU_ERR_INT_SPARE_P_SHFT 10
175#define FO_PCI_IMU_ERR_INT_EQ_OVER_P 0x0000000000000200ULL
176#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_P 0x0000000000000100ULL
177#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_P 0x0000000000000080ULL
178#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_P 0x0000000000000040ULL
179#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_P 0x0000000000000020ULL
180#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_P 0x0000000000000010ULL
181#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_P 0x0000000000000008ULL
182#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_P 0x0000000000000004ULL
183#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_P 0x0000000000000002ULL
184#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_P 0x0000000000000001ULL
185
186/* PCI IMU RDS error log register */
187#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL
188#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_SHFT 58
189#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL
190#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_SHFT 48
191#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL
192#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_SHFT 32
193#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL
194#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_SHFT 24
195#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_MASK 0x0000000000ff0000ULL
196#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_SHFT 16
197#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_MASK 0x000000000000ffffULL
198#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_SHFT 0
199
200/* PCI IMU SCS error log register */
201#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL
202#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_SHFT 58
203#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL
204#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_SHFT 48
205#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL
206#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_SHFT 32
207#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL
208#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_SHFT 24
209#define FO_PCI_IMU_SCS_ERR_LOG_BE_MODE_MASK 0x0000000000ff0000ULL
210#define FO_PCI_IMU_SCS_ERR_LOG_BE_MCODE_SHFT 16
211#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL
212#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_SHFT 0
213
214/* PCI IMU EQS error log register */
215#define FO_PCI_IMU_EQS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL
216#define FO_PCI_IMU_EQS_ERROR_LOG_EQ_NUM_SHFT 0
217
218/*
219 * PCI ERR COR, ERR NONFATAL, ERR FATAL, PM PME and PME To ACK mapping
220 * registers
221 */
222#define FO_PCI_ERR_PME_V 0x8000000000000000ULL
223#define FO_PCI_ERR_PME_EQNUM_MASK 0x000000000000003fULL
224#define FO_PCI_ERR_PME_EQNUM_SHFT 0
225
226/* PCI DMC core and block interrupt enable register */
227#define FO_PCI_DMC_CORE_BLOCK_INT_EN_DMC 0x8000000000000000ULL
228#define FO_PCI_DMC_CORE_BLOCK_INT_EN_MMU 0x0000000000000002ULL
229#define FO_PCI_DMC_CORE_BLOCK_INT_EN_IMU 0x0000000000000001ULL
230
231/* PCI DMC core and block error status register */
232#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_MMU 0x0000000000000002ULL
233#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_IMU 0x0000000000000001ULL
234
235/* PCI multi core error status register */
236#define FO_PCI_MULTI_CORE_ERR_STAT_PEC 0x0000000000000002ULL
237#define FO_PCI_MULTI_CORE_ERR_STAT_DMC 0x0000000000000001ULL
238
239/* PCI MSI 32-bit address register */
240#define FO_PCI_MSI_32_BIT_ADDR_MASK 0x00000000ffff0000ULL
241#define FO_PCI_MSI_32_BIT_ADDR_SHFT 16
242
243/* PCI MSI 64-bit address register */
244#define FO_PCI_MSI_64_BIT_ADDR_MASK 0x0000ffffffff0000ULL
245#define FO_PCI_MSI_64_BIT_ADDR_SHFT 16
246
247/*
248 * PCI MMU interrupt enable, interrupt status and error status clear
249 * registers
250 */
251#define FO_PCI_MMU_ERR_INT_S_MASK 0x0000ffff00000000ULL
252#define FO_PCI_MMU_ERR_INT_S_SHFT 32
253#define FO_PCI_MMU_ERR_INT_TBW_DPE_S 0x0000800000000000ULL
254#define FO_PCI_MMU_ERR_INT_TBW_ERR_S 0x0000400000000000ULL
255#define FO_PCI_MMU_ERR_INT_TBW_UDE_S 0x0000200000000000ULL
256#define FO_PCI_MMU_ERR_INT_TBW_DME_S 0x0000100000000000ULL
257#define FO_PCI_MMU_ERR_INT_SPARE3_S 0x0000080000000000ULL
258#define FO_PCI_MMU_ERR_INT_SPARE2_S 0x0000040000000000ULL
259#define FO_PCI_MMU_ERR_INT_TTC_CAE_S 0x0000020000000000ULL
260#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_S 0x0000010000000000ULL
261#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_S 0x0000010000000000ULL
262#define FO_PCI_MMU_ERR_INT_TTE_PRT_S 0x0000008000000000ULL
263#define FO_PCI_MMU_ERR_INT_TTE_INV_S 0x0000004000000000ULL
264#define FO_PCI_MMU_ERR_INT_TRN_OOR_S 0x0000002000000000ULL
265#define FO_PCI_MMU_ERR_INT_TRN_ERR_S 0x0000001000000000ULL
266#define FO_PCI_MMU_ERR_INT_SPARE1_S 0x0000000800000000ULL
267#define FO_PCI_MMU_ERR_INT_SPARE0_S 0x0000000400000000ULL
268#define FO_PCI_MMU_ERR_INT_BYP_OOR_S 0x0000000200000000ULL
269#define FO_PCI_MMU_ERR_INT_BYP_ERR_S 0x0000000100000000ULL
270#define FO_PCI_MMU_ERR_INT_P_MASK 0x000000000000ffffULL
271#define FO_PCI_MMU_ERR_INT_P_SHFT 0
272#define FO_PCI_MMU_ERR_INT_TBW_DPE_P 0x0000000000008000ULL
273#define FO_PCI_MMU_ERR_INT_TBW_ERR_P 0x0000000000004000ULL
274#define FO_PCI_MMU_ERR_INT_TBW_UDE_P 0x0000000000002000ULL
275#define FO_PCI_MMU_ERR_INT_TBW_DME_P 0x0000000000001000ULL
276#define FO_PCI_MMU_ERR_INT_SPARE3_P 0x0000000000000800ULL
277#define FO_PCI_MMU_ERR_INT_SPARE2_P 0x0000000000000400ULL
278#define FO_PCI_MMU_ERR_INT_TTC_CAE_P 0x0000000000000200ULL
279#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_P 0x0000000000000100ULL
280#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_P 0x0000000000000100ULL
281#define FO_PCI_MMU_ERR_INT_TTE_PRT_P 0x0000000000000080ULL
282#define FO_PCI_MMU_ERR_INT_TTE_INV_P 0x0000000000000040ULL
283#define FO_PCI_MMU_ERR_INT_TRN_OOR_P 0x0000000000000020ULL
284#define FO_PCI_MMU_ERR_INT_TRN_ERR_P 0x0000000000000010ULL
285#define FO_PCI_MMU_ERR_INT_SPARE1_P 0x0000000000000008ULL
286#define FO_PCI_MMU_ERR_INT_SPARE0_P 0x0000000000000004ULL
287#define FO_PCI_MMU_ERR_INT_BYP_OOR_P 0x0000000000000002ULL
288#define FO_PCI_MMU_ERR_INT_BYP_ERR_P 0x0000000000000001ULL
289
290/* PCI MMU translation fault address register */
291#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_MASK 0xfffffffffffffffcULL
292#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_SHFT 2
293
294/* PCI MMU translation fault status register */
295#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_MASK 0x000001ff00000000ULL
296#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_SHFT 32
297#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_MASK 0x00000000007f0000ULL
298#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_SHFT 16
299#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_MASK 0x000000000000ffffULL
300#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_SHFT 0
301
302/*
303 * PCI ILU interrupt enable, interrupt status and error status clear
304 * registers
305 */
306#define FO_PCI_ILU_ERR_INT_SPARE3_S 0x0000008000000000ULL
307#define FO_PCI_ILU_ERR_INT_SPARE2_S 0x0000004000000000ULL
308#define FO_PCI_ILU_ERR_INT_SPARE1_S 0x0000002000000000ULL
309#define FIRE_PCI_ILU_ERR_INT_IHB_PE_S 0x0000001000000000ULL
310#define OBERON_PCI_ILU_ERR_INT_IHB_UE_S 0x0000001000000000ULL
311#define FO_PCI_ILU_ERR_INT_SPARE3_P 0x0000000000000080ULL
312#define FO_PCI_ILU_ERR_INT_SPARE2_P 0x0000000000000040ULL
313#define FO_PCI_ILU_ERR_INT_SPARE1_P 0x0000000000000020ULL
314#define FIRE_PCI_ILU_ERR_INT_IHB_PE_P 0x0000000000000010ULL
315#define OBERON_PCI_ILU_ERR_INT_IHB_UE_P 0x0000000000000010ULL
316
317/* PCI DMC debug select registers for port a/b */
318#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_MASK 0x00000000000003c0ULL
319#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_SHFT 6
320#define FO_PCI_DMC_DBG_SEL_PORT_SUB_MASK 0x0000000000000038ULL
321#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SHFT 3
322#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_MASK 0x0000000000000007ULL
323#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_SHFT 0
324
325/* PCI PEC core and block interrupt enable register */
326#define FO_PCI_PEC_CORE_BLOCK_INT_EN_PEC 0x8000000000000000ULL
327#define FO_PCI_PEC_CORE_BLOCK_INT_EN_ILU 0x0000000000000008ULL
328#define FO_PCI_PEC_CORE_BLOCK_INT_EN_UERR 0x0000000000000004ULL
329#define FO_PCI_PEC_CORE_BLOCK_INT_EN_CERR 0x0000000000000002ULL
330#define FO_PCI_PEC_CORE_BLOCK_INT_EN_OEVENT 0x0000000000000001ULL
331
332/* PCI PEC core and block interrupt status register */
333#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_ILU 0x0000000000000008ULL
334#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_UERR 0x0000000000000004ULL
335#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_CERR 0x0000000000000002ULL
336#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_OEVENT 0x0000000000000001ULL
337
338/* PCI TLU control register */
339#define FO_PCI_TLU_CTRL_L0S_TIM_MASK 0x00000000ff000000ULL
340#define FO_PCI_TLU_CTRL_L0S_TIM_SHFT 24
341#define FO_PCI_TLU_CTRL_NWPR_EN 0x0000000000100000ULL
342#define FO_PCI_TLU_CTRL_CTO_SEL_MASK 0x0000000000070000ULL
343#define FO_PCI_TLU_CTRL_CTO_SEL_SHFT 16
344#define FO_PCI_TLU_CTRL_CFG_MASK 0x000000000000ffffULL
345#define FO_PCI_TLU_CTRL_CFG_SHFT 0
346#define FO_PCI_TLU_CTRL_CFG_REMAIN_DETECT_QUIET 0x0000000000000100ULL
347#define FO_PCI_TLU_CTRL_CFG_PAD_LOOPBACK_EN 0x0000000000000080ULL
348#define FO_PCI_TLU_CTRL_CFG_EWRAP_LOOPBACK_EN 0x0000000000000040ULL
349#define FO_PCI_TLU_CTRL_CFG_DIGITAL_LOOPBACK_EN 0x0000000000000020ULL
350#define FO_PCI_TLU_CTRL_CFG_MPS_MASK 0x000000000000001cULL
351#define FO_PCI_TLU_CTRL_CFG_MPS_SHFT 2
352#define FO_PCI_TLU_CTRL_CFG_COMMON_CLK_CFG 0x0000000000000002ULL
353#define FO_PCI_TLU_CTRL_CFG_PORT 0x0000000000000001ULL
354
355/*
356 * PCI TLU other event interrupt enable, interrupt status and status clear
357 * registers
358 */
359#define FO_PCI_TLU_OEVENT_S_MASK 0x00ffffff00000000ULL
360#define FO_PCI_TLU_OEVENT_S_SHFT 32
361#define FO_PCI_TLU_OEVENT_SPARE_S 0x0080000000000000ULL
362#define FO_PCI_TLU_OEVENT_MFC_S 0x0040000000000000ULL
363#define FO_PCI_TLU_OEVENT_CTO_S 0x0020000000000000ULL
364#define FO_PCI_TLU_OEVENT_NFP_S 0x0010000000000000ULL
365#define FO_PCI_TLU_OEVENT_LWC_S 0x0008000000000000ULL
366#define FO_PCI_TLU_OEVENT_MRC_S 0x0004000000000000ULL
367#define FO_PCI_TLU_OEVENT_WUC_S 0x0002000000000000ULL
368#define FO_PCI_TLU_OEVENT_RUC_S 0x0001000000000000ULL
369#define FO_PCI_TLU_OEVENT_CRS_S 0x0000800000000000ULL
370#define FO_PCI_TLU_OEVENT_IIP_S 0x0000400000000000ULL
371#define FO_PCI_TLU_OEVENT_EDP_S 0x0000200000000000ULL
372#define FIRE_PCI_TLU_OEVENT_EHP_S 0x0000100000000000ULL
373#define OBERON_PCI_TLU_OEVENT_EHBUE_S 0x0000100000000000ULL
374#define OBERON_PCI_TLU_OEVENT_EDBUE_S 0x0000100000000000ULL
375#define FO_PCI_TLU_OEVENT_LIN_S 0x0000080000000000ULL
376#define FO_PCI_TLU_OEVENT_LRS_S 0x0000040000000000ULL
377#define FO_PCI_TLU_OEVENT_LDN_S 0x0000020000000000ULL
378#define FO_PCI_TLU_OEVENT_LUP_S 0x0000010000000000ULL
379#define FO_PCI_TLU_OEVENT_LPU_S_MASK 0x000000c000000000ULL
380#define FO_PCI_TLU_OEVENT_LPU_S_SHFT 38
381#define OBERON_PCI_TLU_OEVENT_TLUEITMO_S 0x0000008000000000ULL
382#define FO_PCI_TLU_OEVENT_ERU_S 0x0000002000000000ULL
383#define FO_PCI_TLU_OEVENT_ERO_S 0x0000001000000000ULL
384#define FO_PCI_TLU_OEVENT_EMP_S 0x0000000800000000ULL
385#define FO_PCI_TLU_OEVENT_EPE_S 0x0000000400000000ULL
386#define FIRE_PCI_TLU_OEVENT_ERP_S 0x0000000200000000ULL
387#define OBERON_PCI_TLU_OEVENT_ERBU_S 0x0000000200000000ULL
388#define FIRE_PCI_TLU_OEVENT_EIP_S 0x0000000100000000ULL
389#define OBERON_PCI_TLU_OEVENT_EIUE_S 0x0000000100000000ULL
390#define FO_PCI_TLU_OEVENT_P_MASK 0x0000000000ffffffULL
391#define FO_PCI_TLU_OEVENT_P_SHFT 0
392#define FO_PCI_TLU_OEVENT_SPARE_P 0x0000000000800000ULL
393#define FO_PCI_TLU_OEVENT_MFC_P 0x0000000000400000ULL
394#define FO_PCI_TLU_OEVENT_CTO_P 0x0000000000200000ULL
395#define FO_PCI_TLU_OEVENT_NFP_P 0x0000000000100000ULL
396#define FO_PCI_TLU_OEVENT_LWC_P 0x0000000000080000ULL
397#define FO_PCI_TLU_OEVENT_MRC_P 0x0000000000040000ULL
398#define FO_PCI_TLU_OEVENT_WUC_P 0x0000000000020000ULL
399#define FO_PCI_TLU_OEVENT_RUC_P 0x0000000000010000ULL
400#define FO_PCI_TLU_OEVENT_CRS_P 0x0000000000008000ULL
401#define FO_PCI_TLU_OEVENT_IIP_P 0x0000000000004000ULL
402#define FO_PCI_TLU_OEVENT_EDP_P 0x0000000000002000ULL
403#define FIRE_PCI_TLU_OEVENT_EHP_P 0x0000000000001000ULL
404#define OBERON_PCI_TLU_OEVENT_EHBUE_P 0x0000000000001000ULL
405#define OBERON_PCI_TLU_OEVENT_EDBUE_P 0x0000000000001000ULL
406#define FO_PCI_TLU_OEVENT_LIN_P 0x0000000000000800ULL
407#define FO_PCI_TLU_OEVENT_LRS_P 0x0000000000000400ULL
408#define FO_PCI_TLU_OEVENT_LDN_P 0x0000000000000200ULL
409#define FO_PCI_TLU_OEVENT_LUP_P 0x0000000000000100ULL
410#define FO_PCI_TLU_OEVENT_LPU_P_MASK 0x00000000000000c0ULL
411#define FO_PCI_TLU_OEVENT_LPU_P_SHFT 6
412#define OBERON_PCI_TLU_OEVENT_TLUEITMO_P 0x0000000000000080ULL
413#define FO_PCI_TLU_OEVENT_ERU_P 0x0000000000000020ULL
414#define FO_PCI_TLU_OEVENT_ERO_P 0x0000000000000010ULL
415#define FO_PCI_TLU_OEVENT_EMP_P 0x0000000000000008ULL
416#define FO_PCI_TLU_OEVENT_EPE_P 0x0000000000000004ULL
417#define FIRE_PCI_TLU_OEVENT_ERP_P 0x0000000000000002ULL
418#define OBERON_PCI_TLU_OEVENT_ERBU_P 0x0000000000000002ULL
419#define FIRE_PCI_TLU_OEVENT_EIP_P 0x0000000000000001ULL
420#define OBERON_PCI_TLU_OEVENT_EIUE_P 0x0000000000000001ULL
421
422/* PCI receive/transmit DLU/TLU other event header 1/2 log registers */
423#define FO_PCI_TLU_OEVENT_HDR_LOG_MASK 0xffffffffffffffffULL
424#define FO_PCI_TLU_OEVENT_HDR_LOG_SHFT 0
425
426/* PCI TLU device control register */
427#define FO_PCI_TLU_DEV_CTRL_MRRS_MASK 0x0000000000007000ULL
428#define FO_PCI_TLU_DEV_CTRL_MRRS_SHFT 12
429#define FO_PCI_TLU_DEV_CTRL_MPS_MASK 0x00000000000000e0ULL
430#define FO_PCI_TLU_DEV_CTRL_MPS_SHFT 5
431
432/*
433 * PCI TLU uncorrectable error interrupt enable, interrupt status and
434 * status clear registers
435 */
436#define FO_PCI_TLU_UERR_INT_S_MASK 0x001fffff00000000ULL
437#define FO_PCI_TLU_UERR_INT_S_SHFT 32
438#define FO_PCI_TLU_UERR_INT_UR_S 0x0010000000000000ULL
439#define OBERON_PCI_TLU_UERR_INT_ECRC_S 0x0008000000000000ULL
440#define FO_PCI_TLU_UERR_INT_MFP_S 0x0004000000000000ULL
441#define FO_PCI_TLU_UERR_INT_ROF_S 0x0002000000000000ULL
442#define FO_PCI_TLU_UERR_INT_UC_S 0x0001000000000000ULL
443#define FO_PCI_TLU_UERR_INT_CA_S 0x0000800000000000ULL
444#define FO_PCI_TLU_UERR_INT_CTO_S 0x0000400000000000ULL
445#define FO_PCI_TLU_UERR_INT_FCP_S 0x0000200000000000ULL
446#define FIRE_PCI_TLU_UERR_INT_PP_S 0x0000100000000000ULL
447#define OBERON_PCI_TLU_UERR_INT_POIS_S 0x0000100000000000ULL
448#define FO_PCI_TLU_UERR_INT_DLP_S 0x0000001000000000ULL
449#define FO_PCI_TLU_UERR_INT_TE_S 0x0000000100000000ULL
450#define FO_PCI_TLU_UERR_INT_P_MASK 0x00000000001fffffULL
451#define FO_PCI_TLU_UERR_INT_P_SHFT 0
452#define FO_PCI_TLU_UERR_INT_UR_P 0x0000000000100000ULL
453#define OBERON_PCI_TLU_UERR_INT_ECRC_P 0x0000000000080000ULL
454#define FO_PCI_TLU_UERR_INT_MFP_P 0x0000000000040000ULL
455#define FO_PCI_TLU_UERR_INT_ROF_P 0x0000000000020000ULL
456#define FO_PCI_TLU_UERR_INT_UC_P 0x0000000000010000ULL
457#define FO_PCI_TLU_UERR_INT_CA_P 0x0000000000008000ULL
458#define FO_PCI_TLU_UERR_INT_CTO_P 0x0000000000004000ULL
459#define FO_PCI_TLU_UERR_INT_FCP_P 0x0000000000002000ULL
460#define FIRE_PCI_TLU_UERR_INT_PP_P 0x0000000000001000ULL
461#define OBERON_PCI_TLU_UERR_INT_POIS_P 0x0000000000001000ULL
462#define FO_PCI_TLU_UERR_INT_DLP_P 0x0000000000000010ULL
463#define FO_PCI_TLU_UERR_INT_TE_P 0x0000000000000001ULL
464
465/*
466 * PCI TLU correctable error interrupt enable, interrupt status and
467 * status clear registers
468 */
469#define FO_PCI_TLU_CERR_INT_S_MASK 0x001fffff00000000ULL
470#define FO_PCI_TLU_CERR_INT_S_SHFT 32
471#define FO_PCI_TLU_CERR_INT_RTO_S 0x0000100000000000ULL
472#define FO_PCI_TLU_CERR_INT_RNR_S 0x0000010000000000ULL
473#define FO_PCI_TLU_CERR_INT_BDP_S 0x0000008000000000ULL
474#define FO_PCI_TLU_CERR_INT_BTP_S 0x0000004000000000ULL
475#define FO_PCI_TLU_CERR_INT_RE_S 0x0000000100000000ULL
476#define FO_PCI_TLU_CERR_INT_P_MASK 0x00000000001fffffULL
477#define FO_PCI_TLU_CERR_INT_P_SHFT 0
478#define FO_PCI_TLU_CERR_INT_RTO_P 0x0000000000001000ULL
479#define FO_PCI_TLU_CERR_INT_RNR_P 0x0000000000000100ULL
480#define FO_PCI_TLU_CERR_INT_BDP_P 0x0000000000000080ULL
481#define FO_PCI_TLU_CERR_INT_BTP_P 0x0000000000000040ULL
482#define FO_PCI_TLU_CERR_INT_RE_P 0x0000000000000001ULL
483
484/* PCI TLU reset register */
485#define FO_PCI_LPU_RST_WE 0x0000000080000000ULL
486#define FO_PCI_LPU_RST_UNUSED_MASK 0x0000000000000e00ULL
487#define FO_PCI_LPU_RST_UNUSED_SHFT 9
488#define FO_PCI_LPU_RST_ERR 0x0000000000000100ULL
489#define FO_PCI_LPU_RST_TXLINK 0x0000000000000080ULL
490#define FO_PCI_LPU_RST_RXLINK 0x0000000000000040ULL
491#define FO_PCI_LPU_RST_SMLINK 0x0000000000000020ULL
492#define FO_PCI_LPU_RST_LTSSM 0x0000000000000010ULL
493#define FO_PCI_LPU_RST_TXPHY 0x0000000000000008ULL
494#define FO_PCI_LPU_RST_RXPHY 0x0000000000000004ULL
495#define FO_PCI_LPU_RST_TXPCS 0x0000000000000002ULL
496#define FO_PCI_LPU_RST_RXPCS 0x0000000000000001ULL
497
498/* PCI TLU link control register */
499#define FO_PCI_TLU_LNK_CTRL_EXTSYNC 0x0000000000000080ULL
500#define FO_PCI_TLU_LNK_CTRL_CLK 0x0000000000000040ULL
501#define FO_PCI_TLU_LNK_CTRL_RETRAIN 0x0000000000000020ULL
502#define FO_PCI_TLU_LNK_CTRL_DIS 0x0000000000000010ULL
503#define FO_PCI_TLU_LNK_CTRL_RCB 0x0000000000000008ULL
504#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S_L1S 0x0000000000000003ULL
505#define FO_PCI_TLU_LNK_CTRL_ASPM_L1S 0x0000000000000002ULL
506#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S 0x0000000000000001ULL
507#define FO_PCI_TLU_LNK_CTRL_ASPM_DIS 0x0000000000000000ULL
508
509/* PCI TLU link status register */
510#define FO_PCI_TLU_LNK_STAT_CLK 0x0000000000001000ULL
511#define FO_PCI_TLU_LNK_STAT_TRAIN 0x0000000000000800ULL
512#define FO_PCI_TLU_LNK_STAT_ERR 0x0000000000000400ULL
513#define FO_PCI_TLU_LNK_STAT_WDTH_MASK 0x00000000000003f0ULL
514#define FO_PCI_TLU_LNK_STAT_WDTH_SHFT 4
515#define FO_PCI_TLU_LNK_STAT_SPEED_MASK 0x000000000000000fULL
516#define FO_PCI_TLU_LNK_STAT_SPEED_SHFT 0
517
518/*
519 * PCI receive/transmit DLU/TLU uncorrectable error header 1/2 log
520 * registers
521 */
522#define FO_PCI_TLU_UERR_HDR_LOG_MASK 0xffffffffffffffffULL
523#define FO_PCI_TLU_UERR_HDR_LOG_SHFT 0
524
525/* PCI DLU/LPU interrupt status and mask registers */
526#define FO_PCI_LPU_INT_INT 0x0000000080000000ULL
527#define FIRE_PCI_LPU_INT_PRF_CNT2_OFLW 0x0000000000000080ULL
528#define FIRE_PCI_LPU_INT_PRF_CNT1_OFLW 0x0000000000000040ULL
529#define FO_PCI_LPU_INT_LNK_LYR 0x0000000000000020ULL
530#define FO_PCI_LPU_INT_PHY_ERR 0x0000000000000010ULL
531#define FIRE_PCI_LPU_INT_LTSSM 0x0000000000000008ULL
532#define FIRE_PCI_LPU_INT_PHY_TX 0x0000000000000004ULL
533#define FIRE_PCI_LPU_INT_PHY_RX 0x0000000000000002ULL
534#define FIRE_PCI_LPU_INT_PHY_GB 0x0000000000000001ULL
535
536/* PCI DLU/LPU link layer config register */
537#define FIRE_PCI_LPU_LNK_LYR_CFG_AUTO_UPDT_DIS 0x0000000000080000ULL
538#define FIRE_PCI_LPU_LNK_LYR_CFG_FREQ_NAK_EN 0x0000000000040000ULL
539#define FIRE_PCI_LPU_LNK_LYR_CFG_RPLY_AFTER_REQ 0x0000000000020000ULL
540#define FIRE_PCI_LPU_LNK_LYR_CFG_LAT_THRS_WR_EN 0x0000000000010000ULL
541#define FO_PCI_LPU_LNK_LYR_CFG_VC0_EN 0x0000000000000100ULL
542#define FIRE_PCI_LPU_LNK_LYR_CFG_L0S_ADJ_FAC_EN 0x0000000000000010ULL
543#define FIER_PCI_LPU_LNK_LYR_CFG_TLP_XMIT_FC_EN 0x0000000000000008ULL
544#define FO_PCI_LPU_LNK_LYR_CFG_FREQ_ACK_EN 0x0000000000000004ULL
545#define FO_PCI_LPU_LNK_LYR_CFG_RETRY_DIS 0x0000000000000002ULL
546
547/* PCI DLU/LPU link layer interrupt and status register */
548#define FO_PCI_LPU_LNK_LYR_INT_STAT_LNK_ERR_ACT 0x0000000080000000ULL
549#define OBERON_PCI_LPU_LNK_LYR_INT_STAT_PBUS_PE 0x0000000000800000ULL
550#define FO_PCI_LPU_LNK_LYR_INT_STAT_USPRTD_DLLP 0x0000000000400000ULL
551#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLLP_RX_ERR 0x0000000000200000ULL
552#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_DLLP 0x0000000000100000ULL
553#define FO_PCI_LPU_LNK_LYR_INT_STAT_TLP_RX_ERR 0x0000000000040000ULL
554#define FO_PCI_LPU_LNK_LYR_INT_STAT_SRC_ERR_TLP 0x0000000000020000ULL
555#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_TLP 0x0000000000010000ULL
556#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_UDF_ERR 0x0000000000000200ULL
557#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_OVF_ERR 0x0000000000000100ULL
558#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TLPM_ERR 0x0000000000000080ULL
559#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TFRM_ERR 0x0000000000000040ULL
560#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_PE 0x0000000000000020ULL
561#define FO_PCI_LPU_LNK_LYR_INT_STAT_EGRESS_PE 0x0000000000000010ULL
562#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_TMR_TO 0x0000000000000004ULL
563#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_NUM_RO 0x0000000000000002ULL
564#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLNK_PES 0x0000000000000001ULL
565
566/* PCI DLU/LPU flow control update control register */
567#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_C_EN 0x0000000000000004ULL
568#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_NP_EN 0x0000000000000002ULL
569#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_P_EN 0x0000000000000001ULL
570
571/* PCI DLU/LPU txlink ACKNAK latency timer threshold register */
572#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_MASK 0x000000000000ffffULL
573#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_SHFT 0
574
575/* PCI DLU/LPU txlink replay timer threshold register */
576#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_MASK 0x00000000000fffffULL
577#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_SHFT 0
578
579/* PCI DLU/LPU txlink FIFO pointer register */
580#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_MASK 0x00000000ffff0000ULL
581#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_SHFT 16
582#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_MASK 0x000000000000ffffULL
583#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_SHFT 0
584
585/* PCI DLU/LPU phy layer interrupt and status register */
586#define FO_PCI_LPU_PHY_LYR_INT_STAT_PHY_LYR_ERR 0x0000000080000000ULL
587#define FO_PCI_LPU_PHY_LYR_INT_STAT_KC_DLLP_ERR 0x0000000000000800ULL
588#define FO_PCI_LPU_PHY_LYR_INT_STAT_END_POS_ERR 0x0000000000000400ULL
589#define FO_PCI_LPU_PHY_LYR_INT_STAT_LNK_ERR 0x0000000000000200ULL
590#define FO_PCI_LPU_PHY_LYR_INT_STAT_TRN_ERR 0x0000000000000100ULL
591#define FO_PCI_LPU_PHY_LYR_INT_STAT_EDB_DET 0x0000000000000080ULL
592#define FO_PCI_LPU_PHY_LYR_INT_STAT_SDP_END 0x0000000000000040ULL
593#define FO_PCI_LPU_PHY_LYR_INT_STAT_STP_END_EDB 0x0000000000000020ULL
594#define FO_PCI_LPU_PHY_LYR_INT_STAT_INVC_ERR 0x0000000000000010ULL
595#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_SDP 0x0000000000000008ULL
596#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_STP 0x0000000000000004ULL
597#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_SDP_POS 0x0000000000000002ULL
598#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_STP_POS 0x0000000000000001ULL
599
600/* PCI DLU/LPU LTSSM config2 register */
601#define FO_PCI_LPU_LTSSM_CFG2_12_TO_MASK 0x00000000ffffffffULL
602#define FO_PCI_LPU_LTSSM_CFG2_12_TO_SHFT 0
603
604/* PCI DLU/LPU LTSSM config3 register */
605#define FO_PCI_LPU_LTSSM_CFG3_2_TO_MASK 0x00000000ffffffffULL
606#define FO_PCI_LPU_LTSSM_CFG3_2_TO_SHFT 0
607
608/* PCI DLU/LPU LTSSM config4 register */
609#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_MASK 0x00000000ff000000ULL
610#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_SHFT 24
611#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_MASK 0x0000000000ff0000ULL
612#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_SHFT 16
613#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_MASK 0x000000000000ff00ULL
614#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_SHFT 8
615#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_MASK 0x00000000000000ffULL
616#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_SHFT 0
617
618/* PCI DLU/LPU LTSSM config5 register */
619#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_MASK 0x00000000ffffe000ULL
620#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_SHFT 13
621#define FO_PCI_LPU_LTSSM_CFG5_RCV_DET_TST_MODE 0x0000000000001000ULL
622#define FO_PCI_LPU_LTSSM_CFG5_POLL_CMPLNC_DIS 0x0000000000000800ULL
623#define FO_PCI_LPU_LTSSM_CFG5_TX_IDLE_TX_FTS 0x0000000000000400ULL
624#define FO_PCI_LPU_LTSSM_CFG5_RX_FTS_RVR_LK 0x0000000000000200ULL
625#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_MASK 0x0000000000000180ULL
626#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_SHFT 7
627#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_ACTIVE 0x0000000000000040ULL
628#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_EXIT 0x0000000000000020ULL
629#define FO_PCI_LPU_LTSSM_CFG5_LPBK_ACTIVE_EXIT 0x0000000000000010ULL
630#define FO_PCI_LPU_LTSSM_CFG5_L1_IDLE_RCVRY_LK 0x0000000000000008ULL
631#define FO_PCI_LPU_LTSSM_CFG5_L0_TRN_CNTRL_RST 0x0000000000000004ULL
632#define FO_PCI_LPU_LTSSM_CFG5_L0_LPBK 0x0000000000000002ULL
633#define FO_PCI_LPU_LTSSM_CFG5_UNUSED2 0x0000000000000001ULL
634
635/* Controller configuration and status registers */
636#define FIRE_JBUS_PAR_CTRL 0x60010
637#define FO_XBC_ERR_LOG_EN 0x61000
638#define FO_XBC_INT_EN 0x61008
639#define FO_XBC_INT_STAT 0x61010
640#define FO_XBC_ERR_STAT_CLR 0x61018
641#define FIRE_JBC_FATAL_RST_EN 0x61028
642#define FIRE_JBCINT_ITRANS_ERR_LOG 0x61040
643#define FIRE_JBCINT_ITRANS_ERR_LOG2 0x61048
644#define FIRE_JBCINT_OTRANS_ERR_LOG 0x61040
645#define FIRE_JBCINT_OTRANS_ERR_LOG2 0x61048
646#define FIRE_FATAL_ERR_LOG 0x61050
647#define FIRE_FATAL_ERR_LOG2 0x61058
648#define FIRE_MERGE_TRANS_ERR_LOG 0x61060
649#define FIRE_DMCINT_ODCD_ERR_LOG 0x61068
650#define FIRE_DMCINT_IDC_ERR_LOG 0x61070
651#define FIRE_JBC_CSR_ERR_LOG 0x61078
652#define FIRE_JBC_CORE_BLOCK_INT_EN 0x61800
653#define FIRE_JBC_CORE_BLOCK_ERR_STAT 0x61808
654#define FO_XBC_PRF_CNT_SEL 0x62000
655#define FO_XBC_PRF_CNT0 0x62008
656#define FO_XBC_PRF_CNT1 0x62010
657
658/* JBus parity control register */
659#define FIRE_JBUS_PAR_CTRL_P_EN 0x8000000000000000ULL
660#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_MASK 0x000000000000003cULL
661#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_SHFT 2
662#define FIRE_JBUS_PAR_CTRL_NEXT_DATA 0x0000000000000002ULL
663#define FIRE_JBUS_PAR_CTRL_NEXT_ADDR 0x0000000000000001ULL
664
665/* JBC error log enable register - may also apply to UBC */
666#define FIRE_JBC_ERR_LOG_EN_SPARE_MASK 0x00000000e0000000ULL
667#define FIRE_JBC_ERR_LOG_EN_SPARE_SHFT 29
668#define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP_RD 0x0000000010000000ULL
669#define FIRE_JBC_ERR_LOG_EN_ILL_ACC_RD 0x0000000008000000ULL
670#define FIRE_JBC_ERR_LOG_EN_EBUS_TO 0x0000000004000000ULL
671#define FIRE_JBC_ERR_LOG_EN_MB_PEA 0x0000000002000000ULL
672#define FIRE_JBC_ERR_LOG_EN_MB_PER 0x0000000001000000ULL
673#define FIRE_JBC_ERR_LOG_EN_MB_PEW 0x0000000000800000ULL
674#define FIRE_JBC_ERR_LOG_EN_UE_ASYN 0x0000000000400000ULL
675#define FIRE_JBC_ERR_LOG_EN_CE_ASYN 0x0000000000200000ULL
676#define FIRE_JBC_ERR_LOG_EN_JTE 0x0000000000100000ULL
677#define FIRE_JBC_ERR_LOG_EN_JBE 0x0000000000080000ULL
678#define FIRE_JBC_ERR_LOG_EN_JUE 0x0000000000040000ULL
679#define FIRE_JBC_ERR_LOG_EN_IJP 0x0000000000020000ULL
680#define FIRE_JBC_ERR_LOG_EN_ICISE 0x0000000000010000ULL
681#define FIRE_JBC_ERR_LOG_EN_CPE 0x0000000000008000ULL
682#define FIRE_JBC_ERR_LOG_EN_APE 0x0000000000004000ULL
683#define FIRE_JBC_ERR_LOG_EN_WR_DPE 0x0000000000002000ULL
684#define FIRE_JBC_ERR_LOG_EN_RD_DPE 0x0000000000001000ULL
685#define FIRE_JBC_ERR_LOG_EN_ILL_BMW 0x0000000000000800ULL
686#define FIRE_JBC_ERR_LOG_EN_ILL_BMR 0x0000000000000400ULL
687#define FIRE_JBC_ERR_LOG_EN_BJC 0x0000000000000200ULL
688#define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP 0x0000000000000100ULL
689#define FIRE_JBC_ERR_LOG_EN_PIO_DPE 0x0000000000000080ULL
690#define FIRE_JBC_ERR_LOG_EN_PIO_CPE 0x0000000000000040ULL
691#define FIRE_JBC_ERR_LOG_EN_ILL_ACC 0x0000000000000020ULL
692#define FIRE_JBC_ERR_LOG_EN_UNSOL_RD 0x0000000000000010ULL
693#define FIRE_JBC_ERR_LOG_EN_UNSOL_INT 0x0000000000000008ULL
694#define FIRE_JBC_ERR_LOG_EN_JTCEEW 0x0000000000000004ULL
695#define FIRE_JBC_ERR_LOG_EN_JTCEEI 0x0000000000000002ULL
696#define FIRE_JBC_ERR_LOG_EN_JTCEER 0x0000000000000001ULL
697
698/* JBC interrupt enable, interrupt status and error status clear registers */
699#define FIRE_JBC_ERR_INT_SPARE_S_MASK 0xe000000000000000ULL
700#define FIRE_JBC_ERR_INT_SPARE_S_SHFT 61
701#define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_S 0x1000000000000000ULL
702#define FIRE_JBC_ERR_INT_ILL_ACC_RD_S 0x0800000000000000ULL
703#define FIRE_JBC_ERR_INT_EBUS_TO_S 0x0400000000000000ULL
704#define FIRE_JBC_ERR_INT_MB_PEA_S 0x0200000000000000ULL
705#define FIRE_JBC_ERR_INT_MB_PER_S 0x0100000000000000ULL
706#define FIRE_JBC_ERR_INT_MB_PEW_S 0x0080000000000000ULL
707#define FIRE_JBC_ERR_INT_UE_ASYN_S 0x0040000000000000ULL
708#define FIRE_JBC_ERR_INT_CE_ASYN_S 0x0020000000000000ULL
709#define FIRE_JBC_ERR_INT_JTE_S 0x0010000000000000ULL
710#define FIRE_JBC_ERR_INT_JBE_S 0x0008000000000000ULL
711#define FIRE_JBC_ERR_INT_JUE_S 0x0004000000000000ULL
712#define FIRE_JBC_ERR_INT_IJP_S 0x0002000000000000ULL
713#define FIRE_JBC_ERR_INT_ICISE_S 0x0001000000000000ULL
714#define FIRE_JBC_ERR_INT_CPE_S 0x0000800000000000ULL
715#define FIRE_JBC_ERR_INT_APE_S 0x0000400000000000ULL
716#define FIRE_JBC_ERR_INT_WR_DPE_S 0x0000200000000000ULL
717#define FIRE_JBC_ERR_INT_RD_DPE_S 0x0000100000000000ULL
718#define FIRE_JBC_ERR_INT_ILL_BMW_S 0x0000080000000000ULL
719#define FIRE_JBC_ERR_INT_ILL_BMR_S 0x0000040000000000ULL
720#define FIRE_JBC_ERR_INT_BJC_S 0x0000020000000000ULL
721#define FIRE_JBC_ERR_INT_PIO_UNMAP_S 0x0000010000000000ULL
722#define FIRE_JBC_ERR_INT_PIO_DPE_S 0x0000008000000000ULL
723#define FIRE_JBC_ERR_INT_PIO_CPE_S 0x0000004000000000ULL
724#define FIRE_JBC_ERR_INT_ILL_ACC_S 0x0000002000000000ULL
725#define FIRE_JBC_ERR_INT_UNSOL_RD_S 0x0000001000000000ULL
726#define FIRE_JBC_ERR_INT_UNSOL_INT_S 0x0000000800000000ULL
727#define FIRE_JBC_ERR_INT_JTCEEW_S 0x0000000400000000ULL
728#define FIRE_JBC_ERR_INT_JTCEEI_S 0x0000000200000000ULL
729#define FIRE_JBC_ERR_INT_JTCEER_S 0x0000000100000000ULL
730#define FIRE_JBC_ERR_INT_SPARE_P_MASK 0x00000000e0000000ULL
731#define FIRE_JBC_ERR_INT_SPARE_P_SHFT 29
732#define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_P 0x0000000010000000ULL
733#define FIRE_JBC_ERR_INT_ILL_ACC_RD_P 0x0000000008000000ULL
734#define FIRE_JBC_ERR_INT_EBUS_TO_P 0x0000000004000000ULL
735#define FIRE_JBC_ERR_INT_MB_PEA_P 0x0000000002000000ULL
736#define FIRE_JBC_ERR_INT_MB_PER_P 0x0000000001000000ULL
737#define FIRE_JBC_ERR_INT_MB_PEW_P 0x0000000000800000ULL
738#define FIRE_JBC_ERR_INT_UE_ASYN_P 0x0000000000400000ULL
739#define FIRE_JBC_ERR_INT_CE_ASYN_P 0x0000000000200000ULL
740#define FIRE_JBC_ERR_INT_JTE_P 0x0000000000100000ULL
741#define FIRE_JBC_ERR_INT_JBE_P 0x0000000000080000ULL
742#define FIRE_JBC_ERR_INT_JUE_P 0x0000000000040000ULL
743#define FIRE_JBC_ERR_INT_IJP_P 0x0000000000020000ULL
744#define FIRE_JBC_ERR_INT_ICISE_P 0x0000000000010000ULL
745#define FIRE_JBC_ERR_INT_CPE_P 0x0000000000008000ULL
746#define FIRE_JBC_ERR_INT_APE_P 0x0000000000004000ULL
747#define FIRE_JBC_ERR_INT_WR_DPE_P 0x0000000000002000ULL
748#define FIRE_JBC_ERR_INT_RD_DPE_P 0x0000000000001000ULL
749#define FIRE_JBC_ERR_INT_ILL_BMW_P 0x0000000000000800ULL
750#define FIRE_JBC_ERR_INT_ILL_BMR_P 0x0000000000000400ULL
751#define FIRE_JBC_ERR_INT_BJC_P 0x0000000000000200ULL
752#define FIRE_JBC_ERR_INT_PIO_UNMAP_P 0x0000000000000100ULL
753#define FIRE_JBC_ERR_INT_PIO_DPE_P 0x0000000000000080ULL
754#define FIRE_JBC_ERR_INT_PIO_CPE_P 0x0000000000000040ULL
755#define FIRE_JBC_ERR_INT_ILL_ACC_P 0x0000000000000020ULL
756#define FIRE_JBC_ERR_INT_UNSOL_RD_P 0x0000000000000010ULL
757#define FIRE_JBC_ERR_INT_UNSOL_INT_P 0x0000000000000008ULL
758#define FIRE_JBC_ERR_INT_JTCEEW_P 0x0000000000000004ULL
759#define FIRE_JBC_ERR_INT_JTCEEI_P 0x0000000000000002ULL
760#define FIRE_JBC_ERR_INT_JTCEER_P 0x0000000000000001ULL
761
762/* UBC interrupt enable, error status and error status clear registers */
763#define OBERON_UBC_ERR_INT_PIORBEUE_S 0x0004000000000000ULL
764#define OBERON_UBC_ERR_INT_PIOWBEUE_S 0x0002000000000000ULL
765#define OBERON_UBC_ERR_INT_PIOWTUE_S 0x0001000000000000ULL
766#define OBERON_UBC_ERR_INT_MEMWTAXB_S 0x0000080000000000ULL
767#define OBERON_UBC_ERR_INT_MEMRDAXB_S 0x0000040000000000ULL
768#define OBERON_UBC_ERR_INT_DMAWTUEB_S 0x0000020000000000ULL
769#define OBERON_UBC_ERR_INT_DMARDUEB_S 0x0000010000000000ULL
770#define OBERON_UBC_ERR_INT_MEMWTAXA_S 0x0000000800000000ULL
771#define OBERON_UBC_ERR_INT_MEMRDAXA_S 0x0000000400000000ULL
772#define OBERON_UBC_ERR_INT_DMAWTUEA_S 0x0000000200000000ULL
773#define OBERON_UBC_ERR_INT_DMARDUEA_S 0x0000000100000000ULL
774#define OBERON_UBC_ERR_INT_PIORBEUE_P 0x0000000000040000ULL
775#define OBERON_UBC_ERR_INT_PIOWBEUE_P 0x0000000000020000ULL
776#define OBERON_UBC_ERR_INT_PIOWTUE_P 0x0000000000010000ULL
777#define OBERON_UBC_ERR_INT_MEMWTAXB_P 0x0000000000000800ULL
778#define OBERON_UBC_ERR_INT_MEMRDAXB_P 0x0000000000000400ULL
779#define OBERON_UBC_ERR_INT_DMARDUEB_P 0x0000000000000200ULL
780#define OBERON_UBC_ERR_INT_DMAWTUEB_P 0x0000000000000100ULL
781#define OBERON_UBC_ERR_INT_MEMWTAXA_P 0x0000000000000008ULL
782#define OBERON_UBC_ERR_INT_MEMRDAXA_P 0x0000000000000004ULL
783#define OBERON_UBC_ERR_INT_DMAWTUEA_P 0x0000000000000002ULL
784#define OBERON_UBC_ERR_INT_DMARDUEA_P 0x0000000000000001ULL
785
786/* JBC fatal reset enable register */
787#define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_MASK 0x000000000c000000ULL
788#define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_SHFT 26
789#define FIRE_JBC_FATAL_RST_EN_MB_PEA_P_INT 0x0000000002000000ULL
790#define FIRE_JBC_FATAL_RST_EN_CPE_P_INT 0x0000000000008000ULL
791#define FIRE_JBC_FATAL_RST_EN_APE_P_INT 0x0000000000004000ULL
792#define FIRE_JBC_FATAL_RST_EN_PIO_CPE_INT 0x0000000000000040ULL
793#define FIRE_JBC_FATAL_RST_EN_JTCEEW_P_INT 0x0000000000000004ULL
794#define FIRE_JBC_FATAL_RST_EN_JTCEEI_P_INT 0x0000000000000002ULL
795#define FIRE_JBC_FATAL_RST_EN_JTCEER_P_INT 0x0000000000000001ULL
796
797/* JBC JBCINT in transaction error log register */
798#define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL
799#define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_SHFT 54
800#define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL
801#define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_SHFT 48
802#define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL
803#define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_SHFT 0
804
805/* JBC JBCINT in transaction error log register 2 */
806#define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL
807#define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_SHFT 28
808#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL
809#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_SHFT 21
810#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL
811#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_SHFT 0
812
813/* JBC JBCINT out transaction error log register */
814#define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_MASK 0x003f000000000000ULL
815#define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_SHFT 48
816#define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL
817#define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_SHFT 0
818
819/* JBC JBCINT out transaction error log register 2 */
820#define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL
821#define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_SHFT 28
822#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL
823#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_SHFT 21
824#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL
825#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_SHFT 0
826
827/* JBC merge transaction error log register */
828#define FIRE_FATAL_ERR_LOG_DATA_MASK 0xffffffffffffffffULL
829#define FIRE_FATAL_ERR_LOG_DATA_SHFT 0
830
831/* JBC merge transaction error log register 2 */
832#define FIRE_FATAL_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL
833#define FIRE_FATAL_ERR_LOG2_ARB_WN_SHFT 28
834#define FIRE_FATAL_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL
835#define FIRE_FATAL_ERR_LOG2_J_REQ_SHFT 21
836#define FIRE_FATAL_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL
837#define FIRE_FATAL_ERR_LOG2_J_PACK_SHFT 0
838
839/* JBC merge transaction error log register */
840#define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL
841#define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_SHFT 54
842#define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL
843#define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_SHFT 48
844#define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_MASK 0x0000f80000000000ULL
845#define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_SHFT 43
846#define FIRE_MERGE_TRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL
847#define FIRE_MERGE_TRANS_ERR_LOG_ADDR_SHFT 0
848
849/* JBC DMCINT ODCD error log register */
850#define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_MASK 0x0030000000000000ULL
851#define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_SHFT 52
852#define FIRE_DMCINT_ODCD_ERR_LOG_AID_MASK 0x000f000000000000ULL
853#define FIRE_DMCINT_ODCD_ERR_LOG_AID_SHFT 48
854#define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_MASK 0x0000f80000000000ULL
855#define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_SHFT 43
856#define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL
857#define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_SHFT 0
858
859/* JBC DMCINT IDC error log register */
860#define FIRE_DMCINT_IDC_ERR_DMC_CTAG_MASK 0x000000000fff0000ULL
861#define FIRE_DMCINT_IDC_ERR_DMC_CTAG_SHFT 16
862#define FIRE_DMCINT_IDC_ERR_TRANSID_MASK 0x000000000000c000ULL
863#define FIRE_DMCINT_IDC_ERR_AGNTID_MASK 0x0000000000003c00ULL
864#define FIRE_DMCINT_IDC_ERR_AGNTID_SHFT 10
865#define FIRE_DMCINT_IDC_ERR_SRCID_MASK 0x00000000000003e0ULL
866#define FIRE_DMCINT_IDC_ERR_SRCID_SHFT 5
867#define FIRE_DMCINT_IDC_ERR_TARGID_MASK 0x000000000000001fULL
868#define FIRE_DMCINT_IDC_ERRO_TARGID_SHFT 0
869
870/* JBC CSR error log register */
871#define FIRE_JBC_CSR_ERR_LOG_WR 0x0000040000000000ULL
872#define FIRE_JBC_CSR_ERR_LOG_BMASK_MASK 0x000003fffc000000ULL
873#define FIRE_JBC_CSR_ERR_LOG_BMASK_SHFT 26
874#define FIRE_JBC_CSR_ERR_LOG_ADDR_MASK 0x0000000003ffffffULL
875#define FIRE_JBC_CSR_ERR_LOG_ADDR_SHFT 0
876
877/* JBC core and block interrupt enable register */
878#define FIRE_JBC_CORE_BLOCK_INT_EN_JBC 0x8000000000000000ULL
879#define FIRE_JBC_CORE_BLOCK_INT_EN_CSR 0x0000000000000008ULL
880#define FIRE_JBC_CORE_BLOCK_INT_EN_MERGE 0x0000000000000004ULL
881#define FIRE_JBC_CORE_BLOCK_INT_EN_JBCINT 0x0000000000000002ULL
882#define FIRE_JBC_CORE_BLOCK_INT_EN_DMCINT 0x0000000000000001ULL
883
884/* JBC core and block error status register */
885#define FIRE_JBC_CORE_BLOCK_ERR_STAT_CSR 0x0000000000000008ULL
886#define FIRE_JBC_CORE_BLOCK_ERR_STAT_MERGE 0x0000000000000004ULL
887#define FIRE_JBC_CORE_BLOCK_ERR_STAT_JBCINT 0x0000000000000002ULL
888#define FIRE_JBC_CORE_BLOCK_ERR_STAT_DMCINT 0x0000000000000001ULL
889
890/* JBC performance counter select register - may also apply to UBC */
891#define FO_XBC_PRF_CNT_PIO_RD_PCIEB 0x0000000000000018ULL
892#define FO_XBC_PRF_CNT_PIO_WR_PCIEB 0x0000000000000017ULL
893#define FO_XBC_PRF_CNT_PIO_RD_PCIEA 0x0000000000000016ULL
894#define FO_XBC_PRF_CNT_PIO_WR_PCIEA 0x0000000000000015ULL
895#define FO_XBC_PRF_CNT_WB 0x0000000000000014ULL
896#define FO_XBC_PRF_CNT_PIO_FRGN 0x0000000000000013ULL
897#define FO_XBC_PRF_CNT_XB_NCHRNT 0x0000000000000012ULL
898#define FO_XBC_PRF_CNT_FO_CHRNT 0x0000000000000011ULL
899#define FO_XBC_PRF_CNT_XB_CHRNT 0x0000000000000010ULL
900#define FO_XBC_PRF_CNT_AOKOFF_DOKOFF 0x000000000000000fULL
901#define FO_XBC_PRF_CNT_DOKOFF 0x000000000000000eULL
902#define FO_XBC_PRF_CNT_AOKOFF 0x000000000000000dULL
903#define FO_XBC_PRF_CNT_RD_TOTAL 0x000000000000000cULL
904#define FO_XBC_PRF_CNT_WR_TOTAL 0x000000000000000bULL
905#define FO_XBC_PRF_CNT_WR_PARTIAL 0x000000000000000aULL
906#define FO_XBC_PRF_CNT_PIOS_CSR_RINGB 0x0000000000000009ULL
907#define FO_XBC_PRF_CNT_PIOS_CSR_RINGA 0x0000000000000008ULL
908#define FO_XBC_PRF_CNT_PIOS_EBUS 0x0000000000000007ULL
909#define FO_XBC_PRF_CNT_PIOS_I2C 0x0000000000000006ULL
910#define FO_XBC_PRF_CNT_RD_LAT_SMPLS 0x0000000000000005ULL
911#define FO_XBC_PRF_CNT_RD_LAT 0x0000000000000004ULL
912#define FO_XBC_PRF_CNT_ON_XB 0x0000000000000003ULL
913#define FO_XBC_PRF_CNT_XB_IDL 0x0000000000000002ULL
914#define FO_XBC_PRF_CNT_XB_CLK 0x0000000000000001ULL
915#define FO_XBC_PRF_CNT_NONE 0x0000000000000000ULL
916#define FO_XBC_PRF_CNT_CNT1_SHFT 8
917#define FO_XBC_PRF_CNT_CNT0_SHFT 0
918
919/* JBC performance counter 0/1 registers - may also apply to UBC */
920#define FO_XBC_PRF_CNT_MASK 0xffffffffffffffffULL
921#define FO_XBC_PRF_CNT_SHFT 0
922
923/* Lookup tables */
924const uint16_t fire_freq_nak_tmr_thrs[6][4] = {
925 { 0x00ed, 0x049, 0x043, 0x030 },
926 { 0x01a0, 0x076, 0x06b, 0x048 },
927 { 0x022f, 0x09a, 0x056, 0x056 },
928 { 0x042f, 0x11a, 0x096, 0x096 },
929 { 0x082f, 0x21a, 0x116, 0x116 },
930 { 0x102f, 0x41a, 0x216, 0x216 }
931};
932
933const uint16_t fire_rply_tmr_thrs[6][4] = {
934 { 0x0379, 0x112, 0x0fc, 0x0b4 },
935 { 0x0618, 0x1BA, 0x192, 0x10e },
936 { 0x0831, 0x242, 0x143, 0x143 },
937 { 0x0fb1, 0x422, 0x233, 0x233 },
938 { 0x1eb0, 0x7e1, 0x412, 0x412 },
939 { 0x3cb0, 0xf61, 0x7d2, 0x7d2 }
940};
941
942/* Register default values */
943#define FO_PCI_TLU_CTRL_L0S_TIM_DFLT 0xda
944#define FO_PCI_TLU_CTRL_CFG_DFLT 0x1
945#define FO_PCI_LPU_LTSSM_CFG2_12_TO_DFLT 0x2dc6c0
946#define FO_PCI_LPU_LTSSM_CFG3_2_TO_DFLT 0x7a120
947#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_DFLT 0x2
948#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_DFLT 0x8c
949#define OBERON_PCI_LPU_TXLNK_RPLY_TMR_THRS_DFLT 0xc9
950#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_DFLT 0x0
951#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_DFLT 0xffff
952
953/* INO macros */
954#define FO_EQ_FIRST_INO 0x18
955#define FO_EQ_LAST_INO 0x3b
956#define FO_DMC_PEC_INO 0x3e
957#define FO_XCB_INO 0x3f
958#define FO_MAX_INO FO_XCB_INO
959
960/* Device space macros */
961#define FO_CONF_BUS_SHFT 20
962#define FO_CONF_DEV_SHFT 15
963#define FO_CONF_FUNC_SHFT 12
964#define FO_CONF_REG_SHFT 0
965#define FO_IO_SIZE 0x10000000
966#define FO_MEM_SIZE 0x1ffff0000
967
968#define FO_CONF_OFF(bus, slot, func, reg) \
969 (((bus) << FO_CONF_BUS_SHFT) | \
970 ((slot) << FO_CONF_DEV_SHFT) | \
971 ((func) << FO_CONF_FUNC_SHFT) | \
972 ((reg) << FO_CONF_REG_SHFT))
973
974/* Width of the physical addresses the IOMMU translates to */
975#define FIRE_IOMMU_BITS 43
976#define OBERON_IOMMU_BITS 47
977
978/* Event queue macros */
979#define FO_EQ_ALIGNMENT (512 * 1024)
980#define FO_EQ_NRECORDS 128
981#define FO_EQ_RECORD_SIZE 64
982
983/* Event queue record format */
984struct fo_msiq_record {
985 uint64_t fomqr_word0;
986 uint64_t fomqr_word1;
987 uint64_t fomqr_reserved[6];
988};
989
990#define FO_MQR_WORD0_FMT_TYPE_MASK 0x7f00000000000000ULL
991#define FO_MQR_WORD0_FMT_TYPE_SHFT 56
992#define FO_MQR_WORD0_FMT_TYPE_MSI64 0x7800000000000000ULL
993#define FO_MQR_WORD0_FMT_TYPE_MSI32 0x5800000000000000ULL
994#define FO_MQR_WORD0_FMT_TYPE_MSG 0x3000000000000000ULL
995#define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_MASK 0x0700000000000000ULL
996#define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_SHFT 56
997#define FO_MQR_WORD0_LENGTH_MASK 0x00ffc00000000000ULL
998#define FO_MQR_WORD0_LENGTH_SHFT 46
999#define FO_MQR_WORD0_ADDR0_MASK 0x00003fff00000000ULL
1000#define FO_MQR_WORD0_ADDR0_SHFT 32
1001#define FO_MQR_WORD0_RID_MASK 0x00000000ffff0000ULL
1002#define FO_MQR_WORD0_RID_SHFT 16
1003#define FO_MQR_WORD0_DATA0_MASK 0x000000000000ffffULL
1004#define FO_MQR_WORD0_DATA0_SHFT 0
1005#define FO_MQR_WORD1_ADDR1_MASK 0xffffffffffff0000ULL
1006#define FO_MQR_WORD1_ADDR1_SHFT 16
1007#define FO_MQR_WORD1_DATA1_MASK 0x000000000000ffffULL
1008#define FO_MQR_WORD1_DATA1_SHFT 0
1009
1010#endif /* !_SPARC64_PCI_FIREREG_H_ */
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