1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/sparc64/include/intr_machdep.h 210176 2010-07-16 22:09:29Z mav $
| 26 * $FreeBSD: head/sys/sparc64/include/intr_machdep.h 210601 2010-07-29 12:08:46Z mav $
|
27 */
28
29#ifndef _MACHINE_INTR_MACHDEP_H_
30#define _MACHINE_INTR_MACHDEP_H_
31
32#define IRSR_BUSY (1 << 5)
33
34#define PIL_MAX (1 << 4)
35#define IV_MAX (1 << 11)
36
37#define IR_FREE (PIL_MAX * 2)
38
39#define IH_SHIFT PTR_SHIFT
40#define IQE_SHIFT 5
41#define IV_SHIFT 6
42
43#define PIL_LOW 1 /* stray interrupts */
44#define PIL_ITHREAD 2 /* interrupts that use ithreads */
45#define PIL_RENDEZVOUS 3 /* smp rendezvous ipi */
46#define PIL_AST 4 /* ast ipi */
47#define PIL_STOP 5 /* stop cpu ipi */
48#define PIL_PREEMPT 6 /* preempt idle thread cpu ipi */
| 27 */
28
29#ifndef _MACHINE_INTR_MACHDEP_H_
30#define _MACHINE_INTR_MACHDEP_H_
31
32#define IRSR_BUSY (1 << 5)
33
34#define PIL_MAX (1 << 4)
35#define IV_MAX (1 << 11)
36
37#define IR_FREE (PIL_MAX * 2)
38
39#define IH_SHIFT PTR_SHIFT
40#define IQE_SHIFT 5
41#define IV_SHIFT 6
42
43#define PIL_LOW 1 /* stray interrupts */
44#define PIL_ITHREAD 2 /* interrupts that use ithreads */
45#define PIL_RENDEZVOUS 3 /* smp rendezvous ipi */
46#define PIL_AST 4 /* ast ipi */
47#define PIL_STOP 5 /* stop cpu ipi */
48#define PIL_PREEMPT 6 /* preempt idle thread cpu ipi */
|
| 49#define PIL_HARDCLOCK 7 /* hardclock broadcast */
50#define PIL_STATCLOCK 8 /* statclock broadcast */
|
49#define PIL_FILTER 12 /* filter interrupts */
50#define PIL_FAST 13 /* fast interrupts */
51#define PIL_TICK 14 /* tick interrupts */
52
53#ifndef LOCORE
54
55struct trapframe;
56
57typedef void ih_func_t(struct trapframe *);
58typedef void iv_func_t(void *);
59
60struct intr_request {
61 struct intr_request *ir_next;
62 iv_func_t *ir_func;
63 void *ir_arg;
64 u_int ir_vec;
65 u_int ir_pri;
66};
67
68struct intr_controller {
69 void (*ic_enable)(void *);
70 void (*ic_disable)(void *);
71 void (*ic_assign)(void *);
72 void (*ic_clear)(void *);
73};
74
75struct intr_vector {
76 iv_func_t *iv_func;
77 void *iv_arg;
78 const struct intr_controller *iv_ic;
79 void *iv_icarg;
80 struct intr_event *iv_event;
81 u_int iv_pri;
82 u_int iv_vec;
83 u_int iv_mid;
84 u_int iv_refcnt;
85 u_int iv_pad[2];
86};
87
88extern ih_func_t *intr_handlers[];
89extern struct intr_vector intr_vectors[];
90
91#ifdef SMP
92void intr_add_cpu(u_int cpu);
93#endif
94int intr_bind(int vec, u_char cpu);
95int intr_describe(int vec, void *ih, const char *descr);
96void intr_setup(int level, ih_func_t *ihf, int pri, iv_func_t *ivf,
97 void *iva);
98void intr_init1(void);
99void intr_init2(void);
100int intr_controller_register(int vec, const struct intr_controller *ic,
101 void *icarg);
102int inthand_add(const char *name, int vec, int (*filt)(void *),
103 void (*handler)(void *), void *arg, int flags, void **cookiep);
104int inthand_remove(int vec, void *cookie);
105
106ih_func_t intr_fast;
107
108#endif /* !LOCORE */
109
110#endif /* !_MACHINE_INTR_MACHDEP_H_ */
| 51#define PIL_FILTER 12 /* filter interrupts */
52#define PIL_FAST 13 /* fast interrupts */
53#define PIL_TICK 14 /* tick interrupts */
54
55#ifndef LOCORE
56
57struct trapframe;
58
59typedef void ih_func_t(struct trapframe *);
60typedef void iv_func_t(void *);
61
62struct intr_request {
63 struct intr_request *ir_next;
64 iv_func_t *ir_func;
65 void *ir_arg;
66 u_int ir_vec;
67 u_int ir_pri;
68};
69
70struct intr_controller {
71 void (*ic_enable)(void *);
72 void (*ic_disable)(void *);
73 void (*ic_assign)(void *);
74 void (*ic_clear)(void *);
75};
76
77struct intr_vector {
78 iv_func_t *iv_func;
79 void *iv_arg;
80 const struct intr_controller *iv_ic;
81 void *iv_icarg;
82 struct intr_event *iv_event;
83 u_int iv_pri;
84 u_int iv_vec;
85 u_int iv_mid;
86 u_int iv_refcnt;
87 u_int iv_pad[2];
88};
89
90extern ih_func_t *intr_handlers[];
91extern struct intr_vector intr_vectors[];
92
93#ifdef SMP
94void intr_add_cpu(u_int cpu);
95#endif
96int intr_bind(int vec, u_char cpu);
97int intr_describe(int vec, void *ih, const char *descr);
98void intr_setup(int level, ih_func_t *ihf, int pri, iv_func_t *ivf,
99 void *iva);
100void intr_init1(void);
101void intr_init2(void);
102int intr_controller_register(int vec, const struct intr_controller *ic,
103 void *icarg);
104int inthand_add(const char *name, int vec, int (*filt)(void *),
105 void (*handler)(void *), void *arg, int flags, void **cookiep);
106int inthand_remove(int vec, void *cookie);
107
108ih_func_t intr_fast;
109
110#endif /* !LOCORE */
111
112#endif /* !_MACHINE_INTR_MACHDEP_H_ */
|