| cache.h (97001) | cache.h (112399) |
|---|---|
| 1/* 2 * Copyright (c) 1996 3 * The President and Fellows of Harvard College. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and --- 27 unchanged lines hidden (view full) --- 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * from: @(#)cache.h 8.1 (Berkeley) 6/11/93 42 * from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp 43 * | 1/* 2 * Copyright (c) 1996 3 * The President and Fellows of Harvard College. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and --- 27 unchanged lines hidden (view full) --- 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * from: @(#)cache.h 8.1 (Berkeley) 6/11/93 42 * from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp 43 * |
| 44 * $FreeBSD: head/sys/sparc64/include/cache.h 97001 2002-05-20 16:30:47Z jake $ | 44 * $FreeBSD: head/sys/sparc64/include/cache.h 112399 2003-03-19 06:55:37Z jake $ |
| 45 */ 46 47#ifndef _MACHINE_CACHE_H_ 48#define _MACHINE_CACHE_H_ 49 | 45 */ 46 47#ifndef _MACHINE_CACHE_H_ 48#define _MACHINE_CACHE_H_ 49 |
| 50#include <vm/vm.h> 51#include <vm/pmap.h> 52 | |
| 53#include <dev/ofw/openfirm.h> 54 | 50#include <dev/ofw/openfirm.h> 51 |
| 55/* 56 * Cache diagnostic access definitions. 57 */ 58/* ASI offsets for I$ diagnostic access */ 59#define ICDA_SET_SHIFT 13 60#define ICDA_SET_MASK (1UL << ICDA_SET_SHIFT) 61#define ICDA_SET(a) (((a) << ICDA_SET_SHIFT) & ICDA_SET_MASK) 62/* I$ tag/valid format */ 63#define ICDT_TAG_SHIFT 8 64#define ICDT_TAG_BITS 28 65#define ICDT_TAG_MASK (((1UL << ICDT_TAG_BITS) - 1) << ICDT_TAG_SHIFT) 66#define ICDT_TAG(x) (((x) & ICDT_TAG_MASK) >> ICDT_TAG_SHIFT) 67#define ICDT_VALID (1UL << 36) 68/* D$ tag/valid format */ 69#define DCDT_TAG_SHIFT 2 70#define DCDT_TAG_BITS 28 71#define DCDT_TAG_MASK (((1UL << DCDT_TAG_BITS) - 1) << DCDT_TAG_SHIFT) 72#define DCDT_TAG(x) (((x) & DCDT_TAG_MASK) >> DCDT_TAG_SHIFT) 73#define DCDT_VALID_BITS 2 74#define DCDT_VALID_MASK ((1UL << DCDT_VALID_BITS) - 1) 75/* E$ ASI_ECACHE_W/ASI_ECACHE_R address flags */ 76#define ECDA_DATA (1UL << 39) 77#define ECDA_TAG (1UL << 40) 78/* E$ tag/state/parity format */ 79#define ECDT_TAG_BITS 13 80#define ECDT_TAG_SIZE (1UL << ECDT_TAG_BITS) 81#define ECDT_TAG_MASK (ECDT_TAG_SIZE - 1) | 52#define DCACHE_COLOR_BITS (1) 53#define DCACHE_COLORS (1 << DCACHE_COLOR_BITS) 54#define DCACHE_COLOR_MASK (DCACHE_COLORS - 1) 55#define DCACHE_COLOR(va) (((va) >> PAGE_SHIFT) & DCACHE_COLOR_MASK) 56#define DCACHE_OTHER_COLOR(color) \ 57 ((color) ^ DCACHE_COLOR_BITS) |
| 82 | 58 |
| 83/* 84 * Do two virtual addresses (at which the same page is mapped) form and illegal 85 * alias in D$? XXX: should use cache.dc_size here. 86 */ 87#define DCACHE_BOUNDARY 0x4000 88#define DCACHE_BMASK (DCACHE_BOUNDARY - 1) 89#define CACHE_BADALIAS(v1, v2) \ 90 (((v1) & DCACHE_BMASK) != ((v2) & DCACHE_BMASK)) 91 92/* 93 * Routines for dealing with the cache. 94 */ 95void cache_init(phandle_t); /* turn it on */ 96void icache_flush(vm_offset_t, vm_offset_t); 97void icache_inval_phys(vm_offset_t, vm_offset_t); 98void dcache_flush(vm_offset_t, vm_offset_t); 99void dcache_inval(pmap_t, vm_offset_t, vm_offset_t); 100void dcache_inval_phys(vm_offset_t, vm_offset_t); 101void dcache_blast(void); 102void ecache_flush(vm_offset_t, vm_offset_t); 103#if 0 104void ecache_inval_phys(vm_offset_t, vm_offset_t); 105#endif 106 107void dcache_page_inval(vm_offset_t pa); 108void icache_page_inval(vm_offset_t pa); 109 | |
| 110#define DC_TAG_SHIFT 2 111#define DC_VALID_SHIFT 0 112 113#define DC_TAG_BITS 28 114#define DC_VALID_BITS 2 115 116#define DC_TAG_MASK ((1 << DC_TAG_BITS) - 1) 117#define DC_VALID_MASK ((1 << DC_VALID_BITS) - 1) --- 23 unchanged lines hidden (view full) --- 141 u_int dc_linesize; 142 u_int ec_size; /* external cache info */ 143 u_int ec_assoc; 144 u_int ec_l2set; 145 u_int ec_linesize; 146 u_int ec_l2linesize; 147}; 148 | 59#define DC_TAG_SHIFT 2 60#define DC_VALID_SHIFT 0 61 62#define DC_TAG_BITS 28 63#define DC_VALID_BITS 2 64 65#define DC_TAG_MASK ((1 << DC_TAG_BITS) - 1) 66#define DC_VALID_MASK ((1 << DC_VALID_BITS) - 1) --- 23 unchanged lines hidden (view full) --- 90 u_int dc_linesize; 91 u_int ec_size; /* external cache info */ 92 u_int ec_assoc; 93 u_int ec_l2set; 94 u_int ec_linesize; 95 u_int ec_l2linesize; 96}; 97 |
| 98typedef void dcache_page_inval_t(vm_offset_t pa); 99typedef void icache_page_inval_t(vm_offset_t pa); 100 101void cache_init(phandle_t node); 102 103void cheetah_dcache_page_inval(vm_offset_t pa); 104void cheetah_icache_page_inval(vm_offset_t pa); 105void spitfire_dcache_page_inval(vm_offset_t pa); 106void spitfire_icache_page_inval(vm_offset_t pa); 107 108extern dcache_page_inval_t *dcache_page_inval; 109extern icache_page_inval_t *icache_page_inval; 110 |
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| 149extern struct cacheinfo cache; 150 151#endif /* !_MACHINE_CACHE_H_ */ | 111extern struct cacheinfo cache; 112 113#endif /* !_MACHINE_CACHE_H_ */ |