| pcibus.h (225394) | pcibus.h (227722) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/hal/pcibus.h 225394 2011-09-05 10:45:29Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/hal/pcibus.h 227722 2011-11-19 14:06:15Z jchandra $ |
| 30 */ 31 32#ifndef __XLP_PCIBUS_H__ | 30 */ 31 32#ifndef __XLP_PCIBUS_H__ |
| 33#define __XLP_PCIBUS_H__ | 33#define __XLP_PCIBUS_H__ |
| 34 | 34 |
| 35#define MSI_MIPS_ADDR_BASE 0xfee00000 | 35#define MSI_MIPS_ADDR_BASE 0xfee00000 |
| 36/* MSI support */ | 36/* MSI support */ |
| 37#define MSI_MIPS_ADDR_DEST 0x000ff000 38#define MSI_MIPS_ADDR_RH 0x00000008 39#define MSI_MIPS_ADDR_RH_OFF 0x00000000 40#define MSI_MIPS_ADDR_RH_ON 0x00000008 41#define MSI_MIPS_ADDR_DM 0x00000004 42#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 43#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 | 37#define MSI_MIPS_ADDR_DEST 0x000ff000 38#define MSI_MIPS_ADDR_RH 0x00000008 39#define MSI_MIPS_ADDR_RH_OFF 0x00000000 40#define MSI_MIPS_ADDR_RH_ON 0x00000008 41#define MSI_MIPS_ADDR_DM 0x00000004 42#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 43#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 |
| 44 45/* Fields in data for Intel MSI messages. */ | 44 45/* Fields in data for Intel MSI messages. */ |
| 46#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ 47#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ 48#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ | 46#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ 47#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ 48#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ |
| 49 | 49 |
| 50#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ 51#define MSI_MIPS_DATA_DEASSERT 0x00000000 52#define MSI_MIPS_DATA_ASSERT 0x00004000 | 50#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ 51#define MSI_MIPS_DATA_DEASSERT 0x00000000 52#define MSI_MIPS_DATA_ASSERT 0x00004000 |
| 53 | 53 |
| 54#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ 55#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ 56#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ | 54#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ 55#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ 56#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ |
| 57 | 57 |
| 58#define MSI_MIPS_DATA_INTVEC 0x000000ff | 58#define MSI_MIPS_DATA_INTVEC 0x000000ff |
| 59 60/* 61 * Build Intel MSI message and data values from a source. AMD64 systems 62 * seem to be compatible, so we use the same function for both. 63 */ | 59 60/* 61 * Build Intel MSI message and data values from a source. AMD64 systems 62 * seem to be compatible, so we use the same function for both. 63 */ |
| 64#define MIPS_MSI_ADDR(cpu) \ 65 (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \ 66 MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL) | 64#define MIPS_MSI_ADDR(cpu) \ 65 (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \ 66 MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL) |
| 67 | 67 |
| 68#define MIPS_MSI_DATA(irq) \ 69 (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \ 70 MSI_MIPS_DATA_ASSERT | (irq)) | 68#define MIPS_MSI_DATA(irq) \ 69 (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \ 70 MSI_MIPS_DATA_ASSERT | (irq)) |
| 71 | 71 |
| 72#define PCIE_BRIDGE_CMD 0x1 73#define PCIE_BRIDGE_MSI_CAP 0x14 74#define PCIE_BRIDGE_MSI_ADDRL 0x15 75#define PCIE_BRIDGE_MSI_ADDRH 0x16 76#define PCIE_BRIDGE_MSI_DATA 0x17 | 72#define PCIE_BRIDGE_CMD 0x1 73#define PCIE_BRIDGE_MSI_CAP 0x14 74#define PCIE_BRIDGE_MSI_ADDRL 0x15 75#define PCIE_BRIDGE_MSI_ADDRH 0x16 76#define PCIE_BRIDGE_MSI_DATA 0x17 |
| 77 78/* XLP Global PCIE configuration space registers */ | 77 78/* XLP Global PCIE configuration space registers */ |
| 79#define PCIE_MSI_STATUS 0x25A 80#define PCIE_MSI_EN 0x25B 81#define PCIE_INT_EN0 0x261 | 79#define PCIE_MSI_STATUS 0x25A 80#define PCIE_MSI_EN 0x25B 81#define PCIE_INT_EN0 0x261 |
| 82 83/* PCIE_MSI_EN */ | 82 83/* PCIE_MSI_EN */ |
| 84#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF | 84#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF |
| 85 86/* PCIE_INT_EN0 */ | 85 86/* PCIE_INT_EN0 */ |
| 87#define PCIE_MSI_INT_EN (1 << 9) | 87#define PCIE_MSI_INT_EN (1 << 9) |
| 88 89#endif /* __XLP_PCIBUS_H__ */ | 88 89#endif /* __XLP_PCIBUS_H__ */ |