1/*-
2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar933x_chip.c 253508 2013-07-21 03:52:52Z adrian $");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar933xreg.h>
56
57#include <mips/atheros/ar71xx_cpudef.h>
58#include <mips/atheros/ar71xx_setup.h>
59
60#include <mips/atheros/ar71xx_chip.h>
61#include <mips/atheros/ar933x_chip.h>
62
63static void
64ar933x_chip_detect_mem_size(void)
65{
66}
67
68static void
69ar933x_chip_detect_sys_frequency(void)
70{
71 uint32_t clock_ctrl;
72 uint32_t cpu_config;
73 uint32_t freq;
74 uint32_t t;
75
76 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
77 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
78 u_ar71xx_refclk = (40 * 1000 * 1000);
79 else
80 u_ar71xx_refclk = (25 * 1000 * 1000);
81
82 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
83 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
84 u_ar71xx_cpu_freq = u_ar71xx_refclk;
85 u_ar71xx_ahb_freq = u_ar71xx_refclk;
86 u_ar71xx_ddr_freq = u_ar71xx_refclk;
87 } else {
88 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
89
90 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
92 freq = u_ar71xx_refclk / t;
93
94 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
95 AR933X_PLL_CPU_CONFIG_NINT_MASK;
96 freq *= t;
97
98 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
99 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
100 if (t == 0)
101 t = 1;
102
103 freq >>= t;
104
105 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
106 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
107 u_ar71xx_cpu_freq = freq / t;
108
109 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
110 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
111 u_ar71xx_ddr_freq = freq / t;
112
113 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
114 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
115 u_ar71xx_ahb_freq = freq / t;
116 }
117
118 /* XXX uart should be the refclk, no? */
119 u_ar71xx_uart_freq = u_ar71xx_ahb_freq;
120 u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
121}
122
123static void
124ar933x_chip_device_stop(uint32_t mask)
125{
126 uint32_t reg;
127
128 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
129 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
130}
131
132static void
133ar933x_chip_device_start(uint32_t mask)
134{
135 uint32_t reg;
136
137 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
138 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
139}
140
141static int
142ar933x_chip_device_stopped(uint32_t mask)
143{
144 uint32_t reg;
145
146 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
147 return ((reg & mask) == mask);
148}
149
150static void
151ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
152{
153
154 /* XXX TODO */
155 return;
156}
157
158/*
159 * XXX TODO !!
160 */
161static void
162ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
163{
164
165 switch (unit) {
166 case 0:
167 /* XXX TODO */
168 break;
169 case 1:
170 /* XXX TODO */
171 break;
172 default:
173 printf("%s: invalid PLL set for arge unit: %d\n",
174 __func__, unit);
175 return;
176 }
177}
178
179static void
180ar933x_chip_ddr_flush_ge(int unit)
181{
182
183 switch (unit) {
184 case 0:
185 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
186 break;
187 case 1:
188 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
189 break;
190 default:
191 printf("%s: invalid DDR flush for arge unit: %d\n",
192 __func__, unit);
193 return;
194 }
195}
196
197static void
198ar933x_chip_ddr_flush_ip2(void)
199{
200
201 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
202}
203
204static uint32_t
205ar933x_chip_get_eth_pll(unsigned int mac, int speed)
206{
207 uint32_t pll;
208
209 switch (speed) {
210 case 10:
211 pll = AR933X_PLL_VAL_10;
212 break;
213 case 100:
214 pll = AR933X_PLL_VAL_100;
215 break;
216 case 1000:
217 pll = AR933X_PLL_VAL_1000;
218 break;
219 default:
220 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
221 pll = 0;
222 }
223 return (pll);
224}
225
226static void
227ar933x_chip_init_usb_peripheral(void)
228{
229 ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
230 DELAY(100);
231
232 ar71xx_device_start(AR933X_RESET_USB_HOST);
233 DELAY(100);
234
235 ar71xx_device_start(AR933X_RESET_USB_PHY);
236 DELAY(100);
237}
238
239struct ar71xx_cpu_def ar933x_chip_def = {
240 &ar933x_chip_detect_mem_size,
241 &ar933x_chip_detect_sys_frequency,
242 &ar933x_chip_device_stop,
243 &ar933x_chip_device_start,
244 &ar933x_chip_device_stopped,
245 &ar933x_chip_set_pll_ge,
246 &ar933x_chip_set_mii_speed,
247 &ar71xx_chip_set_mii_if,
248 &ar933x_chip_ddr_flush_ge,
249 &ar933x_chip_get_eth_pll,
250 &ar933x_chip_ddr_flush_ip2,
251 &ar933x_chip_init_usb_peripheral
252};