| ia64_cpu.h (67032) | ia64_cpu.h (67522) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 67032 2000-10-12 17:47:01Z dfr $ | 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 67522 2000-10-24 19:54:38Z dfr $ |
| 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 96 unchanged lines hidden (view full) --- 131 * Manipulating region bits of an address. 132 */ 133#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61) 134#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1)) 135 136#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6)) 137#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7)) 138 | 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 96 unchanged lines hidden (view full) --- 131 * Manipulating region bits of an address. 132 */ 133#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61) 134#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1)) 135 136#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6)) 137#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7)) 138 |
| 139#ifndef LOCORE 140 |
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| 139/* 140 * Various special ia64 instructions. 141 */ 142 143/* 144 * Memory Fence. 145 */ 146static __inline void --- 275 unchanged lines hidden (view full) --- 422 * Write a region register. 423 */ 424static __inline void 425ia64_set_rr(u_int64_t rrbase, u_int64_t v) 426{ 427 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory"); 428} 429 | 141/* 142 * Various special ia64 instructions. 143 */ 144 145/* 146 * Memory Fence. 147 */ 148static __inline void --- 275 unchanged lines hidden (view full) --- 424 * Write a region register. 425 */ 426static __inline void 427ia64_set_rr(u_int64_t rrbase, u_int64_t v) 428{ 429 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory"); 430} 431 |
| 432#endif 433 |
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| 430#endif /* _MACHINE_IA64_CPU_H_ */ 431 | 434#endif /* _MACHINE_IA64_CPU_H_ */ 435 |