| ia64_cpu.h (66937) | ia64_cpu.h (67032) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 66937 2000-10-10 14:57:10Z dfr $ | 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 67032 2000-10-12 17:47:01Z dfr $ |
| 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 370 unchanged lines hidden (view full) --- 405 */ 406static __inline void 407ia64_set_itm(u_int64_t v) 408{ 409 __asm __volatile("mov cr.itm=%0" :: "r" (v)); 410} 411 412/* | 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 370 unchanged lines hidden (view full) --- 405 */ 406static __inline void 407ia64_set_itm(u_int64_t v) 408{ 409 __asm __volatile("mov cr.itm=%0" :: "r" (v)); 410} 411 412/* |
| 413 * Write the value of ar.itv. 414 */ 415static __inline void 416ia64_set_itv(u_int64_t v) 417{ 418 __asm __volatile("mov cr.itv=%0" :: "r" (v)); 419} 420 421/* |
|
| 413 * Write a region register. 414 */ 415static __inline void 416ia64_set_rr(u_int64_t rrbase, u_int64_t v) 417{ 418 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory"); 419} 420 421#endif /* _MACHINE_IA64_CPU_H_ */ 422 | 422 * Write a region register. 423 */ 424static __inline void 425ia64_set_rr(u_int64_t rrbase, u_int64_t v) 426{ 427 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory"); 428} 429 430#endif /* _MACHINE_IA64_CPU_H_ */ 431 |