1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 83622 2001-09-18 15:21:18Z dfr $
| 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 83766 2001-09-21 10:09:27Z dfr $
|
27 */
28
29#ifndef _MACHINE_IA64_CPU_H_
30#define _MACHINE_IA64_CPU_H_
31
32/*
33 * Definition of PSR and IPSR bits.
34 */
35#define IA64_PSR_BE 0x0000000000000002
36#define IA64_PSR_UP 0x0000000000000004
37#define IA64_PSR_AC 0x0000000000000008
38#define IA64_PSR_MFL 0x0000000000000010
39#define IA64_PSR_MFH 0x0000000000000020
40#define IA64_PSR_IC 0x0000000000002000
41#define IA64_PSR_I 0x0000000000004000
42#define IA64_PSR_PK 0x0000000000008000
43#define IA64_PSR_DT 0x0000000000020000
44#define IA64_PSR_DFL 0x0000000000040000
45#define IA64_PSR_DFH 0x0000000000080000
46#define IA64_PSR_SP 0x0000000000100000
47#define IA64_PSR_PP 0x0000000000200000
48#define IA64_PSR_DI 0x0000000000400000
49#define IA64_PSR_SI 0x0000000000800000
50#define IA64_PSR_DB 0x0000000001000000
51#define IA64_PSR_LP 0x0000000002000000
52#define IA64_PSR_TB 0x0000000004000000
53#define IA64_PSR_RT 0x0000000008000000
54#define IA64_PSR_CPL 0x0000000300000000
55#define IA64_PSR_CPL_KERN 0x0000000000000000
56#define IA64_PSR_CPL_1 0x0000000100000000
57#define IA64_PSR_CPL_2 0x0000000200000000
58#define IA64_PSR_CPL_USER 0x0000000300000000
59#define IA64_PSR_IS 0x0000000400000000
60#define IA64_PSR_MC 0x0000000800000000
61#define IA64_PSR_IT 0x0000001000000000
62#define IA64_PSR_ID 0x0000002000000000
63#define IA64_PSR_DA 0x0000004000000000
64#define IA64_PSR_DD 0x0000008000000000
65#define IA64_PSR_SS 0x0000010000000000
66#define IA64_PSR_RI 0x0000060000000000
67#define IA64_PSR_RI_0 0x0000000000000000
68#define IA64_PSR_RI_1 0x0000020000000000
69#define IA64_PSR_RI_2 0x0000040000000000
70#define IA64_PSR_ED 0x0000080000000000
71#define IA64_PSR_BN 0x0000100000000000
72#define IA64_PSR_IA 0x0000200000000000
73
74/*
75 * Definition of ISR bits.
76 */
77#define IA64_ISR_CODE 0x000000000000ffff
78#define IA64_ISR_VECTOR 0x0000000000ff0000
79#define IA64_ISR_X 0x0000000100000000
80#define IA64_ISR_W 0x0000000200000000
81#define IA64_ISR_R 0x0000000400000000
82#define IA64_ISR_NA 0x0000000800000000
83#define IA64_ISR_SP 0x0000001000000000
84#define IA64_ISR_RS 0x0000002000000000
85#define IA64_ISR_IR 0x0000004000000000
86#define IA64_ISR_NI 0x0000008000000000
87#define IA64_ISR_SO 0x0000010000000000
88#define IA64_ISR_EI 0x0000060000000000
89#define IA64_ISR_EI_0 0x0000000000000000
90#define IA64_ISR_EI_1 0x0000020000000000
91#define IA64_ISR_EI_2 0x0000040000000000
92#define IA64_ISR_ED 0x0000080000000000
93
94/*
95 * Vector numbers for various ia64 interrupts.
96 */
97#define IA64_VEC_VHPT 0
98#define IA64_VEC_ITLB 1
99#define IA64_VEC_DTLB 2
100#define IA64_VEC_ALT_ITLB 3
101#define IA64_VEC_ALT_DTLB 4
102#define IA64_VEC_NESTED_DTLB 5
103#define IA64_VEC_IKEY_MISS 6
104#define IA64_VEC_DKEY_MISS 7
105#define IA64_VEC_DIRTY_BIT 8
106#define IA64_VEC_INST_ACCESS 9
107#define IA64_VEC_DATA_ACCESS 10
108#define IA64_VEC_BREAK 11
109#define IA64_VEC_EXT_INTR 12
110#define IA64_VEC_PAGE_NOT_PRESENT 20
111#define IA64_VEC_KEY_PERMISSION 21
112#define IA64_VEC_INST_ACCESS_RIGHTS 22
113#define IA64_VEC_DATA_ACCESS_RIGHTS 23
114#define IA64_VEC_GENERAL_EXCEPTION 24
115#define IA64_VEC_DISABLED_FP 25
116#define IA64_VEC_NAT_CONSUMPTION 26
117#define IA64_VEC_SPECULATION 27
118#define IA64_VEC_DEBUG 29
119#define IA64_VEC_UNALIGNED_REFERENCE 30
120#define IA64_VEC_UNSUPP_DATA_REFERENCE 31
121#define IA64_VEC_FLOATING_POINT_FAULT 32
122#define IA64_VEC_FLOATING_POINT_TRAP 33
123#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
124#define IA64_VEC_TAKEN_BRANCH_TRAP 35
125#define IA64_VEC_SINGLE_STEP_TRAP 36
126#define IA64_VEC_IA32_EXCEPTION 45
127#define IA64_VEC_IA32_INTERCEPT 46
128#define IA64_VEC_IA32_INTERRUPT 47
129
130/*
131 * Manipulating region bits of an address.
132 */
133#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61)
134#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
135
136#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
137#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
138
139#ifndef LOCORE
140
141/*
142 * Various special ia64 instructions.
143 */
144
145/*
146 * Memory Fence.
147 */
148static __inline void
149ia64_mf(void)
150{
151 __asm __volatile("mf");
152}
153
154static __inline void
155ia64_mf_a(void)
156{
157 __asm __volatile("mf.a");
158}
159
160/*
| 27 */
28
29#ifndef _MACHINE_IA64_CPU_H_
30#define _MACHINE_IA64_CPU_H_
31
32/*
33 * Definition of PSR and IPSR bits.
34 */
35#define IA64_PSR_BE 0x0000000000000002
36#define IA64_PSR_UP 0x0000000000000004
37#define IA64_PSR_AC 0x0000000000000008
38#define IA64_PSR_MFL 0x0000000000000010
39#define IA64_PSR_MFH 0x0000000000000020
40#define IA64_PSR_IC 0x0000000000002000
41#define IA64_PSR_I 0x0000000000004000
42#define IA64_PSR_PK 0x0000000000008000
43#define IA64_PSR_DT 0x0000000000020000
44#define IA64_PSR_DFL 0x0000000000040000
45#define IA64_PSR_DFH 0x0000000000080000
46#define IA64_PSR_SP 0x0000000000100000
47#define IA64_PSR_PP 0x0000000000200000
48#define IA64_PSR_DI 0x0000000000400000
49#define IA64_PSR_SI 0x0000000000800000
50#define IA64_PSR_DB 0x0000000001000000
51#define IA64_PSR_LP 0x0000000002000000
52#define IA64_PSR_TB 0x0000000004000000
53#define IA64_PSR_RT 0x0000000008000000
54#define IA64_PSR_CPL 0x0000000300000000
55#define IA64_PSR_CPL_KERN 0x0000000000000000
56#define IA64_PSR_CPL_1 0x0000000100000000
57#define IA64_PSR_CPL_2 0x0000000200000000
58#define IA64_PSR_CPL_USER 0x0000000300000000
59#define IA64_PSR_IS 0x0000000400000000
60#define IA64_PSR_MC 0x0000000800000000
61#define IA64_PSR_IT 0x0000001000000000
62#define IA64_PSR_ID 0x0000002000000000
63#define IA64_PSR_DA 0x0000004000000000
64#define IA64_PSR_DD 0x0000008000000000
65#define IA64_PSR_SS 0x0000010000000000
66#define IA64_PSR_RI 0x0000060000000000
67#define IA64_PSR_RI_0 0x0000000000000000
68#define IA64_PSR_RI_1 0x0000020000000000
69#define IA64_PSR_RI_2 0x0000040000000000
70#define IA64_PSR_ED 0x0000080000000000
71#define IA64_PSR_BN 0x0000100000000000
72#define IA64_PSR_IA 0x0000200000000000
73
74/*
75 * Definition of ISR bits.
76 */
77#define IA64_ISR_CODE 0x000000000000ffff
78#define IA64_ISR_VECTOR 0x0000000000ff0000
79#define IA64_ISR_X 0x0000000100000000
80#define IA64_ISR_W 0x0000000200000000
81#define IA64_ISR_R 0x0000000400000000
82#define IA64_ISR_NA 0x0000000800000000
83#define IA64_ISR_SP 0x0000001000000000
84#define IA64_ISR_RS 0x0000002000000000
85#define IA64_ISR_IR 0x0000004000000000
86#define IA64_ISR_NI 0x0000008000000000
87#define IA64_ISR_SO 0x0000010000000000
88#define IA64_ISR_EI 0x0000060000000000
89#define IA64_ISR_EI_0 0x0000000000000000
90#define IA64_ISR_EI_1 0x0000020000000000
91#define IA64_ISR_EI_2 0x0000040000000000
92#define IA64_ISR_ED 0x0000080000000000
93
94/*
95 * Vector numbers for various ia64 interrupts.
96 */
97#define IA64_VEC_VHPT 0
98#define IA64_VEC_ITLB 1
99#define IA64_VEC_DTLB 2
100#define IA64_VEC_ALT_ITLB 3
101#define IA64_VEC_ALT_DTLB 4
102#define IA64_VEC_NESTED_DTLB 5
103#define IA64_VEC_IKEY_MISS 6
104#define IA64_VEC_DKEY_MISS 7
105#define IA64_VEC_DIRTY_BIT 8
106#define IA64_VEC_INST_ACCESS 9
107#define IA64_VEC_DATA_ACCESS 10
108#define IA64_VEC_BREAK 11
109#define IA64_VEC_EXT_INTR 12
110#define IA64_VEC_PAGE_NOT_PRESENT 20
111#define IA64_VEC_KEY_PERMISSION 21
112#define IA64_VEC_INST_ACCESS_RIGHTS 22
113#define IA64_VEC_DATA_ACCESS_RIGHTS 23
114#define IA64_VEC_GENERAL_EXCEPTION 24
115#define IA64_VEC_DISABLED_FP 25
116#define IA64_VEC_NAT_CONSUMPTION 26
117#define IA64_VEC_SPECULATION 27
118#define IA64_VEC_DEBUG 29
119#define IA64_VEC_UNALIGNED_REFERENCE 30
120#define IA64_VEC_UNSUPP_DATA_REFERENCE 31
121#define IA64_VEC_FLOATING_POINT_FAULT 32
122#define IA64_VEC_FLOATING_POINT_TRAP 33
123#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
124#define IA64_VEC_TAKEN_BRANCH_TRAP 35
125#define IA64_VEC_SINGLE_STEP_TRAP 36
126#define IA64_VEC_IA32_EXCEPTION 45
127#define IA64_VEC_IA32_INTERCEPT 46
128#define IA64_VEC_IA32_INTERRUPT 47
129
130/*
131 * Manipulating region bits of an address.
132 */
133#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61)
134#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
135
136#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
137#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
138
139#ifndef LOCORE
140
141/*
142 * Various special ia64 instructions.
143 */
144
145/*
146 * Memory Fence.
147 */
148static __inline void
149ia64_mf(void)
150{
151 __asm __volatile("mf");
152}
153
154static __inline void
155ia64_mf_a(void)
156{
157 __asm __volatile("mf.a");
158}
159
160/*
|
| 161 * Flush Cache.
162 */
163static __inline void
164ia64_fc(u_int64_t va)
165{
166 __asm __volatile("fc %0" :: "r"(va));
167}
168
169/*
|
161 * Calculate address in VHPT for va.
162 */
163static __inline u_int64_t
164ia64_thash(u_int64_t va)
165{
166 u_int64_t result;
167 __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
168 return result;
169}
170
171/*
172 * Calculate VHPT tag for va.
173 */
174static __inline u_int64_t
175ia64_ttag(u_int64_t va)
176{
177 u_int64_t result;
178 __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
179 return result;
180}
181
182/*
183 * Convert virtual address to physical.
184 */
185static __inline u_int64_t
186ia64_tpa(u_int64_t va)
187{
188 u_int64_t result;
189 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
190 return result;
191}
192
193/*
194 * Generate a ptc.e instruction.
195 */
196static __inline void
197ia64_ptc_e(u_int64_t v)
198{
199 __asm __volatile("ptc.e %0;;" :: "r"(v));
200}
201
202/*
203 * Generate a ptc.g instruction.
204 */
205static __inline void
206ia64_ptc_g(u_int64_t va, u_int64_t log2size)
207{
208 __asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size));
209}
210
211/*
212 * Generate a ptc.ga instruction.
213 */
214static __inline void
215ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
216{
217 __asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size));
218}
219
220/*
221 * Generate a ptc.l instruction.
222 */
223static __inline void
224ia64_ptc_l(u_int64_t va, u_int64_t log2size)
225{
226 __asm __volatile("ptc.l %0,%1;;" :: "r"(va), "r"(log2size));
227}
228
229/*
230 * Read the value of psr.
231 */
232static __inline u_int64_t
233ia64_get_psr(void)
234{
235 u_int64_t result;
236 __asm __volatile("mov %0=psr;;" : "=r" (result));
237 return result;
238}
239
240/*
241 * Read the value of ar.k0.
242 */
243static __inline u_int64_t
244ia64_get_k0(void)
245{
246 u_int64_t result;
247 __asm __volatile("mov %0=ar.k0" : "=r" (result));
248 return result;
249}
250
251/*
252 * Read the value of ar.k1.
253 */
254static __inline u_int64_t
255ia64_get_k1(void)
256{
257 u_int64_t result;
258 __asm __volatile("mov %0=ar.k1" : "=r" (result));
259 return result;
260}
261
262/*
263 * Read the value of ar.k2.
264 */
265static __inline u_int64_t
266ia64_get_k2(void)
267{
268 u_int64_t result;
269 __asm __volatile("mov %0=ar.k2" : "=r" (result));
270 return result;
271}
272
273/*
274 * Read the value of ar.k3.
275 */
276static __inline u_int64_t
277ia64_get_k3(void)
278{
279 u_int64_t result;
280 __asm __volatile("mov %0=ar.k3" : "=r" (result));
281 return result;
282}
283
284/*
285 * Read the value of ar.k4.
286 */
287static __inline u_int64_t
288ia64_get_k4(void)
289{
290 u_int64_t result;
291 __asm __volatile("mov %0=ar.k4" : "=r" (result));
292 return result;
293}
294
295/*
296 * Read the value of ar.k5.
297 */
298static __inline u_int64_t
299ia64_get_k5(void)
300{
301 u_int64_t result;
302 __asm __volatile("mov %0=ar.k5" : "=r" (result));
303 return result;
304}
305
306/*
307 * Read the value of ar.k6.
308 */
309static __inline u_int64_t
310ia64_get_k6(void)
311{
312 u_int64_t result;
313 __asm __volatile("mov %0=ar.k6" : "=r" (result));
314 return result;
315}
316
317/*
318 * Read the value of ar.k7.
319 */
320static __inline u_int64_t
321ia64_get_k7(void)
322{
323 u_int64_t result;
324 __asm __volatile("mov %0=ar.k7" : "=r" (result));
325 return result;
326}
327
328/*
329 * Write the value of ar.k0.
330 */
331static __inline void
332ia64_set_k0(u_int64_t v)
333{
334 __asm __volatile("mov ar.k0=%0" :: "r" (v));
335}
336
337/*
338 * Write the value of ar.k1.
339 */
340static __inline void
341ia64_set_k1(u_int64_t v)
342{
343 __asm __volatile("mov ar.k1=%0" :: "r" (v));
344}
345
346/*
347 * Write the value of ar.k2.
348 */
349static __inline void
350ia64_set_k2(u_int64_t v)
351{
352 __asm __volatile("mov ar.k2=%0" :: "r" (v));
353}
354
355/*
356 * Write the value of ar.k3.
357 */
358static __inline void
359ia64_set_k3(u_int64_t v)
360{
361 __asm __volatile("mov ar.k3=%0" :: "r" (v));
362}
363
364/*
365 * Write the value of ar.k4.
366 */
367static __inline void
368ia64_set_k4(u_int64_t v)
369{
370 __asm __volatile("mov ar.k4=%0" :: "r" (v));
371}
372
373/*
374 * Write the value of ar.k5.
375 */
376static __inline void
377ia64_set_k5(u_int64_t v)
378{
379 __asm __volatile("mov ar.k5=%0" :: "r" (v));
380}
381
382/*
383 * Write the value of ar.k6.
384 */
385static __inline void
386ia64_set_k6(u_int64_t v)
387{
388 __asm __volatile("mov ar.k6=%0" :: "r" (v));
389}
390
391/*
392 * Write the value of ar.k7.
393 */
394static __inline void
395ia64_set_k7(u_int64_t v)
396{
397 __asm __volatile("mov ar.k7=%0" :: "r" (v));
398}
399
400/*
401 * Read the value of ar.itc.
402 */
403static __inline u_int64_t
404ia64_get_itc(void)
405{
406 u_int64_t result;
407 __asm __volatile("mov %0=ar.itc" : "=r" (result));
408 return result;
409}
410
411/*
412 * Read the value of ar.itm.
413 */
414static __inline u_int64_t
415ia64_get_itm(void)
416{
417 u_int64_t result;
418 __asm __volatile("mov %0=cr.itm" : "=r" (result));
419 return result;
420}
421
422/*
423 * Write the value of ar.itm.
424 */
425static __inline void
426ia64_set_itm(u_int64_t v)
427{
428 __asm __volatile("mov cr.itm=%0" :: "r" (v));
429}
430
431/*
432 * Write the value of ar.itv.
433 */
434static __inline void
435ia64_set_itv(u_int64_t v)
436{
437 __asm __volatile("mov cr.itv=%0" :: "r" (v));
438}
439
440/*
441 * Write a region register.
442 */
443static __inline void
444ia64_set_rr(u_int64_t rrbase, u_int64_t v)
445{
446 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory");
447}
448
449/*
450 * Read a CPUID register.
451 */
452static __inline u_int64_t
453ia64_get_cpuid(int i)
454{
455 u_int64_t result;
456 __asm __volatile("mov %0=cpuid[%1]"
457 : "=r" (result) : "r"(i));
458 return result;
459}
460
461#endif
462
463#endif /* _MACHINE_IA64_CPU_H_ */
464
| 170 * Calculate address in VHPT for va.
171 */
172static __inline u_int64_t
173ia64_thash(u_int64_t va)
174{
175 u_int64_t result;
176 __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
177 return result;
178}
179
180/*
181 * Calculate VHPT tag for va.
182 */
183static __inline u_int64_t
184ia64_ttag(u_int64_t va)
185{
186 u_int64_t result;
187 __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
188 return result;
189}
190
191/*
192 * Convert virtual address to physical.
193 */
194static __inline u_int64_t
195ia64_tpa(u_int64_t va)
196{
197 u_int64_t result;
198 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
199 return result;
200}
201
202/*
203 * Generate a ptc.e instruction.
204 */
205static __inline void
206ia64_ptc_e(u_int64_t v)
207{
208 __asm __volatile("ptc.e %0;;" :: "r"(v));
209}
210
211/*
212 * Generate a ptc.g instruction.
213 */
214static __inline void
215ia64_ptc_g(u_int64_t va, u_int64_t log2size)
216{
217 __asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size));
218}
219
220/*
221 * Generate a ptc.ga instruction.
222 */
223static __inline void
224ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
225{
226 __asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size));
227}
228
229/*
230 * Generate a ptc.l instruction.
231 */
232static __inline void
233ia64_ptc_l(u_int64_t va, u_int64_t log2size)
234{
235 __asm __volatile("ptc.l %0,%1;;" :: "r"(va), "r"(log2size));
236}
237
238/*
239 * Read the value of psr.
240 */
241static __inline u_int64_t
242ia64_get_psr(void)
243{
244 u_int64_t result;
245 __asm __volatile("mov %0=psr;;" : "=r" (result));
246 return result;
247}
248
249/*
250 * Read the value of ar.k0.
251 */
252static __inline u_int64_t
253ia64_get_k0(void)
254{
255 u_int64_t result;
256 __asm __volatile("mov %0=ar.k0" : "=r" (result));
257 return result;
258}
259
260/*
261 * Read the value of ar.k1.
262 */
263static __inline u_int64_t
264ia64_get_k1(void)
265{
266 u_int64_t result;
267 __asm __volatile("mov %0=ar.k1" : "=r" (result));
268 return result;
269}
270
271/*
272 * Read the value of ar.k2.
273 */
274static __inline u_int64_t
275ia64_get_k2(void)
276{
277 u_int64_t result;
278 __asm __volatile("mov %0=ar.k2" : "=r" (result));
279 return result;
280}
281
282/*
283 * Read the value of ar.k3.
284 */
285static __inline u_int64_t
286ia64_get_k3(void)
287{
288 u_int64_t result;
289 __asm __volatile("mov %0=ar.k3" : "=r" (result));
290 return result;
291}
292
293/*
294 * Read the value of ar.k4.
295 */
296static __inline u_int64_t
297ia64_get_k4(void)
298{
299 u_int64_t result;
300 __asm __volatile("mov %0=ar.k4" : "=r" (result));
301 return result;
302}
303
304/*
305 * Read the value of ar.k5.
306 */
307static __inline u_int64_t
308ia64_get_k5(void)
309{
310 u_int64_t result;
311 __asm __volatile("mov %0=ar.k5" : "=r" (result));
312 return result;
313}
314
315/*
316 * Read the value of ar.k6.
317 */
318static __inline u_int64_t
319ia64_get_k6(void)
320{
321 u_int64_t result;
322 __asm __volatile("mov %0=ar.k6" : "=r" (result));
323 return result;
324}
325
326/*
327 * Read the value of ar.k7.
328 */
329static __inline u_int64_t
330ia64_get_k7(void)
331{
332 u_int64_t result;
333 __asm __volatile("mov %0=ar.k7" : "=r" (result));
334 return result;
335}
336
337/*
338 * Write the value of ar.k0.
339 */
340static __inline void
341ia64_set_k0(u_int64_t v)
342{
343 __asm __volatile("mov ar.k0=%0" :: "r" (v));
344}
345
346/*
347 * Write the value of ar.k1.
348 */
349static __inline void
350ia64_set_k1(u_int64_t v)
351{
352 __asm __volatile("mov ar.k1=%0" :: "r" (v));
353}
354
355/*
356 * Write the value of ar.k2.
357 */
358static __inline void
359ia64_set_k2(u_int64_t v)
360{
361 __asm __volatile("mov ar.k2=%0" :: "r" (v));
362}
363
364/*
365 * Write the value of ar.k3.
366 */
367static __inline void
368ia64_set_k3(u_int64_t v)
369{
370 __asm __volatile("mov ar.k3=%0" :: "r" (v));
371}
372
373/*
374 * Write the value of ar.k4.
375 */
376static __inline void
377ia64_set_k4(u_int64_t v)
378{
379 __asm __volatile("mov ar.k4=%0" :: "r" (v));
380}
381
382/*
383 * Write the value of ar.k5.
384 */
385static __inline void
386ia64_set_k5(u_int64_t v)
387{
388 __asm __volatile("mov ar.k5=%0" :: "r" (v));
389}
390
391/*
392 * Write the value of ar.k6.
393 */
394static __inline void
395ia64_set_k6(u_int64_t v)
396{
397 __asm __volatile("mov ar.k6=%0" :: "r" (v));
398}
399
400/*
401 * Write the value of ar.k7.
402 */
403static __inline void
404ia64_set_k7(u_int64_t v)
405{
406 __asm __volatile("mov ar.k7=%0" :: "r" (v));
407}
408
409/*
410 * Read the value of ar.itc.
411 */
412static __inline u_int64_t
413ia64_get_itc(void)
414{
415 u_int64_t result;
416 __asm __volatile("mov %0=ar.itc" : "=r" (result));
417 return result;
418}
419
420/*
421 * Read the value of ar.itm.
422 */
423static __inline u_int64_t
424ia64_get_itm(void)
425{
426 u_int64_t result;
427 __asm __volatile("mov %0=cr.itm" : "=r" (result));
428 return result;
429}
430
431/*
432 * Write the value of ar.itm.
433 */
434static __inline void
435ia64_set_itm(u_int64_t v)
436{
437 __asm __volatile("mov cr.itm=%0" :: "r" (v));
438}
439
440/*
441 * Write the value of ar.itv.
442 */
443static __inline void
444ia64_set_itv(u_int64_t v)
445{
446 __asm __volatile("mov cr.itv=%0" :: "r" (v));
447}
448
449/*
450 * Write a region register.
451 */
452static __inline void
453ia64_set_rr(u_int64_t rrbase, u_int64_t v)
454{
455 __asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory");
456}
457
458/*
459 * Read a CPUID register.
460 */
461static __inline u_int64_t
462ia64_get_cpuid(int i)
463{
464 u_int64_t result;
465 __asm __volatile("mov %0=cpuid[%1]"
466 : "=r" (result) : "r"(i));
467 return result;
468}
469
470#endif
471
472#endif /* _MACHINE_IA64_CPU_H_ */
473
|