| if_wbreg.h (199560) | if_wbreg.h (226995) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/wb/if_wbreg.h 199560 2009-11-19 22:14:23Z jhb $ | 32 * $FreeBSD: head/sys/dev/wb/if_wbreg.h 226995 2011-11-01 16:13:59Z marius $ |
| 33 */ 34 35/* 36 * Winbond register definitions. 37 */ 38 39#define WB_BUSCTL 0x00 /* bus control */ 40#define WB_TXSTART 0x04 /* tx start demand */ --- 295 unchanged lines hidden (view full) --- 336 struct wb_chain *wb_tx_head; 337 struct wb_chain *wb_tx_tail; 338 struct wb_chain *wb_tx_free; 339}; 340 341struct wb_type { 342 u_int16_t wb_vid; 343 u_int16_t wb_did; | 33 */ 34 35/* 36 * Winbond register definitions. 37 */ 38 39#define WB_BUSCTL 0x00 /* bus control */ 40#define WB_TXSTART 0x04 /* tx start demand */ --- 295 unchanged lines hidden (view full) --- 336 struct wb_chain *wb_tx_head; 337 struct wb_chain *wb_tx_tail; 338 struct wb_chain *wb_tx_free; 339}; 340 341struct wb_type { 342 u_int16_t wb_vid; 343 u_int16_t wb_did; |
| 344 char *wb_name; | 344 const char *wb_name; |
| 345}; 346 | 345}; 346 |
| 347struct wb_mii_frame { 348 u_int8_t mii_stdelim; 349 u_int8_t mii_opcode; 350 u_int8_t mii_phyaddr; 351 u_int8_t mii_regaddr; 352 u_int8_t mii_turnaround; 353 u_int16_t mii_data; 354}; 355 356/* 357 * MII constants 358 */ 359#define WB_MII_STARTDELIM 0x01 360#define WB_MII_READOP 0x02 361#define WB_MII_WRITEOP 0x01 362#define WB_MII_TURNAROUND 0x02 363 | |
| 364struct wb_softc { 365 struct ifnet *wb_ifp; /* interface info */ 366 device_t wb_dev; 367 device_t wb_miibus; 368 struct resource *wb_res; 369 struct resource *wb_irq; 370 void *wb_intrhand; 371 struct wb_type *wb_info; /* Winbond adapter info */ --- 18 unchanged lines hidden (view full) --- 390#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->wb_res, reg, val) 391#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val) 392#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->wb_res, reg, val) 393 394#define CSR_READ_4(sc, reg) bus_read_4(sc->wb_res, reg) 395#define CSR_READ_2(sc, reg) bus_read_2(sc->wb_res, reg) 396#define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg) 397 | 347struct wb_softc { 348 struct ifnet *wb_ifp; /* interface info */ 349 device_t wb_dev; 350 device_t wb_miibus; 351 struct resource *wb_res; 352 struct resource *wb_irq; 353 void *wb_intrhand; 354 struct wb_type *wb_info; /* Winbond adapter info */ --- 18 unchanged lines hidden (view full) --- 373#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->wb_res, reg, val) 374#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val) 375#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->wb_res, reg, val) 376 377#define CSR_READ_4(sc, reg) bus_read_4(sc->wb_res, reg) 378#define CSR_READ_2(sc, reg) bus_read_2(sc->wb_res, reg) 379#define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg) 380 |
| 381#define CSR_BARRIER(sc, reg, length, flags) \ 382 bus_barrier(sc->wb_res, reg, length, flags) 383 |
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| 398#define WB_TIMEOUT 1000 399 400/* 401 * General constants that are fun to know. 402 * 403 * Winbond PCI vendor ID 404 */ 405#define WB_VENDORID 0x1050 --- 52 unchanged lines hidden --- | 384#define WB_TIMEOUT 1000 385 386/* 387 * General constants that are fun to know. 388 * 389 * Winbond PCI vendor ID 390 */ 391#define WB_VENDORID 0x1050 --- 52 unchanged lines hidden --- |