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if_axereg.h (187378) if_axereg.h (188412)
1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_axereg.h 187378 2009-01-18 05:35:58Z thompsa $
32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_axereg.h 188412 2009-02-09 22:02:38Z thompsa $
33 */
34
35/*
36 * Definitions for the ASIX Electronics AX88172, AX88178
37 * and AX88772 to ethernet controllers.
38 */
39
40/*

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161#define AXE_CONFIG_IDX 0 /* config number 1 */
162#define AXE_IFACE_IDX 0
163
164struct axe_sframe_hdr {
165 uint16_t len;
166 uint16_t ilen;
167} __packed;
168
33 */
34
35/*
36 * Definitions for the ASIX Electronics AX88172, AX88178
37 * and AX88772 to ethernet controllers.
38 */
39
40/*

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161#define AXE_CONFIG_IDX 0 /* config number 1 */
162#define AXE_IFACE_IDX 0
163
164struct axe_sframe_hdr {
165 uint16_t len;
166 uint16_t ilen;
167} __packed;
168
169#define GET_MII(sc) ((sc)->sc_miibus ? \
170 device_get_softc((sc)->sc_miibus) : NULL)
169#define GET_MII(sc) usb2_ether_getmii(&(sc)->sc_ue)
171
172/* The interrupt endpoint is currently unused by the ASIX part. */
173enum {
174 AXE_BULK_DT_WR,
175 AXE_BULK_DT_RD,
170
171/* The interrupt endpoint is currently unused by the ASIX part. */
172enum {
173 AXE_BULK_DT_WR,
174 AXE_BULK_DT_RD,
176 AXE_BULK_CS_WR,
177 AXE_BULK_CS_RD,
178 AXE_INTR_DT_RD,
175 AXE_INTR_DT_RD,
179 AXE_INTR_CS_RD,
180 AXE_N_TRANSFER = 6,
176 AXE_N_TRANSFER,
181};
182
183struct axe_softc {
177};
178
179struct axe_softc {
184 struct ifnet *sc_ifp;
180 struct usb2_ether sc_ue;
181 struct mtx sc_mtx;
182 struct usb2_xfer *sc_xfer[AXE_N_TRANSFER];
183 int sc_phyno;
185
184
186 struct usb2_config_td sc_config_td;
187 struct usb2_callout sc_watchdog;
188 struct mtx sc_mtx;
189
190 struct usb2_device *sc_udev;
191 struct usb2_xfer *sc_xfer[AXE_N_TRANSFER];
192 device_t sc_miibus;
193 device_t sc_dev;
194
195 int sc_phyno;
196
197 uint32_t sc_unit;
198 uint32_t sc_media_active;
199 uint32_t sc_media_status;
200
201 uint16_t sc_flags;
185 int sc_flags;
202#define AXE_FLAG_LINK 0x0001
186#define AXE_FLAG_LINK 0x0001
203#define AXE_FLAG_INTR_STALL 0x0002
204#define AXE_FLAG_READ_STALL 0x0004
205#define AXE_FLAG_WRITE_STALL 0x0008
206#define AXE_FLAG_LL_READY 0x0010
207#define AXE_FLAG_HL_READY 0x0020
208#define AXE_FLAG_772 0x0040 /* AX88772 */
209#define AXE_FLAG_178 0x0080 /* AX88178 */
187#define AXE_FLAG_772 0x1000 /* AX88772 */
188#define AXE_FLAG_178 0x2000 /* AX88178 */
210
189
211 uint8_t sc_ipgs[3];
212 uint8_t sc_phyaddrs[2];
213
214 uint8_t sc_name[16];
190 uint8_t sc_ipgs[3];
191 uint8_t sc_phyaddrs[2];
215};
192};
193
194#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
195#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
196#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)