| if_auereg.h (187378) | if_auereg.h (188412) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_auereg.h 187378 2009-01-18 05:35:58Z thompsa $ | 32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_auereg.h 188412 2009-02-09 22:02:38Z thompsa $ |
| 33 */ 34 35/* 36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 37 * chip. The Pegasus uses a total of four USB endpoints: the control 38 * endpoint (0), a bulk read endpoint for receiving packets (1), 39 * a bulk write endpoint for sending packets (2) and an interrupt 40 * endpoint for passing RX and TX status (3). Endpoint 0 is used 41 * to read and write the ethernet module's registers. All registers 42 * are 8 bits wide. 43 * 44 * Packet transfer is done in 64 byte chunks. The last chunk in a | 33 */ 34 35/* 36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 37 * chip. The Pegasus uses a total of four USB endpoints: the control 38 * endpoint (0), a bulk read endpoint for receiving packets (1), 39 * a bulk write endpoint for sending packets (2) and an interrupt 40 * endpoint for passing RX and TX status (3). Endpoint 0 is used 41 * to read and write the ethernet module's registers. All registers 42 * are 8 bits wide. 43 * 44 * Packet transfer is done in 64 byte chunks. The last chunk in a |
| 45 * transfer is denoted by having a length less that 64 bytes. For | 45 * transfer is denoted by having a length less that 64 bytes. For |
| 46 * the RX case, the data includes an optional RX status word. 47 */ 48 49#define AUE_UR_READREG 0xF0 50#define AUE_UR_WRITEREG 0xF1 51 52#define AUE_CONFIG_INDEX 0 /* config number 1 */ 53#define AUE_IFACE_IDX 0 --- 4 unchanged lines hidden (view full) --- 58 * don't have direct access to it (we access it using usb2_do_request() 59 * when reading/writing registers. Consequently, our endpoint indexes 60 * don't match those in the ADMtek Pegasus manual: we consider the RX data 61 * endpoint to be index 0 and work up from there. 62 */ 63enum { 64 AUE_BULK_DT_WR, 65 AUE_BULK_DT_RD, | 46 * the RX case, the data includes an optional RX status word. 47 */ 48 49#define AUE_UR_READREG 0xF0 50#define AUE_UR_WRITEREG 0xF1 51 52#define AUE_CONFIG_INDEX 0 /* config number 1 */ 53#define AUE_IFACE_IDX 0 --- 4 unchanged lines hidden (view full) --- 58 * don't have direct access to it (we access it using usb2_do_request() 59 * when reading/writing registers. Consequently, our endpoint indexes 60 * don't match those in the ADMtek Pegasus manual: we consider the RX data 61 * endpoint to be index 0 and work up from there. 62 */ 63enum { 64 AUE_BULK_DT_WR, 65 AUE_BULK_DT_RD, |
| 66 AUE_BULK_CS_WR, 67 AUE_BULK_CS_RD, | |
| 68 AUE_INTR_DT_RD, | 66 AUE_INTR_DT_RD, |
| 69 AUE_INTR_CS_RD, 70 AUE_N_TRANSFER = 6, | 67 AUE_N_TRANSFER, |
| 71}; 72 73#define AUE_INTR_PKTLEN 0x8 74 75#define AUE_CTL0 0x00 76#define AUE_CTL1 0x01 77#define AUE_CTL2 0x02 78#define AUE_MAR0 0x08 --- 102 unchanged lines hidden (view full) --- 181 182#define AUE_RXSTAT_MCAST 0x01 183#define AUE_RXSTAT_GIANT 0x02 184#define AUE_RXSTAT_RUNT 0x04 185#define AUE_RXSTAT_CRCERR 0x08 186#define AUE_RXSTAT_DRIBBLE 0x10 187#define AUE_RXSTAT_MASK 0x1E 188 | 68}; 69 70#define AUE_INTR_PKTLEN 0x8 71 72#define AUE_CTL0 0x00 73#define AUE_CTL1 0x01 74#define AUE_CTL2 0x02 75#define AUE_MAR0 0x08 --- 102 unchanged lines hidden (view full) --- 178 179#define AUE_RXSTAT_MCAST 0x01 180#define AUE_RXSTAT_GIANT 0x02 181#define AUE_RXSTAT_RUNT 0x04 182#define AUE_RXSTAT_CRCERR 0x08 183#define AUE_RXSTAT_DRIBBLE 0x10 184#define AUE_RXSTAT_MASK 0x1E 185 |
| 189#define GET_MII(sc) ((sc)->sc_miibus ? \ 190 device_get_softc((sc)->sc_miibus) : NULL) | 186#define GET_MII(sc) usb2_ether_getmii(&(sc)->sc_ue) |
| 191 192struct aue_intrpkt { 193 uint8_t aue_txstat0; 194 uint8_t aue_txstat1; 195 uint8_t aue_rxstat; 196 uint8_t aue_rxlostpkt0; 197 uint8_t aue_rxlostpkt1; 198 uint8_t aue_wakeupstat; 199 uint8_t aue_rsvd; 200} __packed; 201 202struct aue_rxpkt { 203 uint16_t aue_pktlen; 204 uint8_t aue_rxstat; | 187 188struct aue_intrpkt { 189 uint8_t aue_txstat0; 190 uint8_t aue_txstat1; 191 uint8_t aue_rxstat; 192 uint8_t aue_rxlostpkt0; 193 uint8_t aue_rxlostpkt1; 194 uint8_t aue_wakeupstat; 195 uint8_t aue_rsvd; 196} __packed; 197 198struct aue_rxpkt { 199 uint16_t aue_pktlen; 200 uint8_t aue_rxstat; |
| 201 uint8_t pad; |
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| 205} __packed; 206 207struct aue_softc { | 202} __packed; 203 204struct aue_softc { |
| 208 struct ifnet *sc_ifp; | 205 struct usb2_ether sc_ue; 206 struct mtx sc_mtx; 207 struct usb2_xfer *sc_xfer[AUE_N_TRANSFER]; |
| 209 | 208 |
| 210 struct usb2_config_td sc_config_td; 211 struct usb2_callout sc_watchdog; 212 struct mtx sc_mtx; 213 struct aue_rxpkt sc_rxpkt; 214 215 struct usb2_device *sc_udev; 216 struct usb2_xfer *sc_xfer[AUE_N_TRANSFER]; 217 device_t sc_miibus; 218 device_t sc_dev; 219 220 uint32_t sc_unit; 221 uint32_t sc_media_active; 222 uint32_t sc_media_status; 223 224 uint16_t sc_flags; | 209 int sc_flags; |
| 225#define AUE_FLAG_LSYS 0x0001 /* use Linksys reset */ 226#define AUE_FLAG_PNA 0x0002 /* has Home PNA */ 227#define AUE_FLAG_PII 0x0004 /* Pegasus II chip */ | 210#define AUE_FLAG_LSYS 0x0001 /* use Linksys reset */ 211#define AUE_FLAG_PNA 0x0002 /* has Home PNA */ 212#define AUE_FLAG_PII 0x0004 /* Pegasus II chip */ |
| 228#define AUE_FLAG_WAIT_LINK 0x0008 /* wait for link to come up */ 229#define AUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ 230#define AUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ 231#define AUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ 232#define AUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ 233#define AUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ | 213#define AUE_FLAG_LINK 0x0008 /* wait for link to come up */ |
| 234#define AUE_FLAG_VER_2 0x0200 /* chip is version 2 */ 235#define AUE_FLAG_DUAL_PHY 0x0400 /* chip has two transcivers */ | 214#define AUE_FLAG_VER_2 0x0200 /* chip is version 2 */ 215#define AUE_FLAG_DUAL_PHY 0x0400 /* chip has two transcivers */ |
| 236 237 uint8_t sc_name[16]; | |
| 238}; | 216}; |
| 217 218#define AUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 219#define AUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 220#define AUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) |
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