1#include <sys/cdefs.h>
2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/atmegadci.c 241082 2012-10-01 05:42:43Z hselasky $");
3
4/*-
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * This file contains the driver for the ATMEGA series USB OTG Controller. This
31 * driver currently only supports the DCI mode of the USB hardware.
32 */
33
34/*
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
37 */
38
39#include <sys/stdint.h>
40#include <sys/stddef.h>
41#include <sys/param.h>
42#include <sys/queue.h>
43#include <sys/types.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/bus.h>
47#include <sys/module.h>
48#include <sys/lock.h>
49#include <sys/mutex.h>
50#include <sys/condvar.h>
51#include <sys/sysctl.h>
52#include <sys/sx.h>
53#include <sys/unistd.h>
54#include <sys/callout.h>
55#include <sys/malloc.h>
56#include <sys/priv.h>
57
58#include <dev/usb/usb.h>
59#include <dev/usb/usbdi.h>
60
61#define USB_DEBUG_VAR atmegadci_debug
62
63#include <dev/usb/usb_core.h>
64#include <dev/usb/usb_debug.h>
65#include <dev/usb/usb_busdma.h>
66#include <dev/usb/usb_process.h>
67#include <dev/usb/usb_transfer.h>
68#include <dev/usb/usb_device.h>
69#include <dev/usb/usb_hub.h>
70#include <dev/usb/usb_util.h>
71
72#include <dev/usb/usb_controller.h>
73#include <dev/usb/usb_bus.h>
74#include <dev/usb/controller/atmegadci.h>
75
76#define ATMEGA_BUS2SC(bus) \
77 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
78 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
79
80#define ATMEGA_PC2SC(pc) \
81 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
82
83#ifdef USB_DEBUG
84static int atmegadci_debug = 0;
85
86static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0,
87 "USB ATMEGA DCI");
88SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
89 &atmegadci_debug, 0, "ATMEGA DCI debug level");
90#endif
91
92#define ATMEGA_INTR_ENDPT 1
93
94/* prototypes */
95
96struct usb_bus_methods atmegadci_bus_methods;
97struct usb_pipe_methods atmegadci_device_non_isoc_methods;
98struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
99
100static atmegadci_cmd_t atmegadci_setup_rx;
101static atmegadci_cmd_t atmegadci_data_rx;
102static atmegadci_cmd_t atmegadci_data_tx;
103static atmegadci_cmd_t atmegadci_data_tx_sync;
104static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
105static void atmegadci_do_poll(struct usb_bus *);
106static void atmegadci_standard_done(struct usb_xfer *);
107static void atmegadci_root_intr(struct atmegadci_softc *sc);
108
109/*
110 * Here is a list of what the chip supports:
111 */
112static const struct usb_hw_ep_profile
113 atmegadci_ep_profile[2] = {
114
115 [0] = {
116 .max_in_frame_size = 64,
117 .max_out_frame_size = 64,
118 .is_simplex = 1,
119 .support_control = 1,
120 },
121 [1] = {
122 .max_in_frame_size = 64,
123 .max_out_frame_size = 64,
124 .is_simplex = 1,
125 .support_bulk = 1,
126 .support_interrupt = 1,
127 .support_isochronous = 1,
128 .support_in = 1,
129 .support_out = 1,
130 },
131};
132
133static void
134atmegadci_get_hw_ep_profile(struct usb_device *udev,
135 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
136{
137 if (ep_addr == 0)
138 *ppf = atmegadci_ep_profile;
139 else if (ep_addr < ATMEGA_EP_MAX)
140 *ppf = atmegadci_ep_profile + 1;
141 else
142 *ppf = NULL;
143}
144
145static void
146atmegadci_clocks_on(struct atmegadci_softc *sc)
147{
148 if (sc->sc_flags.clocks_off &&
149 sc->sc_flags.port_powered) {
150
151 DPRINTFN(5, "\n");
152
153 /* turn on clocks */
154 (sc->sc_clocks_on) (&sc->sc_bus);
155
156 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
157 ATMEGA_USBCON_USBE |
158 ATMEGA_USBCON_OTGPADE |
159 ATMEGA_USBCON_VBUSTE);
160
161 sc->sc_flags.clocks_off = 0;
162
163 /* enable transceiver ? */
164 }
165}
166
167static void
168atmegadci_clocks_off(struct atmegadci_softc *sc)
169{
170 if (!sc->sc_flags.clocks_off) {
171
172 DPRINTFN(5, "\n");
173
174 /* disable Transceiver ? */
175
176 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
177 ATMEGA_USBCON_USBE |
178 ATMEGA_USBCON_OTGPADE |
179 ATMEGA_USBCON_FRZCLK |
180 ATMEGA_USBCON_VBUSTE);
181
182 /* turn clocks off */
183 (sc->sc_clocks_off) (&sc->sc_bus);
184
185 sc->sc_flags.clocks_off = 1;
186 }
187}
188
189static void
190atmegadci_pull_up(struct atmegadci_softc *sc)
191{
192 /* pullup D+, if possible */
193
194 if (!sc->sc_flags.d_pulled_up &&
195 sc->sc_flags.port_powered) {
196 sc->sc_flags.d_pulled_up = 1;
197 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
198 }
199}
200
201static void
202atmegadci_pull_down(struct atmegadci_softc *sc)
203{
204 /* pulldown D+, if possible */
205
206 if (sc->sc_flags.d_pulled_up) {
207 sc->sc_flags.d_pulled_up = 0;
208 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
209 }
210}
211
212static void
213atmegadci_wakeup_peer(struct atmegadci_softc *sc)
214{
215 uint8_t temp;
216
217 if (!sc->sc_flags.status_suspend) {
218 return;
219 }
220
221 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
222 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
223
224 /* wait 8 milliseconds */
225 /* Wait for reset to complete. */
226 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
227
228 /* hardware should have cleared RMWKUP bit */
229}
230
231static void
232atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
233{
234 DPRINTFN(5, "addr=%d\n", addr);
235
236 addr |= ATMEGA_UDADDR_ADDEN;
237
238 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
239}
240
241static uint8_t
242atmegadci_setup_rx(struct atmegadci_td *td)
243{
244 struct atmegadci_softc *sc;
245 struct usb_device_request req;
246 uint16_t count;
247 uint8_t temp;
248
249 /* get pointer to softc */
250 sc = ATMEGA_PC2SC(td->pc);
251
252 /* select endpoint number */
253 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
254
255 /* check endpoint status */
256 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
257
258 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
259
260 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
261 goto not_complete;
262 }
263 /* clear did stall */
264 td->did_stall = 0;
265 /* get the packet byte count */
266 count =
267 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
268 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
269
270 /* mask away undefined bits */
271 count &= 0x7FF;
272
273 /* verify data length */
274 if (count != td->remainder) {
275 DPRINTFN(0, "Invalid SETUP packet "
276 "length, %d bytes\n", count);
277 goto not_complete;
278 }
279 if (count != sizeof(req)) {
280 DPRINTFN(0, "Unsupported SETUP packet "
281 "length, %d bytes\n", count);
282 goto not_complete;
283 }
284 /* receive data */
285 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
286 (void *)&req, sizeof(req));
287
288 /* copy data into real buffer */
289 usbd_copy_in(td->pc, 0, &req, sizeof(req));
290
291 td->offset = sizeof(req);
292 td->remainder = 0;
293
294 /* sneak peek the set address */
295 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
296 (req.bRequest == UR_SET_ADDRESS)) {
297 sc->sc_dv_addr = req.wValue[0] & 0x7F;
298 /* must write address before ZLP */
299 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
300 } else {
301 sc->sc_dv_addr = 0xFF;
302 }
303
304 /* Clear SETUP packet interrupt and all other previous interrupts */
305 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
306 return (0); /* complete */
307
308not_complete:
309 /* abort any ongoing transfer */
310 if (!td->did_stall) {
311 DPRINTFN(5, "stalling\n");
312 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
313 ATMEGA_UECONX_EPEN |
314 ATMEGA_UECONX_STALLRQ);
315 td->did_stall = 1;
316 }
317 if (temp & ATMEGA_UEINTX_RXSTPI) {
318 /* clear SETUP packet interrupt */
319 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
320 }
321 /* we only want to know if there is a SETUP packet */
322 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
323 return (1); /* not complete */
324}
325
326static uint8_t
327atmegadci_data_rx(struct atmegadci_td *td)
328{
329 struct atmegadci_softc *sc;
330 struct usb_page_search buf_res;
331 uint16_t count;
332 uint8_t temp;
333 uint8_t to;
334 uint8_t got_short;
335
336 to = 3; /* don't loop forever! */
337 got_short = 0;
338
339 /* get pointer to softc */
340 sc = ATMEGA_PC2SC(td->pc);
341
342 /* select endpoint number */
343 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
344
345repeat:
346 /* check if any of the FIFO banks have data */
347 /* check endpoint status */
348 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
349
350 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
351
352 if (temp & ATMEGA_UEINTX_RXSTPI) {
353 if (td->remainder == 0) {
354 /*
355 * We are actually complete and have
356 * received the next SETUP
357 */
358 DPRINTFN(5, "faking complete\n");
359 return (0); /* complete */
360 }
361 /*
362 * USB Host Aborted the transfer.
363 */
364 td->error = 1;
365 return (0); /* complete */
366 }
367 /* check status */
368 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
369 ATMEGA_UEINTX_RXOUTI))) {
370 /* no data */
371 goto not_complete;
372 }
373 /* get the packet byte count */
374 count =
375 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
376 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
377
378 /* mask away undefined bits */
379 count &= 0x7FF;
380
381 /* verify the packet byte count */
382 if (count != td->max_packet_size) {
383 if (count < td->max_packet_size) {
384 /* we have a short packet */
385 td->short_pkt = 1;
386 got_short = 1;
387 } else {
388 /* invalid USB packet */
389 td->error = 1;
390 return (0); /* we are complete */
391 }
392 }
393 /* verify the packet byte count */
394 if (count > td->remainder) {
395 /* invalid USB packet */
396 td->error = 1;
397 return (0); /* we are complete */
398 }
399 while (count > 0) {
400 usbd_get_page(td->pc, td->offset, &buf_res);
401
402 /* get correct length */
403 if (buf_res.length > count) {
404 buf_res.length = count;
405 }
406 /* receive data */
407 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
408 buf_res.buffer, buf_res.length);
409
410 /* update counters */
411 count -= buf_res.length;
412 td->offset += buf_res.length;
413 td->remainder -= buf_res.length;
414 }
415
416 /* clear OUT packet interrupt */
417 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
418
419 /* release FIFO bank */
420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
421
422 /* check if we are complete */
423 if ((td->remainder == 0) || got_short) {
424 if (td->short_pkt) {
425 /* we are complete */
426 return (0);
427 }
428 /* else need to receive a zero length packet */
429 }
430 if (--to) {
431 goto repeat;
432 }
433not_complete:
434 /* we only want to know if there is a SETUP packet or OUT packet */
435 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
436 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
437 return (1); /* not complete */
438}
439
440static uint8_t
441atmegadci_data_tx(struct atmegadci_td *td)
442{
443 struct atmegadci_softc *sc;
444 struct usb_page_search buf_res;
445 uint16_t count;
446 uint8_t to;
447 uint8_t temp;
448
449 to = 3; /* don't loop forever! */
450
451 /* get pointer to softc */
452 sc = ATMEGA_PC2SC(td->pc);
453
454 /* select endpoint number */
455 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
456
457repeat:
458
459 /* check endpoint status */
460 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
461
462 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
463
464 if (temp & ATMEGA_UEINTX_RXSTPI) {
465 /*
466 * The current transfer was aborted
467 * by the USB Host
468 */
469 td->error = 1;
470 return (0); /* complete */
471 }
472
473 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
474 if (temp & 3) {
475 /* cannot write any data - a bank is busy */
476 goto not_complete;
477 }
478
479 count = td->max_packet_size;
480 if (td->remainder < count) {
481 /* we have a short packet */
482 td->short_pkt = 1;
483 count = td->remainder;
484 }
485 while (count > 0) {
486
487 usbd_get_page(td->pc, td->offset, &buf_res);
488
489 /* get correct length */
490 if (buf_res.length > count) {
491 buf_res.length = count;
492 }
493 /* transmit data */
494 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
495 buf_res.buffer, buf_res.length);
496
497 /* update counters */
498 count -= buf_res.length;
499 td->offset += buf_res.length;
500 td->remainder -= buf_res.length;
501 }
502
503 /* clear IN packet interrupt */
504 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
505
506 /* allocate FIFO bank */
507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
508
509 /* check remainder */
510 if (td->remainder == 0) {
511 if (td->short_pkt) {
512 return (0); /* complete */
513 }
514 /* else we need to transmit a short packet */
515 }
516 if (--to) {
517 goto repeat;
518 }
519not_complete:
520 /* we only want to know if there is a SETUP packet or free IN packet */
521 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
522 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
523 return (1); /* not complete */
524}
525
526static uint8_t
527atmegadci_data_tx_sync(struct atmegadci_td *td)
528{
529 struct atmegadci_softc *sc;
530 uint8_t temp;
531
532 /* get pointer to softc */
533 sc = ATMEGA_PC2SC(td->pc);
534
535 /* select endpoint number */
536 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
537
538 /* check endpoint status */
539 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
540
541 DPRINTFN(5, "temp=0x%02x\n", temp);
542
543 if (temp & ATMEGA_UEINTX_RXSTPI) {
544 DPRINTFN(5, "faking complete\n");
545 /* Race condition */
546 return (0); /* complete */
547 }
548 /*
549 * The control endpoint has only got one bank, so if that bank
550 * is free the packet has been transferred!
551 */
552 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
553 if (temp & 3) {
554 /* cannot write any data - a bank is busy */
555 goto not_complete;
556 }
557 if (sc->sc_dv_addr != 0xFF) {
558 /* set new address */
559 atmegadci_set_address(sc, sc->sc_dv_addr);
560 }
561 return (0); /* complete */
562
563not_complete:
564 /* we only want to know if there is a SETUP packet or free IN packet */
565 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
566 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
567 return (1); /* not complete */
568}
569
570static uint8_t
571atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
572{
573 struct atmegadci_td *td;
574
575 DPRINTFN(9, "\n");
576
577 td = xfer->td_transfer_cache;
578 while (1) {
579 if ((td->func) (td)) {
580 /* operation in progress */
581 break;
582 }
583 if (((void *)td) == xfer->td_transfer_last) {
584 goto done;
585 }
586 if (td->error) {
587 goto done;
588 } else if (td->remainder > 0) {
589 /*
590 * We had a short transfer. If there is no alternate
591 * next, stop processing !
592 */
593 if (!td->alt_next) {
594 goto done;
595 }
596 }
597 /*
598 * Fetch the next transfer descriptor and transfer
599 * some flags to the next transfer descriptor
600 */
601 td = td->obj_next;
602 xfer->td_transfer_cache = td;
603 }
604 return (1); /* not complete */
605
606done:
607 /* compute all actual lengths */
608
609 atmegadci_standard_done(xfer);
610 return (0); /* complete */
611}
612
613static void
614atmegadci_interrupt_poll(struct atmegadci_softc *sc)
615{
616 struct usb_xfer *xfer;
617
618repeat:
619 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
620 if (!atmegadci_xfer_do_fifo(xfer)) {
621 /* queue has been modified */
622 goto repeat;
623 }
624 }
625}
626
627static void
628atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
629{
630 DPRINTFN(5, "vbus = %u\n", is_on);
631
632 if (is_on) {
633 if (!sc->sc_flags.status_vbus) {
634 sc->sc_flags.status_vbus = 1;
635
636 /* complete root HUB interrupt endpoint */
637
638 atmegadci_root_intr(sc);
639 }
640 } else {
641 if (sc->sc_flags.status_vbus) {
642 sc->sc_flags.status_vbus = 0;
643 sc->sc_flags.status_bus_reset = 0;
644 sc->sc_flags.status_suspend = 0;
645 sc->sc_flags.change_suspend = 0;
646 sc->sc_flags.change_connect = 1;
647
648 /* complete root HUB interrupt endpoint */
649
650 atmegadci_root_intr(sc);
651 }
652 }
653}
654
655void
656atmegadci_interrupt(struct atmegadci_softc *sc)
657{
658 uint8_t status;
659
660 USB_BUS_LOCK(&sc->sc_bus);
661
662 /* read interrupt status */
663 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
664
665 /* clear all set interrupts */
666 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
667
668 DPRINTFN(14, "UDINT=0x%02x\n", status);
669
670 /* check for any bus state change interrupts */
671 if (status & ATMEGA_UDINT_EORSTI) {
672
673 DPRINTFN(5, "end of reset\n");
674
675 /* set correct state */
676 sc->sc_flags.status_bus_reset = 1;
677 sc->sc_flags.status_suspend = 0;
678 sc->sc_flags.change_suspend = 0;
679 sc->sc_flags.change_connect = 1;
680
681 /* disable resume interrupt */
682 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
683 ATMEGA_UDINT_SUSPE |
684 ATMEGA_UDINT_EORSTE);
685
686 /* complete root HUB interrupt endpoint */
687 atmegadci_root_intr(sc);
688 }
689 /*
690 * If resume and suspend is set at the same time we interpret
691 * that like RESUME. Resume is set when there is at least 3
692 * milliseconds of inactivity on the USB BUS.
693 */
694 if (status & ATMEGA_UDINT_WAKEUPI) {
695
696 DPRINTFN(5, "resume interrupt\n");
697
698 if (sc->sc_flags.status_suspend) {
699 /* update status bits */
700 sc->sc_flags.status_suspend = 0;
701 sc->sc_flags.change_suspend = 1;
702
703 /* disable resume interrupt */
704 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
705 ATMEGA_UDINT_SUSPE |
706 ATMEGA_UDINT_EORSTE);
707
708 /* complete root HUB interrupt endpoint */
709 atmegadci_root_intr(sc);
710 }
711 } else if (status & ATMEGA_UDINT_SUSPI) {
712
713 DPRINTFN(5, "suspend interrupt\n");
714
715 if (!sc->sc_flags.status_suspend) {
716 /* update status bits */
717 sc->sc_flags.status_suspend = 1;
718 sc->sc_flags.change_suspend = 1;
719
720 /* disable suspend interrupt */
721 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
722 ATMEGA_UDINT_WAKEUPE |
723 ATMEGA_UDINT_EORSTE);
724
725 /* complete root HUB interrupt endpoint */
726 atmegadci_root_intr(sc);
727 }
728 }
729 /* check VBUS */
730 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
731
732 /* clear all set interrupts */
733 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
734
735 if (status & ATMEGA_USBINT_VBUSTI) {
736 uint8_t temp;
737
738 DPRINTFN(5, "USBINT=0x%02x\n", status);
739
740 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
741 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
742 }
743 /* check for any endpoint interrupts */
744 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
745 /* the hardware will clear the UEINT bits automatically */
746 if (status) {
747
748 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
749
750 atmegadci_interrupt_poll(sc);
751 }
752 USB_BUS_UNLOCK(&sc->sc_bus);
753}
754
755static void
756atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
757{
758 struct atmegadci_td *td;
759
760 /* get current Transfer Descriptor */
761 td = temp->td_next;
762 temp->td = td;
763
764 /* prepare for next TD */
765 temp->td_next = td->obj_next;
766
767 /* fill out the Transfer Descriptor */
768 td->func = temp->func;
769 td->pc = temp->pc;
770 td->offset = temp->offset;
771 td->remainder = temp->len;
772 td->error = 0;
773 td->did_stall = temp->did_stall;
774 td->short_pkt = temp->short_pkt;
775 td->alt_next = temp->setup_alt_next;
776}
777
778static void
779atmegadci_setup_standard_chain(struct usb_xfer *xfer)
780{
781 struct atmegadci_std_temp temp;
782 struct atmegadci_softc *sc;
783 struct atmegadci_td *td;
784 uint32_t x;
785 uint8_t ep_no;
786 uint8_t need_sync;
787
788 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
789 xfer->address, UE_GET_ADDR(xfer->endpointno),
790 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
791
792 temp.max_frame_size = xfer->max_frame_size;
793
794 td = xfer->td_start[0];
795 xfer->td_transfer_first = td;
796 xfer->td_transfer_cache = td;
797
798 /* setup temp */
799
800 temp.pc = NULL;
801 temp.td = NULL;
802 temp.td_next = xfer->td_start[0];
803 temp.offset = 0;
804 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
805 temp.did_stall = !xfer->flags_int.control_stall;
806
807 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
808 ep_no = (xfer->endpointno & UE_ADDR);
809
810 /* check if we should prepend a setup message */
811
812 if (xfer->flags_int.control_xfr) {
813 if (xfer->flags_int.control_hdr) {
814
815 temp.func = &atmegadci_setup_rx;
816 temp.len = xfer->frlengths[0];
817 temp.pc = xfer->frbuffers + 0;
818 temp.short_pkt = temp.len ? 1 : 0;
819 /* check for last frame */
820 if (xfer->nframes == 1) {
821 /* no STATUS stage yet, SETUP is last */
822 if (xfer->flags_int.control_act)
823 temp.setup_alt_next = 0;
824 }
825
826 atmegadci_setup_standard_chain_sub(&temp);
827 }
828 x = 1;
829 } else {
830 x = 0;
831 }
832
833 if (x != xfer->nframes) {
834 if (xfer->endpointno & UE_DIR_IN) {
835 temp.func = &atmegadci_data_tx;
836 need_sync = 1;
837 } else {
838 temp.func = &atmegadci_data_rx;
839 need_sync = 0;
840 }
841
842 /* setup "pc" pointer */
843 temp.pc = xfer->frbuffers + x;
844 } else {
845 need_sync = 0;
846 }
847 while (x != xfer->nframes) {
848
849 /* DATA0 / DATA1 message */
850
851 temp.len = xfer->frlengths[x];
852
853 x++;
854
855 if (x == xfer->nframes) {
856 if (xfer->flags_int.control_xfr) {
857 if (xfer->flags_int.control_act) {
858 temp.setup_alt_next = 0;
859 }
860 } else {
861 temp.setup_alt_next = 0;
862 }
863 }
864 if (temp.len == 0) {
865
866 /* make sure that we send an USB packet */
867
868 temp.short_pkt = 0;
869
870 } else {
871
872 /* regular data transfer */
873
874 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
875 }
876
877 atmegadci_setup_standard_chain_sub(&temp);
878
879 if (xfer->flags_int.isochronous_xfr) {
880 temp.offset += temp.len;
881 } else {
882 /* get next Page Cache pointer */
883 temp.pc = xfer->frbuffers + x;
884 }
885 }
886
887 if (xfer->flags_int.control_xfr) {
888
889 /* always setup a valid "pc" pointer for status and sync */
890 temp.pc = xfer->frbuffers + 0;
891 temp.len = 0;
892 temp.short_pkt = 0;
893 temp.setup_alt_next = 0;
894
895 /* check if we need to sync */
896 if (need_sync) {
897 /* we need a SYNC point after TX */
898 temp.func = &atmegadci_data_tx_sync;
899 atmegadci_setup_standard_chain_sub(&temp);
900 }
901
902 /* check if we should append a status stage */
903 if (!xfer->flags_int.control_act) {
904
905 /*
906 * Send a DATA1 message and invert the current
907 * endpoint direction.
908 */
909 if (xfer->endpointno & UE_DIR_IN) {
910 temp.func = &atmegadci_data_rx;
911 need_sync = 0;
912 } else {
913 temp.func = &atmegadci_data_tx;
914 need_sync = 1;
915 }
916
917 atmegadci_setup_standard_chain_sub(&temp);
918 if (need_sync) {
919 /* we need a SYNC point after TX */
920 temp.func = &atmegadci_data_tx_sync;
921 atmegadci_setup_standard_chain_sub(&temp);
922 }
923 }
924 }
925 /* must have at least one frame! */
926 td = temp.td;
927 xfer->td_transfer_last = td;
928}
929
930static void
931atmegadci_timeout(void *arg)
932{
933 struct usb_xfer *xfer = arg;
934
935 DPRINTF("xfer=%p\n", xfer);
936
937 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
938
939 /* transfer is transferred */
940 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
941}
942
943static void
944atmegadci_start_standard_chain(struct usb_xfer *xfer)
945{
946 DPRINTFN(9, "\n");
947
948 /* poll one time - will turn on interrupts */
949 if (atmegadci_xfer_do_fifo(xfer)) {
950
951 /* put transfer on interrupt queue */
952 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
953
954 /* start timeout, if any */
955 if (xfer->timeout != 0) {
956 usbd_transfer_timeout_ms(xfer,
957 &atmegadci_timeout, xfer->timeout);
958 }
959 }
960}
961
962static void
963atmegadci_root_intr(struct atmegadci_softc *sc)
964{
965 DPRINTFN(9, "\n");
966
967 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
968
969 /* set port bit */
970 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
971
972 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
973 sizeof(sc->sc_hub_idata));
974 }
975
976static usb_error_t
977atmegadci_standard_done_sub(struct usb_xfer *xfer)
978{
979 struct atmegadci_td *td;
980 uint32_t len;
981 uint8_t error;
982
983 DPRINTFN(9, "\n");
984
985 td = xfer->td_transfer_cache;
986
987 do {
988 len = td->remainder;
989
990 if (xfer->aframes != xfer->nframes) {
991 /*
992 * Verify the length and subtract
993 * the remainder from "frlengths[]":
994 */
995 if (len > xfer->frlengths[xfer->aframes]) {
996 td->error = 1;
997 } else {
998 xfer->frlengths[xfer->aframes] -= len;
999 }
1000 }
1001 /* Check for transfer error */
1002 if (td->error) {
1003 /* the transfer is finished */
1004 error = 1;
1005 td = NULL;
1006 break;
1007 }
1008 /* Check for short transfer */
1009 if (len > 0) {
1010 if (xfer->flags_int.short_frames_ok) {
1011 /* follow alt next */
1012 if (td->alt_next) {
1013 td = td->obj_next;
1014 } else {
1015 td = NULL;
1016 }
1017 } else {
1018 /* the transfer is finished */
1019 td = NULL;
1020 }
1021 error = 0;
1022 break;
1023 }
1024 td = td->obj_next;
1025
1026 /* this USB frame is complete */
1027 error = 0;
1028 break;
1029
1030 } while (0);
1031
1032 /* update transfer cache */
1033
1034 xfer->td_transfer_cache = td;
1035
1036 return (error ?
1037 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1038}
1039
1040static void
1041atmegadci_standard_done(struct usb_xfer *xfer)
1042{
1043 usb_error_t err = 0;
1044
1045 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1046 xfer, xfer->endpoint);
1047
1048 /* reset scanner */
1049
1050 xfer->td_transfer_cache = xfer->td_transfer_first;
1051
1052 if (xfer->flags_int.control_xfr) {
1053
1054 if (xfer->flags_int.control_hdr) {
1055
1056 err = atmegadci_standard_done_sub(xfer);
1057 }
1058 xfer->aframes = 1;
1059
1060 if (xfer->td_transfer_cache == NULL) {
1061 goto done;
1062 }
1063 }
1064 while (xfer->aframes != xfer->nframes) {
1065
1066 err = atmegadci_standard_done_sub(xfer);
1067 xfer->aframes++;
1068
1069 if (xfer->td_transfer_cache == NULL) {
1070 goto done;
1071 }
1072 }
1073
1074 if (xfer->flags_int.control_xfr &&
1075 !xfer->flags_int.control_act) {
1076
1077 err = atmegadci_standard_done_sub(xfer);
1078 }
1079done:
1080 atmegadci_device_done(xfer, err);
1081}
1082
1083/*------------------------------------------------------------------------*
1084 * atmegadci_device_done
1085 *
1086 * NOTE: this function can be called more than one time on the
1087 * same USB transfer!
1088 *------------------------------------------------------------------------*/
1089static void
1090atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1091{
1092 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1093 uint8_t ep_no;
1094
1095 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1096
1097 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1098 xfer, xfer->endpoint, error);
1099
1100 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1101 ep_no = (xfer->endpointno & UE_ADDR);
1102
1103 /* select endpoint number */
1104 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1105
1106 /* disable endpoint interrupt */
1107 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1108
1109 DPRINTFN(15, "disabled interrupts!\n");
1110 }
1111 /* dequeue transfer and start next transfer */
1112 usbd_transfer_done(xfer, error);
1113}
1114
1115static void
1116atmegadci_xfer_stall(struct usb_xfer *xfer)
1117{
1118 atmegadci_device_done(xfer, USB_ERR_STALLED);
1119}
1120
1121static void
1122atmegadci_set_stall(struct usb_device *udev,
1123 struct usb_endpoint *ep, uint8_t *did_stall)
1124{
1125 struct atmegadci_softc *sc;
1126 uint8_t ep_no;
1127
1128 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1129
1130 DPRINTFN(5, "endpoint=%p\n", ep);
1131
1132 sc = ATMEGA_BUS2SC(udev->bus);
1133 /* get endpoint number */
1134 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1135 /* select endpoint number */
1136 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1137 /* set stall */
1138 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1139 ATMEGA_UECONX_EPEN |
1140 ATMEGA_UECONX_STALLRQ);
1141}
1142
1143static void
1144atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1145 uint8_t ep_type, uint8_t ep_dir)
1146{
1147 uint8_t temp;
1148
1149 if (ep_type == UE_CONTROL) {
1150 /* clearing stall is not needed */
1151 return;
1152 }
1153 /* select endpoint number */
1154 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1155
1156 /* set endpoint reset */
1157 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1158
1159 /* clear endpoint reset */
1160 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1161
1162 /* set stall */
1163 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1164 ATMEGA_UECONX_EPEN |
1165 ATMEGA_UECONX_STALLRQ);
1166
1167 /* reset data toggle */
1168 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1169 ATMEGA_UECONX_EPEN |
1170 ATMEGA_UECONX_RSTDT);
1171
1172 /* clear stall */
1173 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1174 ATMEGA_UECONX_EPEN |
1175 ATMEGA_UECONX_STALLRQC);
1176
1177 do {
1178 if (ep_type == UE_BULK) {
1179 temp = ATMEGA_UECFG0X_EPTYPE2;
1180 } else if (ep_type == UE_INTERRUPT) {
1181 temp = ATMEGA_UECFG0X_EPTYPE3;
1182 } else {
1183 temp = ATMEGA_UECFG0X_EPTYPE1;
1184 }
1185 if (ep_dir & UE_DIR_IN) {
1186 temp |= ATMEGA_UECFG0X_EPDIR;
1187 }
1188 /* two banks, 64-bytes wMaxPacket */
1189 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1190 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1191 ATMEGA_UECFG1X_ALLOC |
1192 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1193 ATMEGA_UECFG1X_EPSIZE(3));
1194
1195 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1196 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1197 device_printf(sc->sc_bus.bdev,
1198 "Chip rejected configuration\n");
1199 }
1200 } while (0);
1201}
1202
1203static void
1204atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1205{
1206 struct atmegadci_softc *sc;
1207 struct usb_endpoint_descriptor *ed;
1208
1209 DPRINTFN(5, "endpoint=%p\n", ep);
1210
1211 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1212
1213 /* check mode */
1214 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1215 /* not supported */
1216 return;
1217 }
1218 /* get softc */
1219 sc = ATMEGA_BUS2SC(udev->bus);
1220
1221 /* get endpoint descriptor */
1222 ed = ep->edesc;
1223
1224 /* reset endpoint */
1225 atmegadci_clear_stall_sub(sc,
1226 (ed->bEndpointAddress & UE_ADDR),
1227 (ed->bmAttributes & UE_XFERTYPE),
1228 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1229}
1230
1231usb_error_t
1232atmegadci_init(struct atmegadci_softc *sc)
1233{
1234 uint8_t n;
1235
1236 DPRINTF("start\n");
1237
1238 /* set up the bus structure */
1239 sc->sc_bus.usbrev = USB_REV_1_1;
1240 sc->sc_bus.methods = &atmegadci_bus_methods;
1241
1242 USB_BUS_LOCK(&sc->sc_bus);
1243
1244 /* make sure USB is enabled */
1245 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1246 ATMEGA_USBCON_USBE |
1247 ATMEGA_USBCON_FRZCLK);
1248
1249 /* enable USB PAD regulator */
1250 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1251 ATMEGA_UHWCON_UVREGE |
1252 ATMEGA_UHWCON_UIMOD);
1253
1254 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1255 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1256
1257 /* wait for PLL to lock */
1258 for (n = 0; n != 20; n++) {
1259 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1260 break;
1261 /* wait a little bit for PLL to start */
1262 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1263 }
1264
1265 /* make sure USB is enabled */
1266 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1267 ATMEGA_USBCON_USBE |
1268 ATMEGA_USBCON_OTGPADE |
1269 ATMEGA_USBCON_VBUSTE);
1270
1271 /* turn on clocks */
1272 (sc->sc_clocks_on) (&sc->sc_bus);
1273
1274 /* make sure device is re-enumerated */
1275 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1276
1277 /* wait a little for things to stabilise */
1278 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1279
1280 /* enable interrupts */
1281 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1282 ATMEGA_UDINT_SUSPE |
1283 ATMEGA_UDINT_EORSTE);
1284
1285 /* reset all endpoints */
1286 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1287 (1 << ATMEGA_EP_MAX) - 1);
1288
1289 /* disable reset */
1290 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1291
1292 /* disable all endpoints */
1293 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1294
1295 /* select endpoint */
1296 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1297
1298 /* disable endpoint interrupt */
1299 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1300
1301 /* disable endpoint */
1302 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1303 }
1304
1305 /* turn off clocks */
1306
1307 atmegadci_clocks_off(sc);
1308
1309 /* read initial VBUS state */
1310
1311 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1312 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1313
1314 USB_BUS_UNLOCK(&sc->sc_bus);
1315
1316 /* catch any lost interrupts */
1317
1318 atmegadci_do_poll(&sc->sc_bus);
1319
1320 return (0); /* success */
1321}
1322
1323void
1324atmegadci_uninit(struct atmegadci_softc *sc)
1325{
1326 USB_BUS_LOCK(&sc->sc_bus);
1327
1328 /* turn on clocks */
1329 (sc->sc_clocks_on) (&sc->sc_bus);
1330
1331 /* disable interrupts */
1332 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1333
1334 /* reset all endpoints */
1335 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1336 (1 << ATMEGA_EP_MAX) - 1);
1337
1338 /* disable reset */
1339 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1340
1341 sc->sc_flags.port_powered = 0;
1342 sc->sc_flags.status_vbus = 0;
1343 sc->sc_flags.status_bus_reset = 0;
1344 sc->sc_flags.status_suspend = 0;
1345 sc->sc_flags.change_suspend = 0;
1346 sc->sc_flags.change_connect = 1;
1347
1348 atmegadci_pull_down(sc);
1349 atmegadci_clocks_off(sc);
1350
1351 /* disable USB PAD regulator */
1352 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1353
1354 USB_BUS_UNLOCK(&sc->sc_bus);
1355}
1356
1357static void
1358atmegadci_suspend(struct atmegadci_softc *sc)
1359{
1360 /* TODO */
1361}
1362
1363static void
1364atmegadci_resume(struct atmegadci_softc *sc)
1365{
1366 /* TODO */
1367}
1368
1369static void
1370atmegadci_do_poll(struct usb_bus *bus)
1371{
1372 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1373
1374 USB_BUS_LOCK(&sc->sc_bus);
1375 atmegadci_interrupt_poll(sc);
1376 USB_BUS_UNLOCK(&sc->sc_bus);
1377}
1378
1379/*------------------------------------------------------------------------*
1380 * at91dci bulk support
1381 * at91dci control support
1382 * at91dci interrupt support
1383 *------------------------------------------------------------------------*/
1384static void
1385atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1386{
1387 return;
1388}
1389
1390static void
1391atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1392{
1393 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1394}
1395
1396static void
1397atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1398{
1399 return;
1400}
1401
1402static void
1403atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1404{
1405 /* setup TDs */
1406 atmegadci_setup_standard_chain(xfer);
1407 atmegadci_start_standard_chain(xfer);
1408}
1409
1410struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1411{
1412 .open = atmegadci_device_non_isoc_open,
1413 .close = atmegadci_device_non_isoc_close,
1414 .enter = atmegadci_device_non_isoc_enter,
1415 .start = atmegadci_device_non_isoc_start,
1416};
1417
1418/*------------------------------------------------------------------------*
1419 * at91dci full speed isochronous support
1420 *------------------------------------------------------------------------*/
1421static void
1422atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1423{
1424 return;
1425}
1426
1427static void
1428atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1429{
1430 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1431}
1432
1433static void
1434atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1435{
1436 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1437 uint32_t temp;
1438 uint32_t nframes;
1439
1440 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1441 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1442
1443 /* get the current frame index */
1444
1445 nframes =
1446 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1447 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1448
1449 nframes &= ATMEGA_FRAME_MASK;
1450
1451 /*
1452 * check if the frame index is within the window where the frames
1453 * will be inserted
1454 */
1455 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1456
1457 if ((xfer->endpoint->is_synced == 0) ||
1458 (temp < xfer->nframes)) {
1459 /*
1460 * If there is data underflow or the pipe queue is
1461 * empty we schedule the transfer a few frames ahead
1462 * of the current frame position. Else two isochronous
1463 * transfers might overlap.
1464 */
1465 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1466 xfer->endpoint->is_synced = 1;
1467 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1468 }
1469 /*
1470 * compute how many milliseconds the insertion is ahead of the
1471 * current frame position:
1472 */
1473 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1474
1475 /*
1476 * pre-compute when the isochronous transfer will be finished:
1477 */
1478 xfer->isoc_time_complete =
1479 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1480 xfer->nframes;
1481
1482 /* compute frame number for next insertion */
1483 xfer->endpoint->isoc_next += xfer->nframes;
1484
1485 /* setup TDs */
1486 atmegadci_setup_standard_chain(xfer);
1487}
1488
1489static void
1490atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1491{
1492 /* start TD chain */
1493 atmegadci_start_standard_chain(xfer);
1494}
1495
1496struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1497{
1498 .open = atmegadci_device_isoc_fs_open,
1499 .close = atmegadci_device_isoc_fs_close,
1500 .enter = atmegadci_device_isoc_fs_enter,
1501 .start = atmegadci_device_isoc_fs_start,
1502};
1503
1504/*------------------------------------------------------------------------*
1505 * at91dci root control support
1506 *------------------------------------------------------------------------*
1507 * Simulate a hardware HUB by handling all the necessary requests.
1508 *------------------------------------------------------------------------*/
1509
1510static const struct usb_device_descriptor atmegadci_devd = {
1511 .bLength = sizeof(struct usb_device_descriptor),
1512 .bDescriptorType = UDESC_DEVICE,
1513 .bcdUSB = {0x00, 0x02},
1514 .bDeviceClass = UDCLASS_HUB,
1515 .bDeviceSubClass = UDSUBCLASS_HUB,
1516 .bDeviceProtocol = UDPROTO_FSHUB,
1517 .bMaxPacketSize = 64,
1518 .bcdDevice = {0x00, 0x01},
1519 .iManufacturer = 1,
1520 .iProduct = 2,
1521 .bNumConfigurations = 1,
1522};
1523
1524static const struct atmegadci_config_desc atmegadci_confd = {
1525 .confd = {
1526 .bLength = sizeof(struct usb_config_descriptor),
1527 .bDescriptorType = UDESC_CONFIG,
1528 .wTotalLength[0] = sizeof(atmegadci_confd),
1529 .bNumInterface = 1,
1530 .bConfigurationValue = 1,
1531 .iConfiguration = 0,
1532 .bmAttributes = UC_SELF_POWERED,
1533 .bMaxPower = 0,
1534 },
1535 .ifcd = {
1536 .bLength = sizeof(struct usb_interface_descriptor),
1537 .bDescriptorType = UDESC_INTERFACE,
1538 .bNumEndpoints = 1,
1539 .bInterfaceClass = UICLASS_HUB,
1540 .bInterfaceSubClass = UISUBCLASS_HUB,
1541 .bInterfaceProtocol = 0,
1542 },
1543 .endpd = {
1544 .bLength = sizeof(struct usb_endpoint_descriptor),
1545 .bDescriptorType = UDESC_ENDPOINT,
1546 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1547 .bmAttributes = UE_INTERRUPT,
1548 .wMaxPacketSize[0] = 8,
1549 .bInterval = 255,
1550 },
1551};
1552
1553#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1554
1555static const struct usb_hub_descriptor_min atmegadci_hubd = {
1556 .bDescLength = sizeof(atmegadci_hubd),
1557 .bDescriptorType = UDESC_HUB,
1558 .bNbrPorts = 1,
1559 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1560 .bPwrOn2PwrGood = 50,
1561 .bHubContrCurrent = 0,
1562 .DeviceRemovable = {0}, /* port is removable */
1563};
1564
1565#define STRING_LANG \
1566 0x09, 0x04, /* American English */
1567
1568#define STRING_VENDOR \
1569 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0
1570
1571#define STRING_PRODUCT \
1572 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1573 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1574 'U', 0, 'B', 0,
1575
1576USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab);
1577USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1578USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1579
1580static usb_error_t
1581atmegadci_roothub_exec(struct usb_device *udev,
1582 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1583{
1584 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1585 const void *ptr;
1586 uint16_t len;
1587 uint16_t value;
1588 uint16_t index;
1589 uint8_t temp;
1590 usb_error_t err;
1591
1592 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1593
1594 /* buffer reset */
1595 ptr = (const void *)&sc->sc_hub_temp;
1596 len = 0;
1597 err = 0;
1598
1599 value = UGETW(req->wValue);
1600 index = UGETW(req->wIndex);
1601
1602 /* demultiplex the control request */
1603
1604 switch (req->bmRequestType) {
1605 case UT_READ_DEVICE:
1606 switch (req->bRequest) {
1607 case UR_GET_DESCRIPTOR:
1608 goto tr_handle_get_descriptor;
1609 case UR_GET_CONFIG:
1610 goto tr_handle_get_config;
1611 case UR_GET_STATUS:
1612 goto tr_handle_get_status;
1613 default:
1614 goto tr_stalled;
1615 }
1616 break;
1617
1618 case UT_WRITE_DEVICE:
1619 switch (req->bRequest) {
1620 case UR_SET_ADDRESS:
1621 goto tr_handle_set_address;
1622 case UR_SET_CONFIG:
1623 goto tr_handle_set_config;
1624 case UR_CLEAR_FEATURE:
1625 goto tr_valid; /* nop */
1626 case UR_SET_DESCRIPTOR:
1627 goto tr_valid; /* nop */
1628 case UR_SET_FEATURE:
1629 default:
1630 goto tr_stalled;
1631 }
1632 break;
1633
1634 case UT_WRITE_ENDPOINT:
1635 switch (req->bRequest) {
1636 case UR_CLEAR_FEATURE:
1637 switch (UGETW(req->wValue)) {
1638 case UF_ENDPOINT_HALT:
1639 goto tr_handle_clear_halt;
1640 case UF_DEVICE_REMOTE_WAKEUP:
1641 goto tr_handle_clear_wakeup;
1642 default:
1643 goto tr_stalled;
1644 }
1645 break;
1646 case UR_SET_FEATURE:
1647 switch (UGETW(req->wValue)) {
1648 case UF_ENDPOINT_HALT:
1649 goto tr_handle_set_halt;
1650 case UF_DEVICE_REMOTE_WAKEUP:
1651 goto tr_handle_set_wakeup;
1652 default:
1653 goto tr_stalled;
1654 }
1655 break;
1656 case UR_SYNCH_FRAME:
1657 goto tr_valid; /* nop */
1658 default:
1659 goto tr_stalled;
1660 }
1661 break;
1662
1663 case UT_READ_ENDPOINT:
1664 switch (req->bRequest) {
1665 case UR_GET_STATUS:
1666 goto tr_handle_get_ep_status;
1667 default:
1668 goto tr_stalled;
1669 }
1670 break;
1671
1672 case UT_WRITE_INTERFACE:
1673 switch (req->bRequest) {
1674 case UR_SET_INTERFACE:
1675 goto tr_handle_set_interface;
1676 case UR_CLEAR_FEATURE:
1677 goto tr_valid; /* nop */
1678 case UR_SET_FEATURE:
1679 default:
1680 goto tr_stalled;
1681 }
1682 break;
1683
1684 case UT_READ_INTERFACE:
1685 switch (req->bRequest) {
1686 case UR_GET_INTERFACE:
1687 goto tr_handle_get_interface;
1688 case UR_GET_STATUS:
1689 goto tr_handle_get_iface_status;
1690 default:
1691 goto tr_stalled;
1692 }
1693 break;
1694
1695 case UT_WRITE_CLASS_INTERFACE:
1696 case UT_WRITE_VENDOR_INTERFACE:
1697 /* XXX forward */
1698 break;
1699
1700 case UT_READ_CLASS_INTERFACE:
1701 case UT_READ_VENDOR_INTERFACE:
1702 /* XXX forward */
1703 break;
1704
1705 case UT_WRITE_CLASS_DEVICE:
1706 switch (req->bRequest) {
1707 case UR_CLEAR_FEATURE:
1708 goto tr_valid;
1709 case UR_SET_DESCRIPTOR:
1710 case UR_SET_FEATURE:
1711 break;
1712 default:
1713 goto tr_stalled;
1714 }
1715 break;
1716
1717 case UT_WRITE_CLASS_OTHER:
1718 switch (req->bRequest) {
1719 case UR_CLEAR_FEATURE:
1720 goto tr_handle_clear_port_feature;
1721 case UR_SET_FEATURE:
1722 goto tr_handle_set_port_feature;
1723 case UR_CLEAR_TT_BUFFER:
1724 case UR_RESET_TT:
1725 case UR_STOP_TT:
1726 goto tr_valid;
1727
1728 default:
1729 goto tr_stalled;
1730 }
1731 break;
1732
1733 case UT_READ_CLASS_OTHER:
1734 switch (req->bRequest) {
1735 case UR_GET_TT_STATE:
1736 goto tr_handle_get_tt_state;
1737 case UR_GET_STATUS:
1738 goto tr_handle_get_port_status;
1739 default:
1740 goto tr_stalled;
1741 }
1742 break;
1743
1744 case UT_READ_CLASS_DEVICE:
1745 switch (req->bRequest) {
1746 case UR_GET_DESCRIPTOR:
1747 goto tr_handle_get_class_descriptor;
1748 case UR_GET_STATUS:
1749 goto tr_handle_get_class_status;
1750
1751 default:
1752 goto tr_stalled;
1753 }
1754 break;
1755 default:
1756 goto tr_stalled;
1757 }
1758 goto tr_valid;
1759
1760tr_handle_get_descriptor:
1761 switch (value >> 8) {
1762 case UDESC_DEVICE:
1763 if (value & 0xff) {
1764 goto tr_stalled;
1765 }
1766 len = sizeof(atmegadci_devd);
1767 ptr = (const void *)&atmegadci_devd;
1768 goto tr_valid;
1769 case UDESC_CONFIG:
1770 if (value & 0xff) {
1771 goto tr_stalled;
1772 }
1773 len = sizeof(atmegadci_confd);
1774 ptr = (const void *)&atmegadci_confd;
1775 goto tr_valid;
1776 case UDESC_STRING:
1777 switch (value & 0xff) {
1778 case 0: /* Language table */
1779 len = sizeof(atmegadci_langtab);
1780 ptr = (const void *)&atmegadci_langtab;
1781 goto tr_valid;
1782
1783 case 1: /* Vendor */
1784 len = sizeof(atmegadci_vendor);
1785 ptr = (const void *)&atmegadci_vendor;
1786 goto tr_valid;
1787
1788 case 2: /* Product */
1789 len = sizeof(atmegadci_product);
1790 ptr = (const void *)&atmegadci_product;
1791 goto tr_valid;
1792 default:
1793 break;
1794 }
1795 break;
1796 default:
1797 goto tr_stalled;
1798 }
1799 goto tr_stalled;
1800
1801tr_handle_get_config:
1802 len = 1;
1803 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1804 goto tr_valid;
1805
1806tr_handle_get_status:
1807 len = 2;
1808 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1809 goto tr_valid;
1810
1811tr_handle_set_address:
1812 if (value & 0xFF00) {
1813 goto tr_stalled;
1814 }
1815 sc->sc_rt_addr = value;
1816 goto tr_valid;
1817
1818tr_handle_set_config:
1819 if (value >= 2) {
1820 goto tr_stalled;
1821 }
1822 sc->sc_conf = value;
1823 goto tr_valid;
1824
1825tr_handle_get_interface:
1826 len = 1;
1827 sc->sc_hub_temp.wValue[0] = 0;
1828 goto tr_valid;
1829
1830tr_handle_get_tt_state:
1831tr_handle_get_class_status:
1832tr_handle_get_iface_status:
1833tr_handle_get_ep_status:
1834 len = 2;
1835 USETW(sc->sc_hub_temp.wValue, 0);
1836 goto tr_valid;
1837
1838tr_handle_set_halt:
1839tr_handle_set_interface:
1840tr_handle_set_wakeup:
1841tr_handle_clear_wakeup:
1842tr_handle_clear_halt:
1843 goto tr_valid;
1844
1845tr_handle_clear_port_feature:
1846 if (index != 1) {
1847 goto tr_stalled;
1848 }
1849 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1850
1851 switch (value) {
1852 case UHF_PORT_SUSPEND:
1853 atmegadci_wakeup_peer(sc);
1854 break;
1855
1856 case UHF_PORT_ENABLE:
1857 sc->sc_flags.port_enabled = 0;
1858 break;
1859
1860 case UHF_PORT_TEST:
1861 case UHF_PORT_INDICATOR:
1862 case UHF_C_PORT_ENABLE:
1863 case UHF_C_PORT_OVER_CURRENT:
1864 case UHF_C_PORT_RESET:
1865 /* nops */
1866 break;
1867 case UHF_PORT_POWER:
1868 sc->sc_flags.port_powered = 0;
1869 atmegadci_pull_down(sc);
1870 atmegadci_clocks_off(sc);
1871 break;
1872 case UHF_C_PORT_CONNECTION:
1873 /* clear connect change flag */
1874 sc->sc_flags.change_connect = 0;
1875
1876 if (!sc->sc_flags.status_bus_reset) {
1877 /* we are not connected */
1878 break;
1879 }
1880
1881 /* configure the control endpoint */
1882
1883 /* select endpoint number */
1884 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1885
1886 /* set endpoint reset */
1887 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1888
1889 /* clear endpoint reset */
1890 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1891
1892 /* enable and stall endpoint */
1893 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1894 ATMEGA_UECONX_EPEN |
1895 ATMEGA_UECONX_STALLRQ);
1896
1897 /* one bank, 64-bytes wMaxPacket */
1898 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1899 ATMEGA_UECFG0X_EPTYPE0);
1900 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1901 ATMEGA_UECFG1X_ALLOC |
1902 ATMEGA_UECFG1X_EPBK0 |
1903 ATMEGA_UECFG1X_EPSIZE(3));
1904
1905 /* check valid config */
1906 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1907 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1908 device_printf(sc->sc_bus.bdev,
1909 "Chip rejected EP0 configuration\n");
1910 }
1911 break;
1912 case UHF_C_PORT_SUSPEND:
1913 sc->sc_flags.change_suspend = 0;
1914 break;
1915 default:
1916 err = USB_ERR_IOERROR;
1917 goto done;
1918 }
1919 goto tr_valid;
1920
1921tr_handle_set_port_feature:
1922 if (index != 1) {
1923 goto tr_stalled;
1924 }
1925 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1926
1927 switch (value) {
1928 case UHF_PORT_ENABLE:
1929 sc->sc_flags.port_enabled = 1;
1930 break;
1931 case UHF_PORT_SUSPEND:
1932 case UHF_PORT_RESET:
1933 case UHF_PORT_TEST:
1934 case UHF_PORT_INDICATOR:
1935 /* nops */
1936 break;
1937 case UHF_PORT_POWER:
1938 sc->sc_flags.port_powered = 1;
1939 break;
1940 default:
1941 err = USB_ERR_IOERROR;
1942 goto done;
1943 }
1944 goto tr_valid;
1945
1946tr_handle_get_port_status:
1947
1948 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1949
1950 if (index != 1) {
1951 goto tr_stalled;
1952 }
1953 if (sc->sc_flags.status_vbus) {
1954 atmegadci_clocks_on(sc);
1955 atmegadci_pull_up(sc);
1956 } else {
1957 atmegadci_pull_down(sc);
1958 atmegadci_clocks_off(sc);
1959 }
1960
1961 /* Select FULL-speed and Device Side Mode */
1962
1963 value = UPS_PORT_MODE_DEVICE;
1964
1965 if (sc->sc_flags.port_powered) {
1966 value |= UPS_PORT_POWER;
1967 }
1968 if (sc->sc_flags.port_enabled) {
1969 value |= UPS_PORT_ENABLED;
1970 }
1971 if (sc->sc_flags.status_vbus &&
1972 sc->sc_flags.status_bus_reset) {
1973 value |= UPS_CURRENT_CONNECT_STATUS;
1974 }
1975 if (sc->sc_flags.status_suspend) {
1976 value |= UPS_SUSPEND;
1977 }
1978 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1979
1980 value = 0;
1981
1982 if (sc->sc_flags.change_connect) {
1983 value |= UPS_C_CONNECT_STATUS;
1984 }
1985 if (sc->sc_flags.change_suspend) {
1986 value |= UPS_C_SUSPEND;
1987 }
1988 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1989 len = sizeof(sc->sc_hub_temp.ps);
1990 goto tr_valid;
1991
1992tr_handle_get_class_descriptor:
1993 if (value & 0xFF) {
1994 goto tr_stalled;
1995 }
1996 ptr = (const void *)&atmegadci_hubd;
1997 len = sizeof(atmegadci_hubd);
1998 goto tr_valid;
1999
2000tr_stalled:
2001 err = USB_ERR_STALLED;
2002tr_valid:
2003done:
2004 *plength = len;
2005 *pptr = ptr;
2006 return (err);
2007}
2008
2009static void
2010atmegadci_xfer_setup(struct usb_setup_params *parm)
2011{
2012 const struct usb_hw_ep_profile *pf;
2013 struct atmegadci_softc *sc;
2014 struct usb_xfer *xfer;
2015 void *last_obj;
2016 uint32_t ntd;
2017 uint32_t n;
2018 uint8_t ep_no;
2019
2020 sc = ATMEGA_BUS2SC(parm->udev->bus);
2021 xfer = parm->curr_xfer;
2022
2023 /*
2024 * NOTE: This driver does not use any of the parameters that
2025 * are computed from the following values. Just set some
2026 * reasonable dummies:
2027 */
2028 parm->hc_max_packet_size = 0x500;
2029 parm->hc_max_packet_count = 1;
2030 parm->hc_max_frame_size = 0x500;
2031
2032 usbd_transfer_setup_sub(parm);
2033
2034 /*
2035 * compute maximum number of TDs
2036 */
2037 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2038
2039 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2040 + 1 /* SYNC 2 */ ;
2041 } else {
2042
2043 ntd = xfer->nframes + 1 /* SYNC */ ;
2044 }
2045
2046 /*
2047 * check if "usbd_transfer_setup_sub" set an error
2048 */
2049 if (parm->err)
2050 return;
2051
2052 /*
2053 * allocate transfer descriptors
2054 */
2055 last_obj = NULL;
2056
2057 /*
2058 * get profile stuff
2059 */
2060 ep_no = xfer->endpointno & UE_ADDR;
2061 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2062
2063 if (pf == NULL) {
2064 /* should not happen */
2065 parm->err = USB_ERR_INVAL;
2066 return;
2067 }
2068
2069 /* align data */
2070 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2071
2072 for (n = 0; n != ntd; n++) {
2073
2074 struct atmegadci_td *td;
2075
2076 if (parm->buf) {
2077
2078 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2079
2080 /* init TD */
2081 td->max_packet_size = xfer->max_packet_size;
2082 td->ep_no = ep_no;
2083 if (pf->support_multi_buffer) {
2084 td->support_multi_buffer = 1;
2085 }
2086 td->obj_next = last_obj;
2087
2088 last_obj = td;
2089 }
2090 parm->size[0] += sizeof(*td);
2091 }
2092
2093 xfer->td_start[0] = last_obj;
2094}
2095
2096static void
2097atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2098{
2099 return;
2100}
2101
2102static void
2103atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2104 struct usb_endpoint *ep)
2105{
2106 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2107
2108 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2109 ep, udev->address,
2110 edesc->bEndpointAddress, udev->flags.usb_mode,
2111 sc->sc_rt_addr, udev->device_index);
2112
2113 if (udev->device_index != sc->sc_rt_addr) {
2114
2115 if (udev->speed != USB_SPEED_FULL) {
2116 /* not supported */
2117 return;
2118 }
2119 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2120 ep->methods = &atmegadci_device_isoc_fs_methods;
2121 else
2122 ep->methods = &atmegadci_device_non_isoc_methods;
2123 }
2124}
2125
2126static void
2127atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2128{
2129 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2130
2131 switch (state) {
2132 case USB_HW_POWER_SUSPEND:
2133 atmegadci_suspend(sc);
2134 break;
2135 case USB_HW_POWER_SHUTDOWN:
2136 atmegadci_uninit(sc);
2137 break;
2138 case USB_HW_POWER_RESUME:
2139 atmegadci_resume(sc);
2140 break;
2141 default:
2142 break;
2143 }
2144}
2145
2146struct usb_bus_methods atmegadci_bus_methods =
2147{
2148 .endpoint_init = &atmegadci_ep_init,
2149 .xfer_setup = &atmegadci_xfer_setup,
2150 .xfer_unsetup = &atmegadci_xfer_unsetup,
2151 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2152 .xfer_stall = &atmegadci_xfer_stall,
2153 .set_stall = &atmegadci_set_stall,
2154 .clear_stall = &atmegadci_clear_stall,
2155 .roothub_exec = &atmegadci_roothub_exec,
2156 .xfer_poll = &atmegadci_do_poll,
2157 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,
2158};