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if_stge.c (173839) if_stge.c (175315)
1/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.

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37 */
38
39/*
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
42 */
43
44#include <sys/cdefs.h>
1/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.

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37 */
38
39/*
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
42 */
43
44#include <sys/cdefs.h>
45__FBSDID("$FreeBSD: head/sys/dev/stge/if_stge.c 173839 2007-11-22 02:45:00Z yongari $");
45__FBSDID("$FreeBSD: head/sys/dev/stge/if_stge.c 175315 2008-01-14 07:16:48Z yongari $");
46
47#ifdef HAVE_KERNEL_OPTION_HEADERS
48#include "opt_device_polling.h"
49#endif
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/endian.h>

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182static void stge_dma_free(struct stge_softc *);
183static void stge_dma_wait(struct stge_softc *);
184static void stge_init_tx_ring(struct stge_softc *);
185static int stge_init_rx_ring(struct stge_softc *);
186#ifdef DEVICE_POLLING
187static void stge_poll(struct ifnet *, enum poll_cmd, int);
188#endif
189
46
47#ifdef HAVE_KERNEL_OPTION_HEADERS
48#include "opt_device_polling.h"
49#endif
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/endian.h>

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182static void stge_dma_free(struct stge_softc *);
183static void stge_dma_wait(struct stge_softc *);
184static void stge_init_tx_ring(struct stge_softc *);
185static int stge_init_rx_ring(struct stge_softc *);
186#ifdef DEVICE_POLLING
187static void stge_poll(struct ifnet *, enum poll_cmd, int);
188#endif
189
190static void stge_setwol(struct stge_softc *);
190static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
191static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
192static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
193
194static device_method_t stge_methods[] = {
195 /* Device interface */
196 DEVMETHOD(device_probe, stge_probe),
197 DEVMETHOD(device_attach, stge_attach),

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731 /* Revision B3 and earlier chips have checksum bug. */
732 if (sc->sc_rev >= 0x0c) {
733 ifp->if_hwassist = STGE_CSUM_FEATURES;
734 ifp->if_capabilities = IFCAP_HWCSUM;
735 } else {
736 ifp->if_hwassist = 0;
737 ifp->if_capabilities = 0;
738 }
191static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
192static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
193static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
194
195static device_method_t stge_methods[] = {
196 /* Device interface */
197 DEVMETHOD(device_probe, stge_probe),
198 DEVMETHOD(device_attach, stge_attach),

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732 /* Revision B3 and earlier chips have checksum bug. */
733 if (sc->sc_rev >= 0x0c) {
734 ifp->if_hwassist = STGE_CSUM_FEATURES;
735 ifp->if_capabilities = IFCAP_HWCSUM;
736 } else {
737 ifp->if_hwassist = 0;
738 ifp->if_capabilities = 0;
739 }
740 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
739 ifp->if_capenable = ifp->if_capabilities;
740
741 /*
742 * Read some important bits from the PhyCtrl register.
743 */
744 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
745 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
746

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1116/*
1117 * stge_shutdown:
1118 *
1119 * Make sure the interface is stopped at reboot time.
1120 */
1121static int
1122stge_shutdown(device_t dev)
1123{
741 ifp->if_capenable = ifp->if_capabilities;
742
743 /*
744 * Read some important bits from the PhyCtrl register.
745 */
746 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
747 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
748

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1118/*
1119 * stge_shutdown:
1120 *
1121 * Make sure the interface is stopped at reboot time.
1122 */
1123static int
1124stge_shutdown(device_t dev)
1125{
1124 struct stge_softc *sc;
1125
1126
1126 sc = device_get_softc(dev);
1127 return (stge_suspend(dev));
1128}
1127
1129
1128 STGE_LOCK(sc);
1129 stge_stop(sc);
1130 STGE_UNLOCK(sc);
1130static void
1131stge_setwol(struct stge_softc *sc)
1132{
1133 struct ifnet *ifp;
1134 uint8_t v;
1131
1135
1132 return (0);
1136 STGE_LOCK_ASSERT(sc);
1137
1138 ifp = sc->sc_ifp;
1139 v = CSR_READ_1(sc, STGE_WakeEvent);
1140 /* Disable all WOL bits. */
1141 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1142 WE_WakeOnLanEnable);
1143 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1144 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
1145 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1146 /* Reset Tx and prevent transmission. */
1147 CSR_WRITE_4(sc, STGE_AsicCtrl,
1148 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1149 /*
1150 * TC9021 automatically reset link speed to 100Mbps when it's put
1151 * into sleep so there is no need to try to resetting link speed.
1152 */
1133}
1134
1135static int
1136stge_suspend(device_t dev)
1137{
1138 struct stge_softc *sc;
1139
1140 sc = device_get_softc(dev);
1141
1142 STGE_LOCK(sc);
1143 stge_stop(sc);
1144 sc->sc_suspended = 1;
1153}
1154
1155static int
1156stge_suspend(device_t dev)
1157{
1158 struct stge_softc *sc;
1159
1160 sc = device_get_softc(dev);
1161
1162 STGE_LOCK(sc);
1163 stge_stop(sc);
1164 sc->sc_suspended = 1;
1165 stge_setwol(sc);
1145 STGE_UNLOCK(sc);
1146
1147 return (0);
1148}
1149
1150static int
1151stge_resume(device_t dev)
1152{
1153 struct stge_softc *sc;
1154 struct ifnet *ifp;
1166 STGE_UNLOCK(sc);
1167
1168 return (0);
1169}
1170
1171static int
1172stge_resume(device_t dev)
1173{
1174 struct stge_softc *sc;
1175 struct ifnet *ifp;
1176 uint8_t v;
1155
1156 sc = device_get_softc(dev);
1157
1158 STGE_LOCK(sc);
1177
1178 sc = device_get_softc(dev);
1179
1180 STGE_LOCK(sc);
1181 /*
1182 * Clear WOL bits, so special frames wouldn't interfere
1183 * normal Rx operation anymore.
1184 */
1185 v = CSR_READ_1(sc, STGE_WakeEvent);
1186 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1187 WE_WakeOnLanEnable);
1188 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1159 ifp = sc->sc_ifp;
1160 if (ifp->if_flags & IFF_UP)
1161 stge_init_locked(sc);
1162
1163 sc->sc_suspended = 0;
1164 STGE_UNLOCK(sc);
1165
1166 return (0);

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1445 if ((mask & IFCAP_HWCSUM) != 0) {
1446 ifp->if_capenable ^= IFCAP_HWCSUM;
1447 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1448 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1449 ifp->if_hwassist = STGE_CSUM_FEATURES;
1450 else
1451 ifp->if_hwassist = 0;
1452 }
1189 ifp = sc->sc_ifp;
1190 if (ifp->if_flags & IFF_UP)
1191 stge_init_locked(sc);
1192
1193 sc->sc_suspended = 0;
1194 STGE_UNLOCK(sc);
1195
1196 return (0);

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1475 if ((mask & IFCAP_HWCSUM) != 0) {
1476 ifp->if_capenable ^= IFCAP_HWCSUM;
1477 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1478 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1479 ifp->if_hwassist = STGE_CSUM_FEATURES;
1480 else
1481 ifp->if_hwassist = 0;
1482 }
1483 if ((mask & IFCAP_WOL) != 0 &&
1484 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1485 if ((mask & IFCAP_WOL_MAGIC) != 0)
1486 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1487 }
1453 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1454 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1455 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1456 STGE_LOCK(sc);
1457 stge_vlan_setup(sc);
1458 STGE_UNLOCK(sc);
1459 }
1460 }

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2091 ifp = sc->sc_ifp;
2092 mii = device_get_softc(sc->sc_miibus);
2093
2094 /*
2095 * Cancel any pending I/O.
2096 */
2097 stge_stop(sc);
2098
1488 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1489 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1490 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1491 STGE_LOCK(sc);
1492 stge_vlan_setup(sc);
1493 STGE_UNLOCK(sc);
1494 }
1495 }

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2126 ifp = sc->sc_ifp;
2127 mii = device_get_softc(sc->sc_miibus);
2128
2129 /*
2130 * Cancel any pending I/O.
2131 */
2132 stge_stop(sc);
2133
2134 /*
2135 * Reset the chip to a known state.
2136 */
2137 stge_reset(sc, STGE_RESET_FULL);
2138
2099 /* Init descriptors. */
2100 error = stge_init_rx_ring(sc);
2101 if (error != 0) {
2102 device_printf(sc->sc_dev,
2103 "initialization failed: no memory for rx buffers\n");
2104 stge_stop(sc);
2105 goto out;
2106 }

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2304 STGE_LOCK_ASSERT(sc);
2305 /*
2306 * Stop the one second clock.
2307 */
2308 callout_stop(&sc->sc_tick_ch);
2309 sc->sc_watchdog_timer = 0;
2310
2311 /*
2139 /* Init descriptors. */
2140 error = stge_init_rx_ring(sc);
2141 if (error != 0) {
2142 device_printf(sc->sc_dev,
2143 "initialization failed: no memory for rx buffers\n");
2144 stge_stop(sc);
2145 goto out;
2146 }

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2344 STGE_LOCK_ASSERT(sc);
2345 /*
2346 * Stop the one second clock.
2347 */
2348 callout_stop(&sc->sc_tick_ch);
2349 sc->sc_watchdog_timer = 0;
2350
2351 /*
2312 * Reset the chip to a known state.
2313 */
2314 stge_reset(sc, STGE_RESET_FULL);
2315
2316 /*
2317 * Disable interrupts.
2318 */
2319 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2320
2321 /*
2322 * Stop receiver, transmitter, and stats update.
2323 */
2324 stge_stop_rx(sc);

--- 378 unchanged lines hidden --- 		2352 * Disable interrupts.
2353 */
2354 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2355
2356 /*
2357 * Stop receiver, transmitter, and stats update.
2358 */
2359 stge_stop_rx(sc);

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