1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/pci/if_ste.c 72813 2001-02-21 20:54:22Z wpaul $
|
| 32 * $FreeBSD: head/sys/pci/if_ste.c 79472 2001-07-09 17:58:42Z wpaul $ |
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/sockio.h>
38#include <sys/mbuf.h>
39#include <sys/malloc.h>
40#include <sys/kernel.h>
41#include <sys/socket.h>
42
43#include <net/if.h>
44#include <net/if_arp.h>
45#include <net/ethernet.h>
46#include <net/if_dl.h>
47#include <net/if_media.h>
48
49#include <net/bpf.h>
50
51#include <vm/vm.h> /* for vtophys */
52#include <vm/pmap.h> /* for vtophys */
53#include <machine/bus_memio.h>
54#include <machine/bus_pio.h>
55#include <machine/bus.h>
56#include <machine/resource.h>
57#include <sys/bus.h>
58#include <sys/rman.h>
59
60#include <dev/mii/mii.h>
61#include <dev/mii/miivar.h>
62
63#include <pci/pcireg.h>
64#include <pci/pcivar.h>
65
66/* "controller miibus0" required. See GENERIC if you get errors here. */
67#include "miibus_if.h"
68
69#define STE_USEIOSPACE
70
71#include <pci/if_stereg.h>
72
73MODULE_DEPEND(ste, miibus, 1, 1, 1);
74
75#if !defined(lint)
76static const char rcsid[] =
|
77 "$FreeBSD: head/sys/pci/if_ste.c 72813 2001-02-21 20:54:22Z wpaul $";
|
| 77 "$FreeBSD: head/sys/pci/if_ste.c 79472 2001-07-09 17:58:42Z wpaul $"; |
78#endif
79
80/*
81 * Various supported device vendors/types and their names.
82 */
83static struct ste_type ste_devs[] = {
84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
86 { 0, 0, NULL }
87};
88
89static int ste_probe __P((device_t));
90static int ste_attach __P((device_t));
91static int ste_detach __P((device_t));
92static void ste_init __P((void *));
93static void ste_intr __P((void *));
94static void ste_rxeof __P((struct ste_softc *));
95static void ste_txeoc __P((struct ste_softc *));
96static void ste_txeof __P((struct ste_softc *));
97static void ste_stats_update __P((void *));
98static void ste_stop __P((struct ste_softc *));
99static void ste_reset __P((struct ste_softc *));
100static int ste_ioctl __P((struct ifnet *, u_long, caddr_t));
101static int ste_encap __P((struct ste_softc *, struct ste_chain *,
102 struct mbuf *));
103static void ste_start __P((struct ifnet *));
104static void ste_watchdog __P((struct ifnet *));
105static void ste_shutdown __P((device_t));
106static int ste_newbuf __P((struct ste_softc *,
107 struct ste_chain_onefrag *,
108 struct mbuf *));
109static int ste_ifmedia_upd __P((struct ifnet *));
110static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
111
112static void ste_mii_sync __P((struct ste_softc *));
113static void ste_mii_send __P((struct ste_softc *, u_int32_t, int));
114static int ste_mii_readreg __P((struct ste_softc *,
115 struct ste_mii_frame *));
116static int ste_mii_writereg __P((struct ste_softc *,
117 struct ste_mii_frame *));
118static int ste_miibus_readreg __P((device_t, int, int));
119static int ste_miibus_writereg __P((device_t, int, int, int));
120static void ste_miibus_statchg __P((device_t));
121
122static int ste_eeprom_wait __P((struct ste_softc *));
123static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int,
124 int, int));
125static void ste_wait __P((struct ste_softc *));
126static u_int8_t ste_calchash __P((caddr_t));
127static void ste_setmulti __P((struct ste_softc *));
128static int ste_init_rx_list __P((struct ste_softc *));
129static void ste_init_tx_list __P((struct ste_softc *));
130
131#ifdef STE_USEIOSPACE
132#define STE_RES SYS_RES_IOPORT
133#define STE_RID STE_PCI_LOIO
134#else
135#define STE_RES SYS_RES_MEMORY
136#define STE_RID STE_PCI_LOMEM
137#endif
138
139static device_method_t ste_methods[] = {
140 /* Device interface */
141 DEVMETHOD(device_probe, ste_probe),
142 DEVMETHOD(device_attach, ste_attach),
143 DEVMETHOD(device_detach, ste_detach),
144 DEVMETHOD(device_shutdown, ste_shutdown),
145
146 /* bus interface */
147 DEVMETHOD(bus_print_child, bus_generic_print_child),
148 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
149
150 /* MII interface */
151 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
152 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
153 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
154
155 { 0, 0 }
156};
157
158static driver_t ste_driver = {
159 "ste",
160 ste_methods,
161 sizeof(struct ste_softc)
162};
163
164static devclass_t ste_devclass;
165
166DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
167DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
168
169#define STE_SETBIT4(sc, reg, x) \
170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
171
172#define STE_CLRBIT4(sc, reg, x) \
173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
174
175#define STE_SETBIT2(sc, reg, x) \
176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
177
178#define STE_CLRBIT2(sc, reg, x) \
179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
180
181#define STE_SETBIT1(sc, reg, x) \
182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
183
184#define STE_CLRBIT1(sc, reg, x) \
185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
186
187
188#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
189#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
190
191/*
192 * Sync the PHYs by setting data bit and strobing the clock 32 times.
193 */
194static void ste_mii_sync(sc)
195 struct ste_softc *sc;
196{
197 register int i;
198
199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
200
201 for (i = 0; i < 32; i++) {
202 MII_SET(STE_PHYCTL_MCLK);
203 DELAY(1);
204 MII_CLR(STE_PHYCTL_MCLK);
205 DELAY(1);
206 }
207
208 return;
209}
210
211/*
212 * Clock a series of bits through the MII.
213 */
214static void ste_mii_send(sc, bits, cnt)
215 struct ste_softc *sc;
216 u_int32_t bits;
217 int cnt;
218{
219 int i;
220
221 MII_CLR(STE_PHYCTL_MCLK);
222
223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
224 if (bits & i) {
225 MII_SET(STE_PHYCTL_MDATA);
226 } else {
227 MII_CLR(STE_PHYCTL_MDATA);
228 }
229 DELAY(1);
230 MII_CLR(STE_PHYCTL_MCLK);
231 DELAY(1);
232 MII_SET(STE_PHYCTL_MCLK);
233 }
234}
235
236/*
237 * Read an PHY register through the MII.
238 */
239static int ste_mii_readreg(sc, frame)
240 struct ste_softc *sc;
241 struct ste_mii_frame *frame;
242
243{
244 int i, ack;
245
246 STE_LOCK(sc);
247
248 /*
249 * Set up frame for RX.
250 */
251 frame->mii_stdelim = STE_MII_STARTDELIM;
252 frame->mii_opcode = STE_MII_READOP;
253 frame->mii_turnaround = 0;
254 frame->mii_data = 0;
255
256 CSR_WRITE_2(sc, STE_PHYCTL, 0);
257 /*
258 * Turn on data xmit.
259 */
260 MII_SET(STE_PHYCTL_MDIR);
261
262 ste_mii_sync(sc);
263
264 /*
265 * Send command/address info.
266 */
267 ste_mii_send(sc, frame->mii_stdelim, 2);
268 ste_mii_send(sc, frame->mii_opcode, 2);
269 ste_mii_send(sc, frame->mii_phyaddr, 5);
270 ste_mii_send(sc, frame->mii_regaddr, 5);
271
272 /* Turn off xmit. */
273 MII_CLR(STE_PHYCTL_MDIR);
274
275 /* Idle bit */
276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
277 DELAY(1);
278 MII_SET(STE_PHYCTL_MCLK);
279 DELAY(1);
280
281 /* Check for ack */
282 MII_CLR(STE_PHYCTL_MCLK);
283 DELAY(1);
284 MII_SET(STE_PHYCTL_MCLK);
285 DELAY(1);
286 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
287
288 /*
289 * Now try reading data bits. If the ack failed, we still
290 * need to clock through 16 cycles to keep the PHY(s) in sync.
291 */
292 if (ack) {
293 for(i = 0; i < 16; i++) {
294 MII_CLR(STE_PHYCTL_MCLK);
295 DELAY(1);
296 MII_SET(STE_PHYCTL_MCLK);
297 DELAY(1);
298 }
299 goto fail;
300 }
301
302 for (i = 0x8000; i; i >>= 1) {
303 MII_CLR(STE_PHYCTL_MCLK);
304 DELAY(1);
305 if (!ack) {
306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
307 frame->mii_data |= i;
308 DELAY(1);
309 }
310 MII_SET(STE_PHYCTL_MCLK);
311 DELAY(1);
312 }
313
314fail:
315
316 MII_CLR(STE_PHYCTL_MCLK);
317 DELAY(1);
318 MII_SET(STE_PHYCTL_MCLK);
319 DELAY(1);
320
321 STE_UNLOCK(sc);
322
323 if (ack)
324 return(1);
325 return(0);
326}
327
328/*
329 * Write to a PHY register through the MII.
330 */
331static int ste_mii_writereg(sc, frame)
332 struct ste_softc *sc;
333 struct ste_mii_frame *frame;
334
335{
336 STE_LOCK(sc);
337
338 /*
339 * Set up frame for TX.
340 */
341
342 frame->mii_stdelim = STE_MII_STARTDELIM;
343 frame->mii_opcode = STE_MII_WRITEOP;
344 frame->mii_turnaround = STE_MII_TURNAROUND;
345
346 /*
347 * Turn on data output.
348 */
349 MII_SET(STE_PHYCTL_MDIR);
350
351 ste_mii_sync(sc);
352
353 ste_mii_send(sc, frame->mii_stdelim, 2);
354 ste_mii_send(sc, frame->mii_opcode, 2);
355 ste_mii_send(sc, frame->mii_phyaddr, 5);
356 ste_mii_send(sc, frame->mii_regaddr, 5);
357 ste_mii_send(sc, frame->mii_turnaround, 2);
358 ste_mii_send(sc, frame->mii_data, 16);
359
360 /* Idle bit. */
361 MII_SET(STE_PHYCTL_MCLK);
362 DELAY(1);
363 MII_CLR(STE_PHYCTL_MCLK);
364 DELAY(1);
365
366 /*
367 * Turn off xmit.
368 */
369 MII_CLR(STE_PHYCTL_MDIR);
370
371 STE_UNLOCK(sc);
372
373 return(0);
374}
375
376static int ste_miibus_readreg(dev, phy, reg)
377 device_t dev;
378 int phy, reg;
379{
380 struct ste_softc *sc;
381 struct ste_mii_frame frame;
382
383 sc = device_get_softc(dev);
384
385 bzero((char *)&frame, sizeof(frame));
386
387 frame.mii_phyaddr = phy;
388 frame.mii_regaddr = reg;
389 ste_mii_readreg(sc, &frame);
390
391 return(frame.mii_data);
392}
393
394static int ste_miibus_writereg(dev, phy, reg, data)
395 device_t dev;
396 int phy, reg, data;
397{
398 struct ste_softc *sc;
399 struct ste_mii_frame frame;
400
401 sc = device_get_softc(dev);
402 bzero((char *)&frame, sizeof(frame));
403
404 frame.mii_phyaddr = phy;
405 frame.mii_regaddr = reg;
406 frame.mii_data = data;
407
408 ste_mii_writereg(sc, &frame);
409
410 return(0);
411}
412
413static void ste_miibus_statchg(dev)
414 device_t dev;
415{
416 struct ste_softc *sc;
417 struct mii_data *mii;
418
419 sc = device_get_softc(dev);
420 STE_LOCK(sc);
421 mii = device_get_softc(sc->ste_miibus);
422
423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
424 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
425 } else {
426 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
427 }
428 STE_UNLOCK(sc);
429
430 return;
431}
432
433static int ste_ifmedia_upd(ifp)
434 struct ifnet *ifp;
435{
436 struct ste_softc *sc;
437 struct mii_data *mii;
438
439 sc = ifp->if_softc;
440 mii = device_get_softc(sc->ste_miibus);
441 sc->ste_link = 0;
442 if (mii->mii_instance) {
443 struct mii_softc *miisc;
444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
445 mii_phy_reset(miisc);
446 }
447 mii_mediachg(mii);
448
449 return(0);
450}
451
452static void ste_ifmedia_sts(ifp, ifmr)
453 struct ifnet *ifp;
454 struct ifmediareq *ifmr;
455{
456 struct ste_softc *sc;
457 struct mii_data *mii;
458
459 sc = ifp->if_softc;
460 mii = device_get_softc(sc->ste_miibus);
461
462 mii_pollstat(mii);
463 ifmr->ifm_active = mii->mii_media_active;
464 ifmr->ifm_status = mii->mii_media_status;
465
466 return;
467}
468
469static void ste_wait(sc)
470 struct ste_softc *sc;
471{
472 register int i;
473
474 for (i = 0; i < STE_TIMEOUT; i++) {
475 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
476 break;
477 }
478
479 if (i == STE_TIMEOUT)
480 printf("ste%d: command never completed!\n", sc->ste_unit);
481
482 return;
483}
484
485/*
486 * The EEPROM is slow: give it time to come ready after issuing
487 * it a command.
488 */
489static int ste_eeprom_wait(sc)
490 struct ste_softc *sc;
491{
492 int i;
493
494 DELAY(1000);
495
496 for (i = 0; i < 100; i++) {
497 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
498 DELAY(1000);
499 else
500 break;
501 }
502
503 if (i == 100) {
504 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
505 return(1);
506 }
507
508 return(0);
509}
510
511/*
512 * Read a sequence of words from the EEPROM. Note that ethernet address
513 * data is stored in the EEPROM in network byte order.
514 */
515static int ste_read_eeprom(sc, dest, off, cnt, swap)
516 struct ste_softc *sc;
517 caddr_t dest;
518 int off;
519 int cnt;
520 int swap;
521{
522 int err = 0, i;
523 u_int16_t word = 0, *ptr;
524
525 if (ste_eeprom_wait(sc))
526 return(1);
527
528 for (i = 0; i < cnt; i++) {
529 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
530 err = ste_eeprom_wait(sc);
531 if (err)
532 break;
533 word = CSR_READ_2(sc, STE_EEPROM_DATA);
534 ptr = (u_int16_t *)(dest + (i * 2));
535 if (swap)
536 *ptr = ntohs(word);
537 else
538 *ptr = word;
539 }
540
541 return(err ? 1 : 0);
542}
543
544static u_int8_t ste_calchash(addr)
545 caddr_t addr;
546{
547
548 u_int32_t crc, carry;
549 int i, j;
550 u_int8_t c;
551
552 /* Compute CRC for the address value. */
553 crc = 0xFFFFFFFF; /* initial value */
554
555 for (i = 0; i < 6; i++) {
556 c = *(addr + i);
557 for (j = 0; j < 8; j++) {
558 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
559 crc <<= 1;
560 c >>= 1;
561 if (carry)
562 crc = (crc ^ 0x04c11db6) | carry;
563 }
564 }
565
566 /* return the filter bit position */
567 return(crc & 0x0000003F);
568}
569
570static void ste_setmulti(sc)
571 struct ste_softc *sc;
572{
573 struct ifnet *ifp;
574 int h = 0;
575 u_int32_t hashes[2] = { 0, 0 };
576 struct ifmultiaddr *ifma;
577
578 ifp = &sc->arpcom.ac_if;
579 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
580 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
581 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
582 return;
583 }
584
585 /* first, zot all the existing hash bits */
586 CSR_WRITE_4(sc, STE_MAR0, 0);
587 CSR_WRITE_4(sc, STE_MAR1, 0);
588
589 /* now program new ones */
590 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
591 if (ifma->ifma_addr->sa_family != AF_LINK)
592 continue;
593 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
594 if (h < 32)
595 hashes[0] |= (1 << h);
596 else
597 hashes[1] |= (1 << (h - 32));
598 }
599
600 CSR_WRITE_4(sc, STE_MAR0, hashes[0]);
601 CSR_WRITE_4(sc, STE_MAR1, hashes[1]);
602 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
603 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
604
605 return;
606}
607
608static void ste_intr(xsc)
609 void *xsc;
610{
611 struct ste_softc *sc;
612 struct ifnet *ifp;
613 u_int16_t status;
614
615 sc = xsc;
616 STE_LOCK(sc);
617 ifp = &sc->arpcom.ac_if;
618
619 /* See if this is really our interrupt. */
620 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
621 STE_UNLOCK(sc);
622 return;
623 }
624
625 for (;;) {
626 status = CSR_READ_2(sc, STE_ISR_ACK);
627
628 if (!(status & STE_INTRS))
629 break;
630
631 if (status & STE_ISR_RX_DMADONE)
632 ste_rxeof(sc);
633
634 if (status & STE_ISR_TX_DMADONE)
635 ste_txeof(sc);
636
637 if (status & STE_ISR_TX_DONE)
638 ste_txeoc(sc);
639
640 if (status & STE_ISR_STATS_OFLOW) {
641 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
642 ste_stats_update(sc);
643 }
644
645 if (status & STE_ISR_HOSTERR) {
646 ste_reset(sc);
647 ste_init(sc);
648 }
649 }
650
651 /* Re-enable interrupts */
652 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
653
654 if (ifp->if_snd.ifq_head != NULL)
655 ste_start(ifp);
656
657 STE_UNLOCK(sc);
658
659 return;
660}
661
662/*
663 * A frame has been uploaded: pass the resulting mbuf chain up to
664 * the higher level protocols.
665 */
666static void ste_rxeof(sc)
667 struct ste_softc *sc;
668{
669 struct ether_header *eh;
670 struct mbuf *m;
671 struct ifnet *ifp;
672 struct ste_chain_onefrag *cur_rx;
673 int total_len = 0;
674 u_int32_t rxstat;
675
676 ifp = &sc->arpcom.ac_if;
677
678again:
679
680 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) {
681 cur_rx = sc->ste_cdata.ste_rx_head;
682 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
683
684 /*
685 * If an error occurs, update stats, clear the
686 * status word and leave the mbuf cluster in place:
687 * it should simply get re-used next time this descriptor
688 * comes up in the ring.
689 */
690 if (rxstat & STE_RXSTAT_FRAME_ERR) {
691 ifp->if_ierrors++;
692 cur_rx->ste_ptr->ste_status = 0;
693 continue;
694 }
695
696 /*
697 * If there error bit was not set, the upload complete
698 * bit should be set which means we have a valid packet.
699 * If not, something truly strange has happened.
700 */
701 if (!(rxstat & STE_RXSTAT_DMADONE)) {
702 printf("ste%d: bad receive status -- packet dropped",
703 sc->ste_unit);
704 ifp->if_ierrors++;
705 cur_rx->ste_ptr->ste_status = 0;
706 continue;
707 }
708
709 /* No errors; receive the packet. */
710 m = cur_rx->ste_mbuf;
711 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
712
713 /*
714 * Try to conjure up a new mbuf cluster. If that
715 * fails, it means we have an out of memory condition and
716 * should leave the buffer in place and continue. This will
717 * result in a lost packet, but there's little else we
718 * can do in this situation.
719 */
720 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
721 ifp->if_ierrors++;
722 cur_rx->ste_ptr->ste_status = 0;
723 continue;
724 }
725
726 ifp->if_ipackets++;
727 eh = mtod(m, struct ether_header *);
728 m->m_pkthdr.rcvif = ifp;
729 m->m_pkthdr.len = m->m_len = total_len;
730
731 /* Remove header from mbuf and pass it on. */
732 m_adj(m, sizeof(struct ether_header));
733 ether_input(ifp, eh, m);
734 }
735
736 /*
737 * Handle the 'end of channel' condition. When the upload
738 * engine hits the end of the RX ring, it will stall. This
739 * is our cue to flush the RX ring, reload the uplist pointer
740 * register and unstall the engine.
741 * XXX This is actually a little goofy. With the ThunderLAN
742 * chip, you get an interrupt when the receiver hits the end
743 * of the receive ring, which tells you exactly when you
744 * you need to reload the ring pointer. Here we have to
745 * fake it. I'm mad at myself for not being clever enough
746 * to avoid the use of a goto here.
747 */
748 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 ||
749 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) {
750 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
751 ste_wait(sc);
752 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
753 vtophys(&sc->ste_ldata->ste_rx_list[0]));
754 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0];
755 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
756 goto again;
757 }
758
759 return;
760}
761
762static void ste_txeoc(sc)
763 struct ste_softc *sc;
764{
765 u_int8_t txstat;
766 struct ifnet *ifp;
767
768 ifp = &sc->arpcom.ac_if;
769
770 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
771 STE_TXSTATUS_TXDONE) {
772 if (txstat & STE_TXSTATUS_UNDERRUN ||
773 txstat & STE_TXSTATUS_EXCESSCOLLS ||
774 txstat & STE_TXSTATUS_RECLAIMERR) {
775 ifp->if_oerrors++;
776 printf("ste%d: transmission error: %x\n",
777 sc->ste_unit, txstat);
778
779 ste_reset(sc);
780 ste_init(sc);
781
782 if (txstat & STE_TXSTATUS_UNDERRUN &&
783 sc->ste_tx_thresh < STE_PACKET_SIZE) {
784 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
785 printf("ste%d: tx underrun, increasing tx"
786 " start threshold to %d bytes\n",
787 sc->ste_unit, sc->ste_tx_thresh);
788 }
789 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
790 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
791 (STE_PACKET_SIZE >> 4));
792 }
793 ste_init(sc);
794 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
795 }
796
797 return;
798}
799
800static void ste_txeof(sc)
801 struct ste_softc *sc;
802{
803 struct ste_chain *cur_tx = NULL;
804 struct ifnet *ifp;
805 int idx;
806
807 ifp = &sc->arpcom.ac_if;
808
809 idx = sc->ste_cdata.ste_tx_cons;
810 while(idx != sc->ste_cdata.ste_tx_prod) {
811 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
812
813 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
814 break;
815
816 if (cur_tx->ste_mbuf != NULL) {
817 m_freem(cur_tx->ste_mbuf);
818 cur_tx->ste_mbuf = NULL;
819 }
820
821 ifp->if_opackets++;
822
823 sc->ste_cdata.ste_tx_cnt--;
824 STE_INC(idx, STE_TX_LIST_CNT);
825 ifp->if_timer = 0;
826 }
827
828 sc->ste_cdata.ste_tx_cons = idx;
829
830 if (cur_tx != NULL)
831 ifp->if_flags &= ~IFF_OACTIVE;
832
833 return;
834}
835
836static void ste_stats_update(xsc)
837 void *xsc;
838{
839 struct ste_softc *sc;
840 struct ste_stats stats;
841 struct ifnet *ifp;
842 struct mii_data *mii;
843 int i;
844 u_int8_t *p;
845
846 sc = xsc;
847 STE_LOCK(sc);
848
849 ifp = &sc->arpcom.ac_if;
850 mii = device_get_softc(sc->ste_miibus);
851
852 p = (u_int8_t *)&stats;
853
854 for (i = 0; i < sizeof(stats); i++) {
855 *p = CSR_READ_1(sc, STE_STATS + i);
856 p++;
857 }
858
859 ifp->if_collisions += stats.ste_single_colls +
860 stats.ste_multi_colls + stats.ste_late_colls;
861
862 mii_tick(mii);
863 if (!sc->ste_link) {
864 mii_pollstat(mii);
865 if (mii->mii_media_status & IFM_ACTIVE &&
866 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
867 sc->ste_link++;
868 if (ifp->if_snd.ifq_head != NULL)
869 ste_start(ifp);
870 }
871
872 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
873 STE_UNLOCK(sc);
874
875 return;
876}
877
878
879/*
880 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
881 * IDs against our list and return a device name if we find a match.
882 */
883static int ste_probe(dev)
884 device_t dev;
885{
886 struct ste_type *t;
887
888 t = ste_devs;
889
890 while(t->ste_name != NULL) {
891 if ((pci_get_vendor(dev) == t->ste_vid) &&
892 (pci_get_device(dev) == t->ste_did)) {
893 device_set_desc(dev, t->ste_name);
894 return(0);
895 }
896 t++;
897 }
898
899 return(ENXIO);
900}
901
902/*
903 * Attach the interface. Allocate softc structures, do ifmedia
904 * setup and ethernet/BPF attach.
905 */
906static int ste_attach(dev)
907 device_t dev;
908{
909 u_int32_t command;
910 struct ste_softc *sc;
911 struct ifnet *ifp;
912 int unit, error = 0, rid;
913
914 sc = device_get_softc(dev);
915 unit = device_get_unit(dev);
916 bzero(sc, sizeof(struct ste_softc));
917
918 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
919 STE_LOCK(sc);
920
921 /*
922 * Handle power management nonsense.
923 */
924 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
925 u_int32_t iobase, membase, irq;
926
927 /* Save important PCI config data. */
928 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
929 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
930 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
931
932 /* Reset the power state. */
933 printf("ste%d: chip is in D%d power mode "
934 "-- setting to D0\n", unit,
935 pci_get_powerstate(dev));
936 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
937
938 /* Restore PCI config data. */
939 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
940 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
941 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
942 }
943
944 /*
945 * Map control/status registers.
946 */
947 pci_enable_busmaster(dev);
|
948 pci_enable_io(dev, PCIM_CMD_PORTEN);
949 pci_enable_io(dev, PCIM_CMD_MEMEN);
|
948 pci_enable_io(dev, SYS_RES_IOPORT);
949 pci_enable_io(dev, SYS_RES_MEMORY); |
950 command = pci_read_config(dev, PCIR_COMMAND, 4);
951
952#ifdef STE_USEIOSPACE
953 if (!(command & PCIM_CMD_PORTEN)) {
954 printf("ste%d: failed to enable I/O ports!\n", unit);
955 error = ENXIO;
956 goto fail;
957 }
958#else
959 if (!(command & PCIM_CMD_MEMEN)) {
960 printf("ste%d: failed to enable memory mapping!\n", unit);
961 error = ENXIO;
962 goto fail;
963 }
964#endif
965
966 rid = STE_RID;
967 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
968 0, ~0, 1, RF_ACTIVE);
969
970 if (sc->ste_res == NULL) {
971 printf ("ste%d: couldn't map ports/memory\n", unit);
972 error = ENXIO;
973 goto fail;
974 }
975
976 sc->ste_btag = rman_get_bustag(sc->ste_res);
977 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
978
979 rid = 0;
980 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
981 RF_SHAREABLE | RF_ACTIVE);
982
983 if (sc->ste_irq == NULL) {
984 printf("ste%d: couldn't map interrupt\n", unit);
985 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
986 error = ENXIO;
987 goto fail;
988 }
989
990 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
991 ste_intr, sc, &sc->ste_intrhand);
992
993 if (error) {
994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
995 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
996 printf("ste%d: couldn't set up irq\n", unit);
997 goto fail;
998 }
999
1000 callout_handle_init(&sc->ste_stat_ch);
1001
1002 /* Reset the adapter. */
1003 ste_reset(sc);
1004
1005 /*
1006 * Get station address from the EEPROM.
1007 */
1008 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1009 STE_EEADDR_NODE0, 3, 0)) {
1010 printf("ste%d: failed to read station address\n", unit);
1011 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1012 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1013 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1014 error = ENXIO;;
1015 goto fail;
1016 }
1017
1018 /*
1019 * A Sundance chip was detected. Inform the world.
1020 */
1021 printf("ste%d: Ethernet address: %6D\n", unit,
1022 sc->arpcom.ac_enaddr, ":");
1023
1024 sc->ste_unit = unit;
1025
1026 /* Allocate the descriptor queues. */
1027 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1028 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1029
1030 if (sc->ste_ldata == NULL) {
1031 printf("ste%d: no memory for list buffers!\n", unit);
1032 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1033 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1034 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1035 error = ENXIO;
1036 goto fail;
1037 }
1038
1039 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1040
1041 /* Do MII setup. */
1042 if (mii_phy_probe(dev, &sc->ste_miibus,
1043 ste_ifmedia_upd, ste_ifmedia_sts)) {
1044 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1045 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1046 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1047 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1048 contigfree(sc->ste_ldata,
1049 sizeof(struct ste_list_data), M_DEVBUF);
1050 error = ENXIO;
1051 goto fail;
1052 }
1053
1054 ifp = &sc->arpcom.ac_if;
1055 ifp->if_softc = sc;
1056 ifp->if_unit = unit;
1057 ifp->if_name = "ste";
1058 ifp->if_mtu = ETHERMTU;
1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1060 ifp->if_ioctl = ste_ioctl;
1061 ifp->if_output = ether_output;
1062 ifp->if_start = ste_start;
1063 ifp->if_watchdog = ste_watchdog;
1064 ifp->if_init = ste_init;
1065 ifp->if_baudrate = 10000000;
1066 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1067
1068 /*
1069 * Call MI attach routine.
1070 */
1071 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1072 STE_UNLOCK(sc);
1073 return(0);
1074
1075fail:
1076 STE_UNLOCK(sc);
1077 mtx_destroy(&sc->ste_mtx);
1078 return(error);
1079}
1080
1081static int ste_detach(dev)
1082 device_t dev;
1083{
1084 struct ste_softc *sc;
1085 struct ifnet *ifp;
1086
1087 sc = device_get_softc(dev);
1088 STE_LOCK(sc);
1089 ifp = &sc->arpcom.ac_if;
1090
1091 ste_stop(sc);
1092 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1093
1094 bus_generic_detach(dev);
1095 device_delete_child(dev, sc->ste_miibus);
1096
1097 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1099 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1100
1101 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1102
1103 STE_UNLOCK(sc);
1104 mtx_destroy(&sc->ste_mtx);
1105
1106 return(0);
1107}
1108
1109static int ste_newbuf(sc, c, m)
1110 struct ste_softc *sc;
1111 struct ste_chain_onefrag *c;
1112 struct mbuf *m;
1113{
1114 struct mbuf *m_new = NULL;
1115
1116 if (m == NULL) {
1117 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1118 if (m_new == NULL) {
1119 printf("ste%d: no memory for rx list -- "
1120 "packet dropped\n", sc->ste_unit);
1121 return(ENOBUFS);
1122 }
1123 MCLGET(m_new, M_DONTWAIT);
1124 if (!(m_new->m_flags & M_EXT)) {
1125 printf("ste%d: no memory for rx list -- "
1126 "packet dropped\n", sc->ste_unit);
1127 m_freem(m_new);
1128 return(ENOBUFS);
1129 }
1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1131 } else {
1132 m_new = m;
1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1134 m_new->m_data = m_new->m_ext.ext_buf;
1135 }
1136
1137 m_adj(m_new, ETHER_ALIGN);
1138
1139 c->ste_mbuf = m_new;
1140 c->ste_ptr->ste_status = 0;
1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1142 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST;
1143
1144 return(0);
1145}
1146
1147static int ste_init_rx_list(sc)
1148 struct ste_softc *sc;
1149{
1150 struct ste_chain_data *cd;
1151 struct ste_list_data *ld;
1152 int i;
1153
1154 cd = &sc->ste_cdata;
1155 ld = sc->ste_ldata;
1156
1157 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1158 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1159 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1160 return(ENOBUFS);
1161 if (i == (STE_RX_LIST_CNT - 1)) {
1162 cd->ste_rx_chain[i].ste_next =
1163 &cd->ste_rx_chain[0];
1164 ld->ste_rx_list[i].ste_next =
1165 vtophys(&ld->ste_rx_list[0]);
1166 } else {
1167 cd->ste_rx_chain[i].ste_next =
1168 &cd->ste_rx_chain[i + 1];
1169 ld->ste_rx_list[i].ste_next =
1170 vtophys(&ld->ste_rx_list[i + 1]);
1171 }
1172
1173 }
1174
1175 cd->ste_rx_head = &cd->ste_rx_chain[0];
1176
1177 return(0);
1178}
1179
1180static void ste_init_tx_list(sc)
1181 struct ste_softc *sc;
1182{
1183 struct ste_chain_data *cd;
1184 struct ste_list_data *ld;
1185 int i;
1186
1187 cd = &sc->ste_cdata;
1188 ld = sc->ste_ldata;
1189 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1190 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1191 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1192 if (i == (STE_TX_LIST_CNT - 1))
1193 cd->ste_tx_chain[i].ste_next =
1194 &cd->ste_tx_chain[0];
1195 else
1196 cd->ste_tx_chain[i].ste_next =
1197 &cd->ste_tx_chain[i + 1];
1198 if (i == 0)
1199 cd->ste_tx_chain[i].ste_prev =
1200 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1201 else
1202 cd->ste_tx_chain[i].ste_prev =
1203 &cd->ste_tx_chain[i - 1];
1204 }
1205
1206
1207 bzero((char *)ld->ste_tx_list,
1208 sizeof(struct ste_desc) * STE_TX_LIST_CNT);
1209
1210 cd->ste_tx_prod = 0;
1211 cd->ste_tx_cons = 0;
1212 cd->ste_tx_cnt = 0;
1213
1214 return;
1215}
1216
1217static void ste_init(xsc)
1218 void *xsc;
1219{
1220 struct ste_softc *sc;
1221 int i;
1222 struct ifnet *ifp;
1223 struct mii_data *mii;
1224
1225 sc = xsc;
1226 STE_LOCK(sc);
1227 ifp = &sc->arpcom.ac_if;
1228 mii = device_get_softc(sc->ste_miibus);
1229
1230 ste_stop(sc);
1231
1232 /* Init our MAC address */
1233 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1234 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1235 }
1236
1237 /* Init RX list */
1238 if (ste_init_rx_list(sc) == ENOBUFS) {
1239 printf("ste%d: initialization failed: no "
1240 "memory for RX buffers\n", sc->ste_unit);
1241 ste_stop(sc);
1242 STE_UNLOCK(sc);
1243 return;
1244 }
1245
1246 /* Init TX descriptors */
1247 ste_init_tx_list(sc);
1248
1249 /* Set the TX freethresh value */
1250 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1251
1252 /* Set the TX start threshold for best performance. */
1253 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1254
1255 /* Set the TX reclaim threshold. */
1256 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1257
1258 /* Set up the RX filter. */
1259 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1260
1261 /* If we want promiscuous mode, set the allframes bit. */
1262 if (ifp->if_flags & IFF_PROMISC) {
1263 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1264 } else {
1265 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1266 }
1267
1268 /* Set capture broadcast bit to accept broadcast frames. */
1269 if (ifp->if_flags & IFF_BROADCAST) {
1270 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1271 } else {
1272 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1273 }
1274
1275 ste_setmulti(sc);
1276
1277 /* Load the address of the RX list. */
1278 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1279 ste_wait(sc);
1280 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1281 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1282 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1284
1285 /* Set TX polling interval */
1286 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1287
1288 /* Load address of the TX list */
1289 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1290 ste_wait(sc);
1291 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1292 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1293 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1295 ste_wait(sc);
1296
1297 /* Enable receiver and transmitter */
1298 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1299 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1300 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1301
1302 /* Enable stats counters. */
1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1304
1305 /* Enable interrupts. */
1306 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1307 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1308
1309 ste_ifmedia_upd(ifp);
1310
1311 ifp->if_flags |= IFF_RUNNING;
1312 ifp->if_flags &= ~IFF_OACTIVE;
1313
1314 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1315 STE_UNLOCK(sc);
1316
1317 return;
1318}
1319
1320static void ste_stop(sc)
1321 struct ste_softc *sc;
1322{
1323 int i;
1324 struct ifnet *ifp;
1325
1326 STE_LOCK(sc);
1327 ifp = &sc->arpcom.ac_if;
1328
1329 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1330
1331 CSR_WRITE_2(sc, STE_IMR, 0);
1332 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1333 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1334 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1335 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1336 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1337 ste_wait(sc);
1338
1339 sc->ste_link = 0;
1340
1341 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1342 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1343 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1344 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1345 }
1346 }
1347
1348 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1349 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1350 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1351 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1352 }
1353 }
1354
1355 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1356 STE_UNLOCK(sc);
1357
1358 return;
1359}
1360
1361static void ste_reset(sc)
1362 struct ste_softc *sc;
1363{
1364 int i;
1365
1366 STE_SETBIT4(sc, STE_ASICCTL,
1367 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1368 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1369 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1370 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1371 STE_ASICCTL_EXTRESET_RESET);
1372
1373 DELAY(100000);
1374
1375 for (i = 0; i < STE_TIMEOUT; i++) {
1376 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1377 break;
1378 }
1379
1380 if (i == STE_TIMEOUT)
1381 printf("ste%d: global reset never completed\n", sc->ste_unit);
1382
1383 return;
1384}
1385
1386static int ste_ioctl(ifp, command, data)
1387 struct ifnet *ifp;
1388 u_long command;
1389 caddr_t data;
1390{
1391 struct ste_softc *sc;
1392 struct ifreq *ifr;
1393 struct mii_data *mii;
1394 int error = 0;
1395
1396 sc = ifp->if_softc;
1397 STE_LOCK(sc);
1398 ifr = (struct ifreq *)data;
1399
1400 switch(command) {
1401 case SIOCSIFADDR:
1402 case SIOCGIFADDR:
1403 case SIOCSIFMTU:
1404 error = ether_ioctl(ifp, command, data);
1405 break;
1406 case SIOCSIFFLAGS:
1407 if (ifp->if_flags & IFF_UP) {
1408 if (ifp->if_flags & IFF_RUNNING &&
1409 ifp->if_flags & IFF_PROMISC &&
1410 !(sc->ste_if_flags & IFF_PROMISC)) {
1411 STE_SETBIT1(sc, STE_RX_MODE,
1412 STE_RXMODE_PROMISC);
1413 } else if (ifp->if_flags & IFF_RUNNING &&
1414 !(ifp->if_flags & IFF_PROMISC) &&
1415 sc->ste_if_flags & IFF_PROMISC) {
1416 STE_CLRBIT1(sc, STE_RX_MODE,
1417 STE_RXMODE_PROMISC);
1418 } else if (!(ifp->if_flags & IFF_RUNNING)) {
1419 sc->ste_tx_thresh = STE_MIN_FRAMELEN;
1420 ste_init(sc);
1421 }
1422 } else {
1423 if (ifp->if_flags & IFF_RUNNING)
1424 ste_stop(sc);
1425 }
1426 sc->ste_if_flags = ifp->if_flags;
1427 error = 0;
1428 break;
1429 case SIOCADDMULTI:
1430 case SIOCDELMULTI:
1431 ste_setmulti(sc);
1432 error = 0;
1433 break;
1434 case SIOCGIFMEDIA:
1435 case SIOCSIFMEDIA:
1436 mii = device_get_softc(sc->ste_miibus);
1437 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1438 break;
1439 default:
1440 error = EINVAL;
1441 break;
1442 }
1443
1444 STE_UNLOCK(sc);
1445
1446 return(error);
1447}
1448
1449static int ste_encap(sc, c, m_head)
1450 struct ste_softc *sc;
1451 struct ste_chain *c;
1452 struct mbuf *m_head;
1453{
1454 int frag = 0;
1455 struct ste_frag *f = NULL;
1456 struct mbuf *m;
1457 struct ste_desc *d;
1458 int total_len = 0;
1459
1460 d = c->ste_ptr;
1461 d->ste_ctl = 0;
1462 d->ste_next = 0;
1463
1464 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1465 if (m->m_len != 0) {
1466 if (frag == STE_MAXFRAGS)
1467 break;
1468 total_len += m->m_len;
1469 f = &c->ste_ptr->ste_frags[frag];
1470 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1471 f->ste_len = m->m_len;
1472 frag++;
1473 }
1474 }
1475
1476 c->ste_mbuf = m_head;
1477 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1478 c->ste_ptr->ste_ctl = total_len;
1479
1480 return(0);
1481}
1482
1483static void ste_start(ifp)
1484 struct ifnet *ifp;
1485{
1486 struct ste_softc *sc;
1487 struct mbuf *m_head = NULL;
1488 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1489 int idx;
1490
1491 sc = ifp->if_softc;
1492 STE_LOCK(sc);
1493
1494 if (!sc->ste_link) {
1495 STE_UNLOCK(sc);
1496 return;
1497 }
1498
1499 if (ifp->if_flags & IFF_OACTIVE) {
1500 STE_UNLOCK(sc);
1501 return;
1502 }
1503
1504 idx = sc->ste_cdata.ste_tx_prod;
1505 start_tx = &sc->ste_cdata.ste_tx_chain[idx];
1506
1507 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1508
1509 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1510 ifp->if_flags |= IFF_OACTIVE;
1511 break;
1512 }
1513
1514 IF_DEQUEUE(&ifp->if_snd, m_head);
1515 if (m_head == NULL)
1516 break;
1517
1518 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1519
1520 ste_encap(sc, cur_tx, m_head);
1521
1522 if (prev != NULL)
1523 prev->ste_ptr->ste_next = cur_tx->ste_phys;
1524 prev = cur_tx;
1525
1526 /*
1527 * If there's a BPF listener, bounce a copy of this frame
1528 * to him.
1529 */
1530 if (ifp->if_bpf)
1531 bpf_mtap(ifp, cur_tx->ste_mbuf);
1532
1533 STE_INC(idx, STE_TX_LIST_CNT);
1534 sc->ste_cdata.ste_tx_cnt++;
1535 }
1536
1537 if (cur_tx == NULL) {
1538 STE_UNLOCK(sc);
1539 return;
1540 }
1541
1542 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR;
1543
1544 /* Start transmission */
1545 sc->ste_cdata.ste_tx_prod = idx;
1546 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys;
1547
1548 ifp->if_timer = 5;
1549 STE_UNLOCK(sc);
1550
1551 return;
1552}
1553
1554static void ste_watchdog(ifp)
1555 struct ifnet *ifp;
1556{
1557 struct ste_softc *sc;
1558
1559 sc = ifp->if_softc;
1560 STE_LOCK(sc);
1561
1562 ifp->if_oerrors++;
1563 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1564
1565 ste_txeoc(sc);
1566 ste_txeof(sc);
1567 ste_rxeof(sc);
1568 ste_reset(sc);
1569 ste_init(sc);
1570
1571 if (ifp->if_snd.ifq_head != NULL)
1572 ste_start(ifp);
1573 STE_UNLOCK(sc);
1574
1575 return;
1576}
1577
1578static void ste_shutdown(dev)
1579 device_t dev;
1580{
1581 struct ste_softc *sc;
1582
1583 sc = device_get_softc(dev);
1584
1585 ste_stop(sc);
1586
1587 return;
1588}
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