28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/kernel.h>
33#include <sys/lock.h>
34#include <sys/module.h>
35#include <sys/mutex.h>
36#include <sys/resource.h>
37#include <sys/rman.h>
38#include <sys/sysctl.h>
39#include <sys/taskqueue.h>
40
41#include <dev/pci/pcireg.h>
42#include <dev/pci/pcivar.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46
47#include <dev/mmc/bridge.h>
48
49#include <dev/sdhci/sdhci.h>
50
51#include "mmcbr_if.h"
52#include "sdhci_if.h"
53
54/*
55 * PCI registers
56 */
57#define PCI_SDHCI_IFPIO 0x00
58#define PCI_SDHCI_IFDMA 0x01
59#define PCI_SDHCI_IFVENDOR 0x02
60
61#define PCI_SLOT_INFO 0x40 /* 8 bits */
62#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
63#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
64
65/*
66 * RICOH specific PCI registers
67 */
68#define SDHC_PCI_MODE_KEY 0xf9
69#define SDHC_PCI_MODE 0x150
70#define SDHC_PCI_MODE_SD20 0x10
71#define SDHC_PCI_BASE_FREQ_KEY 0xfc
72#define SDHC_PCI_BASE_FREQ 0xe1
73
74static const struct sdhci_device {
75 uint32_t model;
76 uint16_t subvendor;
77 const char *desc;
78 u_int quirks;
79} sdhci_devices[] = {
80 { 0x08221180, 0xffff, "RICOH R5C822 SD",
81 SDHCI_QUIRK_FORCE_DMA },
82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
83 SDHCI_QUIRK_FORCE_DMA |
84 SDHCI_QUIRK_LOWER_FREQUENCY },
85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
86 SDHCI_QUIRK_LOWER_FREQUENCY },
87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
88 SDHCI_QUIRK_FORCE_DMA },
89 { 0x05501524, 0xffff, "ENE CB712 SD",
90 SDHCI_QUIRK_BROKEN_TIMINGS },
91 { 0x05511524, 0xffff, "ENE CB712 SD 2",
92 SDHCI_QUIRK_BROKEN_TIMINGS },
93 { 0x07501524, 0xffff, "ENE CB714 SD",
94 SDHCI_QUIRK_RESET_ON_IOS |
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x07511524, 0xffff, "ENE CB714 SD 2",
97 SDHCI_QUIRK_RESET_ON_IOS |
98 SDHCI_QUIRK_BROKEN_TIMINGS },
99 { 0x410111ab, 0xffff, "Marvell CaFe SD",
100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
101 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
102 SDHCI_QUIRK_32BIT_DMA_SIZE |
103 SDHCI_QUIRK_RESET_AFTER_REQUEST },
104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
107 /* DDR52 is supported but affected by the VLI54 erratum */
108 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
109 SDHCI_QUIRK_WAIT_WHILE_BUSY |
110 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
111 SDHCI_QUIRK_PRESET_VALUE_BROKEN},
112 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
113 SDHCI_QUIRK_WAIT_WHILE_BUSY |
114 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
115 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
116 /* DDR52 is supported but affected by the VLI54 erratum */
117 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
118 SDHCI_QUIRK_WAIT_WHILE_BUSY |
119 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
120 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
121 { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller",
122 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
123 SDHCI_QUIRK_WAIT_WHILE_BUSY |
124 SDHCI_QUIRK_MMC_DDR52 |
125 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
126 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
127 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
128 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
129 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
130 SDHCI_QUIRK_WAIT_WHILE_BUSY |
131 SDHCI_QUIRK_MMC_DDR52 |
132 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
133 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
134 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
135 SDHCI_QUIRK_WAIT_WHILE_BUSY |
136 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
137 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
138 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
139 SDHCI_QUIRK_WAIT_WHILE_BUSY |
140 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
141 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
142 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
143 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
144 SDHCI_QUIRK_WAIT_WHILE_BUSY |
145 SDHCI_QUIRK_MMC_DDR52 |
146 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
147 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
148 { 0, 0xffff, NULL,
149 0 }
150};
151
152struct sdhci_pci_softc {
153 u_int quirks; /* Chip specific quirks */
154 struct resource *irq_res; /* IRQ resource */
155 void *intrhand; /* Interrupt handle */
156
157 int num_slots; /* Number of slots on this controller */
158 struct sdhci_slot slots[6];
159 struct resource *mem_res[6]; /* Memory resource */
160 uint8_t cfg_freq; /* Saved frequency */
161 uint8_t cfg_mode; /* Saved mode */
162};
163
164static int sdhci_enable_msi = 1;
165TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi);
166SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
167 0, "Enable MSI interrupts");
168
169static uint8_t
170sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
171{
172 struct sdhci_pci_softc *sc = device_get_softc(dev);
173
174 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
175 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
176 return bus_read_1(sc->mem_res[slot->num], off);
177}
178
179static void
180sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
181 bus_size_t off, uint8_t val)
182{
183 struct sdhci_pci_softc *sc = device_get_softc(dev);
184
185 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
187 bus_write_1(sc->mem_res[slot->num], off, val);
188}
189
190static uint16_t
191sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
192{
193 struct sdhci_pci_softc *sc = device_get_softc(dev);
194
195 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
196 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
197 return bus_read_2(sc->mem_res[slot->num], off);
198}
199
200static void
201sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
202 bus_size_t off, uint16_t val)
203{
204 struct sdhci_pci_softc *sc = device_get_softc(dev);
205
206 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
207 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
208 bus_write_2(sc->mem_res[slot->num], off, val);
209}
210
211static uint32_t
212sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
213{
214 struct sdhci_pci_softc *sc = device_get_softc(dev);
215
216 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
217 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
218 return bus_read_4(sc->mem_res[slot->num], off);
219}
220
221static void
222sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
223 bus_size_t off, uint32_t val)
224{
225 struct sdhci_pci_softc *sc = device_get_softc(dev);
226
227 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
228 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
229 bus_write_4(sc->mem_res[slot->num], off, val);
230}
231
232static void
233sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
234 bus_size_t off, uint32_t *data, bus_size_t count)
235{
236 struct sdhci_pci_softc *sc = device_get_softc(dev);
237
238 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
239}
240
241static void
242sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
243 bus_size_t off, uint32_t *data, bus_size_t count)
244{
245 struct sdhci_pci_softc *sc = device_get_softc(dev);
246
247 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
248}
249
250static void sdhci_pci_intr(void *arg);
251
252static void
253sdhci_lower_frequency(device_t dev)
254{
255 struct sdhci_pci_softc *sc = device_get_softc(dev);
256
257 /*
258 * Enable SD2.0 mode.
259 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
260 */
261 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
262 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
263 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
264 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
265
266 /*
267 * Some SD/MMC cards don't work with the default base
268 * clock frequency of 200 MHz. Lower it to 50 MHz.
269 */
270 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
271 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
272 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
273 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
274}
275
276static void
277sdhci_restore_frequency(device_t dev)
278{
279 struct sdhci_pci_softc *sc = device_get_softc(dev);
280
281 /* Restore mode. */
282 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
283 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
284 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
285
286 /* Restore frequency. */
287 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
288 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
289 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
290}
291
292static int
293sdhci_pci_probe(device_t dev)
294{
295 uint32_t model;
296 uint16_t subvendor;
297 uint8_t class, subclass;
298 int i, result;
299
300 model = (uint32_t)pci_get_device(dev) << 16;
301 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
302 subvendor = pci_get_subvendor(dev);
303 class = pci_get_class(dev);
304 subclass = pci_get_subclass(dev);
305
306 result = ENXIO;
307 for (i = 0; sdhci_devices[i].model != 0; i++) {
308 if (sdhci_devices[i].model == model &&
309 (sdhci_devices[i].subvendor == 0xffff ||
310 sdhci_devices[i].subvendor == subvendor)) {
311 device_set_desc(dev, sdhci_devices[i].desc);
312 result = BUS_PROBE_DEFAULT;
313 break;
314 }
315 }
316 if (result == ENXIO && class == PCIC_BASEPERIPH &&
317 subclass == PCIS_BASEPERIPH_SDHC) {
318 device_set_desc(dev, "Generic SD HCI");
319 result = BUS_PROBE_GENERIC;
320 }
321
322 return (result);
323}
324
325static int
326sdhci_pci_attach(device_t dev)
327{
328 struct sdhci_pci_softc *sc = device_get_softc(dev);
329 struct sdhci_slot *slot;
330 uint32_t model;
331 uint16_t subvendor;
332 int bar, err, rid, slots, i;
333
334 model = (uint32_t)pci_get_device(dev) << 16;
335 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
336 subvendor = pci_get_subvendor(dev);
337 /* Apply chip specific quirks. */
338 for (i = 0; sdhci_devices[i].model != 0; i++) {
339 if (sdhci_devices[i].model == model &&
340 (sdhci_devices[i].subvendor == 0xffff ||
341 sdhci_devices[i].subvendor == subvendor)) {
342 sc->quirks = sdhci_devices[i].quirks;
343 break;
344 }
345 }
346 sc->quirks &= ~sdhci_quirk_clear;
347 sc->quirks |= sdhci_quirk_set;
348
349 /* Some controllers need to be bumped into the right mode. */
350 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
351 sdhci_lower_frequency(dev);
352 /* Read slots info from PCI registers. */
353 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
354 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
355 slots = PCI_SLOT_INFO_SLOTS(slots);
356 if (slots > 6 || bar > 5) {
357 device_printf(dev, "Incorrect slots information (%d, %d).\n",
358 slots, bar);
359 return (EINVAL);
360 }
361 /* Allocate IRQ. */
362 i = 1;
363 rid = 0;
364 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
365 rid = 1;
366 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
367 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
368 if (sc->irq_res == NULL) {
369 device_printf(dev, "Can't allocate IRQ\n");
370 pci_release_msi(dev);
371 return (ENOMEM);
372 }
373 /* Scan all slots. */
374 for (i = 0; i < slots; i++) {
375 slot = &sc->slots[sc->num_slots];
376
377 /* Allocate memory. */
378 rid = PCIR_BAR(bar + i);
379 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
380 &rid, RF_ACTIVE);
381 if (sc->mem_res[i] == NULL) {
382 device_printf(dev,
383 "Can't allocate memory for slot %d\n", i);
384 continue;
385 }
386
387 slot->quirks = sc->quirks;
388
389 if (sdhci_init_slot(dev, slot, i) != 0)
390 continue;
391
392 sc->num_slots++;
393 }
394 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
395 /* Activate the interrupt */
396 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
397 NULL, sdhci_pci_intr, sc, &sc->intrhand);
398 if (err)
399 device_printf(dev, "Can't setup IRQ\n");
400 pci_enable_busmaster(dev);
401 /* Process cards detection. */
402 for (i = 0; i < sc->num_slots; i++)
403 sdhci_start_slot(&sc->slots[i]);
404
405 return (0);
406}
407
408static int
409sdhci_pci_detach(device_t dev)
410{
411 struct sdhci_pci_softc *sc = device_get_softc(dev);
412 int i;
413
414 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
415 bus_release_resource(dev, SYS_RES_IRQ,
416 rman_get_rid(sc->irq_res), sc->irq_res);
417 pci_release_msi(dev);
418
419 for (i = 0; i < sc->num_slots; i++) {
420 sdhci_cleanup_slot(&sc->slots[i]);
421 bus_release_resource(dev, SYS_RES_MEMORY,
422 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
423 }
424 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
425 sdhci_restore_frequency(dev);
426 return (0);
427}
428
429static int
430sdhci_pci_shutdown(device_t dev)
431{
432 struct sdhci_pci_softc *sc = device_get_softc(dev);
433
434 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
435 sdhci_restore_frequency(dev);
436 return (0);
437}
438
439static int
440sdhci_pci_suspend(device_t dev)
441{
442 struct sdhci_pci_softc *sc = device_get_softc(dev);
443 int i, err;
444
445 err = bus_generic_suspend(dev);
446 if (err)
447 return (err);
448 for (i = 0; i < sc->num_slots; i++)
449 sdhci_generic_suspend(&sc->slots[i]);
450 return (0);
451}
452
453static int
454sdhci_pci_resume(device_t dev)
455{
456 struct sdhci_pci_softc *sc = device_get_softc(dev);
457 int i, err;
458
459 for (i = 0; i < sc->num_slots; i++)
460 sdhci_generic_resume(&sc->slots[i]);
461 err = bus_generic_resume(dev);
462 if (err)
463 return (err);
464 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
465 sdhci_lower_frequency(dev);
466 return (0);
467}
468
469static void
470sdhci_pci_intr(void *arg)
471{
472 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
473 int i;
474
475 for (i = 0; i < sc->num_slots; i++)
476 sdhci_generic_intr(&sc->slots[i]);
477}
478
479static device_method_t sdhci_methods[] = {
480 /* device_if */
481 DEVMETHOD(device_probe, sdhci_pci_probe),
482 DEVMETHOD(device_attach, sdhci_pci_attach),
483 DEVMETHOD(device_detach, sdhci_pci_detach),
484 DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
485 DEVMETHOD(device_suspend, sdhci_pci_suspend),
486 DEVMETHOD(device_resume, sdhci_pci_resume),
487
488 /* Bus interface */
489 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
490 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
491
492 /* mmcbr_if */
493 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
494 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
495 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
496 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
497 DEVMETHOD(mmcbr_request, sdhci_generic_request),
498 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
499 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
500 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
501
502 /* SDHCI accessors */
503 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
504 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
505 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
506 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
507 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
508 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
509 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
510 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
511 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
512
513 DEVMETHOD_END
514};
515
516static driver_t sdhci_pci_driver = {
517 "sdhci_pci",
518 sdhci_methods,
519 sizeof(struct sdhci_pci_softc),
520};
521static devclass_t sdhci_pci_devclass;
522
523DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
524 NULL);
| 28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/kernel.h>
33#include <sys/lock.h>
34#include <sys/module.h>
35#include <sys/mutex.h>
36#include <sys/resource.h>
37#include <sys/rman.h>
38#include <sys/sysctl.h>
39#include <sys/taskqueue.h>
40
41#include <dev/pci/pcireg.h>
42#include <dev/pci/pcivar.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46
47#include <dev/mmc/bridge.h>
48
49#include <dev/sdhci/sdhci.h>
50
51#include "mmcbr_if.h"
52#include "sdhci_if.h"
53
54/*
55 * PCI registers
56 */
57#define PCI_SDHCI_IFPIO 0x00
58#define PCI_SDHCI_IFDMA 0x01
59#define PCI_SDHCI_IFVENDOR 0x02
60
61#define PCI_SLOT_INFO 0x40 /* 8 bits */
62#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
63#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
64
65/*
66 * RICOH specific PCI registers
67 */
68#define SDHC_PCI_MODE_KEY 0xf9
69#define SDHC_PCI_MODE 0x150
70#define SDHC_PCI_MODE_SD20 0x10
71#define SDHC_PCI_BASE_FREQ_KEY 0xfc
72#define SDHC_PCI_BASE_FREQ 0xe1
73
74static const struct sdhci_device {
75 uint32_t model;
76 uint16_t subvendor;
77 const char *desc;
78 u_int quirks;
79} sdhci_devices[] = {
80 { 0x08221180, 0xffff, "RICOH R5C822 SD",
81 SDHCI_QUIRK_FORCE_DMA },
82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
83 SDHCI_QUIRK_FORCE_DMA |
84 SDHCI_QUIRK_LOWER_FREQUENCY },
85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
86 SDHCI_QUIRK_LOWER_FREQUENCY },
87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
88 SDHCI_QUIRK_FORCE_DMA },
89 { 0x05501524, 0xffff, "ENE CB712 SD",
90 SDHCI_QUIRK_BROKEN_TIMINGS },
91 { 0x05511524, 0xffff, "ENE CB712 SD 2",
92 SDHCI_QUIRK_BROKEN_TIMINGS },
93 { 0x07501524, 0xffff, "ENE CB714 SD",
94 SDHCI_QUIRK_RESET_ON_IOS |
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x07511524, 0xffff, "ENE CB714 SD 2",
97 SDHCI_QUIRK_RESET_ON_IOS |
98 SDHCI_QUIRK_BROKEN_TIMINGS },
99 { 0x410111ab, 0xffff, "Marvell CaFe SD",
100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
101 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
102 SDHCI_QUIRK_32BIT_DMA_SIZE |
103 SDHCI_QUIRK_RESET_AFTER_REQUEST },
104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
107 /* DDR52 is supported but affected by the VLI54 erratum */
108 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
109 SDHCI_QUIRK_WAIT_WHILE_BUSY |
110 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
111 SDHCI_QUIRK_PRESET_VALUE_BROKEN},
112 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
113 SDHCI_QUIRK_WAIT_WHILE_BUSY |
114 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
115 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
116 /* DDR52 is supported but affected by the VLI54 erratum */
117 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
118 SDHCI_QUIRK_WAIT_WHILE_BUSY |
119 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
120 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
121 { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller",
122 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
123 SDHCI_QUIRK_WAIT_WHILE_BUSY |
124 SDHCI_QUIRK_MMC_DDR52 |
125 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
126 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
127 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
128 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
129 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
130 SDHCI_QUIRK_WAIT_WHILE_BUSY |
131 SDHCI_QUIRK_MMC_DDR52 |
132 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
133 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
134 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
135 SDHCI_QUIRK_WAIT_WHILE_BUSY |
136 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
137 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
138 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
139 SDHCI_QUIRK_WAIT_WHILE_BUSY |
140 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
141 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
142 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
143 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
144 SDHCI_QUIRK_WAIT_WHILE_BUSY |
145 SDHCI_QUIRK_MMC_DDR52 |
146 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
147 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
148 { 0, 0xffff, NULL,
149 0 }
150};
151
152struct sdhci_pci_softc {
153 u_int quirks; /* Chip specific quirks */
154 struct resource *irq_res; /* IRQ resource */
155 void *intrhand; /* Interrupt handle */
156
157 int num_slots; /* Number of slots on this controller */
158 struct sdhci_slot slots[6];
159 struct resource *mem_res[6]; /* Memory resource */
160 uint8_t cfg_freq; /* Saved frequency */
161 uint8_t cfg_mode; /* Saved mode */
162};
163
164static int sdhci_enable_msi = 1;
165TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi);
166SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
167 0, "Enable MSI interrupts");
168
169static uint8_t
170sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
171{
172 struct sdhci_pci_softc *sc = device_get_softc(dev);
173
174 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
175 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
176 return bus_read_1(sc->mem_res[slot->num], off);
177}
178
179static void
180sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
181 bus_size_t off, uint8_t val)
182{
183 struct sdhci_pci_softc *sc = device_get_softc(dev);
184
185 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
187 bus_write_1(sc->mem_res[slot->num], off, val);
188}
189
190static uint16_t
191sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
192{
193 struct sdhci_pci_softc *sc = device_get_softc(dev);
194
195 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
196 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
197 return bus_read_2(sc->mem_res[slot->num], off);
198}
199
200static void
201sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
202 bus_size_t off, uint16_t val)
203{
204 struct sdhci_pci_softc *sc = device_get_softc(dev);
205
206 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
207 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
208 bus_write_2(sc->mem_res[slot->num], off, val);
209}
210
211static uint32_t
212sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
213{
214 struct sdhci_pci_softc *sc = device_get_softc(dev);
215
216 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
217 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
218 return bus_read_4(sc->mem_res[slot->num], off);
219}
220
221static void
222sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
223 bus_size_t off, uint32_t val)
224{
225 struct sdhci_pci_softc *sc = device_get_softc(dev);
226
227 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
228 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
229 bus_write_4(sc->mem_res[slot->num], off, val);
230}
231
232static void
233sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
234 bus_size_t off, uint32_t *data, bus_size_t count)
235{
236 struct sdhci_pci_softc *sc = device_get_softc(dev);
237
238 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
239}
240
241static void
242sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
243 bus_size_t off, uint32_t *data, bus_size_t count)
244{
245 struct sdhci_pci_softc *sc = device_get_softc(dev);
246
247 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
248}
249
250static void sdhci_pci_intr(void *arg);
251
252static void
253sdhci_lower_frequency(device_t dev)
254{
255 struct sdhci_pci_softc *sc = device_get_softc(dev);
256
257 /*
258 * Enable SD2.0 mode.
259 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
260 */
261 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
262 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
263 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
264 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
265
266 /*
267 * Some SD/MMC cards don't work with the default base
268 * clock frequency of 200 MHz. Lower it to 50 MHz.
269 */
270 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
271 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
272 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
273 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
274}
275
276static void
277sdhci_restore_frequency(device_t dev)
278{
279 struct sdhci_pci_softc *sc = device_get_softc(dev);
280
281 /* Restore mode. */
282 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
283 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
284 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
285
286 /* Restore frequency. */
287 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
288 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
289 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
290}
291
292static int
293sdhci_pci_probe(device_t dev)
294{
295 uint32_t model;
296 uint16_t subvendor;
297 uint8_t class, subclass;
298 int i, result;
299
300 model = (uint32_t)pci_get_device(dev) << 16;
301 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
302 subvendor = pci_get_subvendor(dev);
303 class = pci_get_class(dev);
304 subclass = pci_get_subclass(dev);
305
306 result = ENXIO;
307 for (i = 0; sdhci_devices[i].model != 0; i++) {
308 if (sdhci_devices[i].model == model &&
309 (sdhci_devices[i].subvendor == 0xffff ||
310 sdhci_devices[i].subvendor == subvendor)) {
311 device_set_desc(dev, sdhci_devices[i].desc);
312 result = BUS_PROBE_DEFAULT;
313 break;
314 }
315 }
316 if (result == ENXIO && class == PCIC_BASEPERIPH &&
317 subclass == PCIS_BASEPERIPH_SDHC) {
318 device_set_desc(dev, "Generic SD HCI");
319 result = BUS_PROBE_GENERIC;
320 }
321
322 return (result);
323}
324
325static int
326sdhci_pci_attach(device_t dev)
327{
328 struct sdhci_pci_softc *sc = device_get_softc(dev);
329 struct sdhci_slot *slot;
330 uint32_t model;
331 uint16_t subvendor;
332 int bar, err, rid, slots, i;
333
334 model = (uint32_t)pci_get_device(dev) << 16;
335 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
336 subvendor = pci_get_subvendor(dev);
337 /* Apply chip specific quirks. */
338 for (i = 0; sdhci_devices[i].model != 0; i++) {
339 if (sdhci_devices[i].model == model &&
340 (sdhci_devices[i].subvendor == 0xffff ||
341 sdhci_devices[i].subvendor == subvendor)) {
342 sc->quirks = sdhci_devices[i].quirks;
343 break;
344 }
345 }
346 sc->quirks &= ~sdhci_quirk_clear;
347 sc->quirks |= sdhci_quirk_set;
348
349 /* Some controllers need to be bumped into the right mode. */
350 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
351 sdhci_lower_frequency(dev);
352 /* Read slots info from PCI registers. */
353 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
354 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
355 slots = PCI_SLOT_INFO_SLOTS(slots);
356 if (slots > 6 || bar > 5) {
357 device_printf(dev, "Incorrect slots information (%d, %d).\n",
358 slots, bar);
359 return (EINVAL);
360 }
361 /* Allocate IRQ. */
362 i = 1;
363 rid = 0;
364 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
365 rid = 1;
366 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
367 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
368 if (sc->irq_res == NULL) {
369 device_printf(dev, "Can't allocate IRQ\n");
370 pci_release_msi(dev);
371 return (ENOMEM);
372 }
373 /* Scan all slots. */
374 for (i = 0; i < slots; i++) {
375 slot = &sc->slots[sc->num_slots];
376
377 /* Allocate memory. */
378 rid = PCIR_BAR(bar + i);
379 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
380 &rid, RF_ACTIVE);
381 if (sc->mem_res[i] == NULL) {
382 device_printf(dev,
383 "Can't allocate memory for slot %d\n", i);
384 continue;
385 }
386
387 slot->quirks = sc->quirks;
388
389 if (sdhci_init_slot(dev, slot, i) != 0)
390 continue;
391
392 sc->num_slots++;
393 }
394 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
395 /* Activate the interrupt */
396 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
397 NULL, sdhci_pci_intr, sc, &sc->intrhand);
398 if (err)
399 device_printf(dev, "Can't setup IRQ\n");
400 pci_enable_busmaster(dev);
401 /* Process cards detection. */
402 for (i = 0; i < sc->num_slots; i++)
403 sdhci_start_slot(&sc->slots[i]);
404
405 return (0);
406}
407
408static int
409sdhci_pci_detach(device_t dev)
410{
411 struct sdhci_pci_softc *sc = device_get_softc(dev);
412 int i;
413
414 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
415 bus_release_resource(dev, SYS_RES_IRQ,
416 rman_get_rid(sc->irq_res), sc->irq_res);
417 pci_release_msi(dev);
418
419 for (i = 0; i < sc->num_slots; i++) {
420 sdhci_cleanup_slot(&sc->slots[i]);
421 bus_release_resource(dev, SYS_RES_MEMORY,
422 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
423 }
424 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
425 sdhci_restore_frequency(dev);
426 return (0);
427}
428
429static int
430sdhci_pci_shutdown(device_t dev)
431{
432 struct sdhci_pci_softc *sc = device_get_softc(dev);
433
434 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
435 sdhci_restore_frequency(dev);
436 return (0);
437}
438
439static int
440sdhci_pci_suspend(device_t dev)
441{
442 struct sdhci_pci_softc *sc = device_get_softc(dev);
443 int i, err;
444
445 err = bus_generic_suspend(dev);
446 if (err)
447 return (err);
448 for (i = 0; i < sc->num_slots; i++)
449 sdhci_generic_suspend(&sc->slots[i]);
450 return (0);
451}
452
453static int
454sdhci_pci_resume(device_t dev)
455{
456 struct sdhci_pci_softc *sc = device_get_softc(dev);
457 int i, err;
458
459 for (i = 0; i < sc->num_slots; i++)
460 sdhci_generic_resume(&sc->slots[i]);
461 err = bus_generic_resume(dev);
462 if (err)
463 return (err);
464 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
465 sdhci_lower_frequency(dev);
466 return (0);
467}
468
469static void
470sdhci_pci_intr(void *arg)
471{
472 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
473 int i;
474
475 for (i = 0; i < sc->num_slots; i++)
476 sdhci_generic_intr(&sc->slots[i]);
477}
478
479static device_method_t sdhci_methods[] = {
480 /* device_if */
481 DEVMETHOD(device_probe, sdhci_pci_probe),
482 DEVMETHOD(device_attach, sdhci_pci_attach),
483 DEVMETHOD(device_detach, sdhci_pci_detach),
484 DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
485 DEVMETHOD(device_suspend, sdhci_pci_suspend),
486 DEVMETHOD(device_resume, sdhci_pci_resume),
487
488 /* Bus interface */
489 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
490 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
491
492 /* mmcbr_if */
493 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
494 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
495 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
496 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
497 DEVMETHOD(mmcbr_request, sdhci_generic_request),
498 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
499 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
500 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
501
502 /* SDHCI accessors */
503 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
504 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
505 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
506 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
507 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
508 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
509 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
510 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
511 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
512
513 DEVMETHOD_END
514};
515
516static driver_t sdhci_pci_driver = {
517 "sdhci_pci",
518 sdhci_methods,
519 sizeof(struct sdhci_pci_softc),
520};
521static devclass_t sdhci_pci_devclass;
522
523DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
524 NULL);
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