| sdhci.h (271051) | sdhci.h (276287) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * | 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * |
| 25 * $FreeBSD: stable/10/sys/dev/sdhci/sdhci.h 271051 2014-09-03 20:07:26Z marius $ | 25 * $FreeBSD: stable/10/sys/dev/sdhci/sdhci.h 276287 2014-12-27 04:54:36Z ian $ |
| 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 20 unchanged lines hidden (view full) --- 54/* Data timeout is invalid, should use SD clock */ 55#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10) 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1<<12) 60/* Hardware shifts the 136-bit response, don't do it in software. */ 61#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) | 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 20 unchanged lines hidden (view full) --- 54/* Data timeout is invalid, should use SD clock */ 55#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10) 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1<<12) 60/* Hardware shifts the 136-bit response, don't do it in software. */ 61#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) |
| 62/* Wait to see reset bit asserted before waiting for de-asserted */ 63#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) |
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| 62 63/* 64 * Controller registers 65 */ 66#define SDHCI_DMA_ADDRESS 0x00 67 68#define SDHCI_BLOCK_SIZE 0x04 69#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) --- 107 unchanged lines hidden (view full) --- 177#define SDHCI_INT_DATA_END_BIT 0x00400000 178#define SDHCI_INT_BUS_POWER 0x00800000 179#define SDHCI_INT_ACMD12ERR 0x01000000 180#define SDHCI_INT_ADMAERR 0x02000000 181 182#define SDHCI_INT_NORMAL_MASK 0x00007FFF 183#define SDHCI_INT_ERROR_MASK 0xFFFF8000 184 | 64 65/* 66 * Controller registers 67 */ 68#define SDHCI_DMA_ADDRESS 0x00 69 70#define SDHCI_BLOCK_SIZE 0x04 71#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) --- 107 unchanged lines hidden (view full) --- 179#define SDHCI_INT_DATA_END_BIT 0x00400000 180#define SDHCI_INT_BUS_POWER 0x00800000 181#define SDHCI_INT_ACMD12ERR 0x01000000 182#define SDHCI_INT_ADMAERR 0x02000000 183 184#define SDHCI_INT_NORMAL_MASK 0x00007FFF 185#define SDHCI_INT_ERROR_MASK 0xFFFF8000 186 |
| 185#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | 187#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ |
| 186 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) | 188 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
| 189 190#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 191 |
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| 187#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 188 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 189 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 190 SDHCI_INT_DATA_END_BIT) 191 192#define SDHCI_ACMD12_ERR 0x3C 193 194#define SDHCI_CAPABILITIES 0x40 --- 90 unchanged lines hidden --- | 192#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 193 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 194 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 195 SDHCI_INT_DATA_END_BIT) 196 197#define SDHCI_ACMD12_ERR 0x3C 198 199#define SDHCI_CAPABILITIES 0x40 --- 90 unchanged lines hidden --- |