39
40#include <machine/resource.h>
41#include <machine/bus.h>
42#include <sys/rman.h>
43
44#include <dev/pci/pcivar.h>
45
46#include <dev/puc/puc_bus.h>
47#include <dev/puc/puc_cfg.h>
48#include <dev/puc/puc_bfe.h>
49
50static puc_config_f puc_config_amc;
51static puc_config_f puc_config_diva;
52static puc_config_f puc_config_exar;
53static puc_config_f puc_config_exar_pcie;
54static puc_config_f puc_config_icbook;
55static puc_config_f puc_config_moxa;
56static puc_config_f puc_config_oxford_pci954;
57static puc_config_f puc_config_oxford_pcie;
58static puc_config_f puc_config_quatech;
59static puc_config_f puc_config_syba;
60static puc_config_f puc_config_siig;
61static puc_config_f puc_config_sunix;
62static puc_config_f puc_config_timedia;
63static puc_config_f puc_config_titan;
64
65const struct puc_cfg puc_pci_devices[] = {
66
67 { 0x0009, 0x7168, 0xffff, 0,
68 "Sunix SUN1889",
69 DEFAULT_RCLK * 8,
70 PUC_PORT_2S, 0x10, 0, 8,
71 },
72
73 { 0x103c, 0x1048, 0x103c, 0x1049,
74 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
75 DEFAULT_RCLK,
76 PUC_PORT_3S, 0x10, 0, -1,
77 .config_function = puc_config_diva
78 },
79
80 { 0x103c, 0x1048, 0x103c, 0x104a,
81 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
82 DEFAULT_RCLK,
83 PUC_PORT_2S, 0x10, 0, -1,
84 .config_function = puc_config_diva
85 },
86
87 { 0x103c, 0x1048, 0x103c, 0x104b,
88 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
89 DEFAULT_RCLK,
90 PUC_PORT_4S, 0x10, 0, -1,
91 .config_function = puc_config_diva
92 },
93
94 { 0x103c, 0x1048, 0x103c, 0x1223,
95 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
96 DEFAULT_RCLK,
97 PUC_PORT_3S, 0x10, 0, -1,
98 .config_function = puc_config_diva
99 },
100
101 { 0x103c, 0x1048, 0x103c, 0x1226,
102 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
103 DEFAULT_RCLK,
104 PUC_PORT_3S, 0x10, 0, -1,
105 .config_function = puc_config_diva
106 },
107
108 { 0x103c, 0x1048, 0x103c, 0x1282,
109 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
110 DEFAULT_RCLK,
111 PUC_PORT_3S, 0x10, 0, -1,
112 .config_function = puc_config_diva
113 },
114
115 { 0x10b5, 0x1076, 0x10b5, 0x1076,
116 "VScom PCI-800",
117 DEFAULT_RCLK * 8,
118 PUC_PORT_8S, 0x18, 0, 8,
119 },
120
121 { 0x10b5, 0x1077, 0x10b5, 0x1077,
122 "VScom PCI-400",
123 DEFAULT_RCLK * 8,
124 PUC_PORT_4S, 0x18, 0, 8,
125 },
126
127 { 0x10b5, 0x1103, 0x10b5, 0x1103,
128 "VScom PCI-200",
129 DEFAULT_RCLK * 8,
130 PUC_PORT_2S, 0x18, 4, 0,
131 },
132
133 /*
134 * Boca Research Turbo Serial 658 (8 serial port) card.
135 * Appears to be the same as Chase Research PLC PCI-FAST8
136 * and Perle PCI-FAST8 Multi-Port serial cards.
137 */
138 { 0x10b5, 0x9050, 0x12e0, 0x0021,
139 "Boca Research Turbo Serial 658",
140 DEFAULT_RCLK * 4,
141 PUC_PORT_8S, 0x18, 0, 8,
142 },
143
144 { 0x10b5, 0x9050, 0x12e0, 0x0031,
145 "Boca Research Turbo Serial 654",
146 DEFAULT_RCLK * 4,
147 PUC_PORT_4S, 0x18, 0, 8,
148 },
149
150 /*
151 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
152 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
153 * into the subsystem fields, and claims that it's a
154 * network/misc (0x02/0x80) device.
155 */
156 { 0x10b5, 0x9050, 0xd84d, 0x6808,
157 "Dolphin Peripherals 4035",
158 DEFAULT_RCLK,
159 PUC_PORT_2S, 0x18, 4, 0,
160 },
161
162 /*
163 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
164 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
165 * into the subsystem fields, and claims that it's a
166 * network/misc (0x02/0x80) device.
167 */
168 { 0x10b5, 0x9050, 0xd84d, 0x6810,
169 "Dolphin Peripherals 4014",
170 0,
171 PUC_PORT_2P, 0x20, 4, 0,
172 },
173
174 { 0x10e8, 0x818e, 0xffff, 0,
175 "Applied Micro Circuits 8 Port UART",
176 DEFAULT_RCLK,
177 PUC_PORT_8S, 0x14, -1, -1,
178 .config_function = puc_config_amc
179 },
180
181 { 0x11fe, 0x8010, 0xffff, 0,
182 "Comtrol RocketPort 550/8 RJ11 part A",
183 DEFAULT_RCLK * 4,
184 PUC_PORT_4S, 0x10, 0, 8,
185 },
186
187 { 0x11fe, 0x8011, 0xffff, 0,
188 "Comtrol RocketPort 550/8 RJ11 part B",
189 DEFAULT_RCLK * 4,
190 PUC_PORT_4S, 0x10, 0, 8,
191 },
192
193 { 0x11fe, 0x8012, 0xffff, 0,
194 "Comtrol RocketPort 550/8 Octa part A",
195 DEFAULT_RCLK * 4,
196 PUC_PORT_4S, 0x10, 0, 8,
197 },
198
199 { 0x11fe, 0x8013, 0xffff, 0,
200 "Comtrol RocketPort 550/8 Octa part B",
201 DEFAULT_RCLK * 4,
202 PUC_PORT_4S, 0x10, 0, 8,
203 },
204
205 { 0x11fe, 0x8014, 0xffff, 0,
206 "Comtrol RocketPort 550/4 RJ45",
207 DEFAULT_RCLK * 4,
208 PUC_PORT_4S, 0x10, 0, 8,
209 },
210
211 { 0x11fe, 0x8015, 0xffff, 0,
212 "Comtrol RocketPort 550/Quad",
213 DEFAULT_RCLK * 4,
214 PUC_PORT_4S, 0x10, 0, 8,
215 },
216
217 { 0x11fe, 0x8016, 0xffff, 0,
218 "Comtrol RocketPort 550/16 part A",
219 DEFAULT_RCLK * 4,
220 PUC_PORT_4S, 0x10, 0, 8,
221 },
222
223 { 0x11fe, 0x8017, 0xffff, 0,
224 "Comtrol RocketPort 550/16 part B",
225 DEFAULT_RCLK * 4,
226 PUC_PORT_12S, 0x10, 0, 8,
227 },
228
229 { 0x11fe, 0x8018, 0xffff, 0,
230 "Comtrol RocketPort 550/8 part A",
231 DEFAULT_RCLK * 4,
232 PUC_PORT_4S, 0x10, 0, 8,
233 },
234
235 { 0x11fe, 0x8019, 0xffff, 0,
236 "Comtrol RocketPort 550/8 part B",
237 DEFAULT_RCLK * 4,
238 PUC_PORT_4S, 0x10, 0, 8,
239 },
240
241 /*
242 * IBM SurePOS 300 Series (481033H) serial ports
243 * Details can be found on the IBM RSS websites
244 */
245
246 { 0x1014, 0x0297, 0xffff, 0,
247 "IBM SurePOS 300 Series (481033H) serial ports",
248 DEFAULT_RCLK,
249 PUC_PORT_4S, 0x10, 4, 0
250 },
251
252 /*
253 * SIIG Boards.
254 *
255 * SIIG provides documentation for their boards at:
256 * <URL:http://www.siig.com/downloads.asp>
257 */
258
259 { 0x131f, 0x1010, 0xffff, 0,
260 "SIIG Cyber I/O PCI 16C550 (10x family)",
261 DEFAULT_RCLK,
262 PUC_PORT_1S1P, 0x18, 4, 0,
263 },
264
265 { 0x131f, 0x1011, 0xffff, 0,
266 "SIIG Cyber I/O PCI 16C650 (10x family)",
267 DEFAULT_RCLK,
268 PUC_PORT_1S1P, 0x18, 4, 0,
269 },
270
271 { 0x131f, 0x1012, 0xffff, 0,
272 "SIIG Cyber I/O PCI 16C850 (10x family)",
273 DEFAULT_RCLK,
274 PUC_PORT_1S1P, 0x18, 4, 0,
275 },
276
277 { 0x131f, 0x1021, 0xffff, 0,
278 "SIIG Cyber Parallel Dual PCI (10x family)",
279 0,
280 PUC_PORT_2P, 0x18, 8, 0,
281 },
282
283 { 0x131f, 0x1030, 0xffff, 0,
284 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
285 DEFAULT_RCLK,
286 PUC_PORT_2S, 0x18, 4, 0,
287 },
288
289 { 0x131f, 0x1031, 0xffff, 0,
290 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
291 DEFAULT_RCLK,
292 PUC_PORT_2S, 0x18, 4, 0,
293 },
294
295 { 0x131f, 0x1032, 0xffff, 0,
296 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
297 DEFAULT_RCLK,
298 PUC_PORT_2S, 0x18, 4, 0,
299 },
300
301 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
302 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
303 DEFAULT_RCLK,
304 PUC_PORT_2S1P, 0x18, 4, 0,
305 },
306
307 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
308 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
309 DEFAULT_RCLK,
310 PUC_PORT_2S1P, 0x18, 4, 0,
311 },
312
313 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
314 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
315 DEFAULT_RCLK,
316 PUC_PORT_2S1P, 0x18, 4, 0,
317 },
318
319 { 0x131f, 0x1050, 0xffff, 0,
320 "SIIG Cyber 4S PCI 16C550 (10x family)",
321 DEFAULT_RCLK,
322 PUC_PORT_4S, 0x18, 4, 0,
323 },
324
325 { 0x131f, 0x1051, 0xffff, 0,
326 "SIIG Cyber 4S PCI 16C650 (10x family)",
327 DEFAULT_RCLK,
328 PUC_PORT_4S, 0x18, 4, 0,
329 },
330
331 { 0x131f, 0x1052, 0xffff, 0,
332 "SIIG Cyber 4S PCI 16C850 (10x family)",
333 DEFAULT_RCLK,
334 PUC_PORT_4S, 0x18, 4, 0,
335 },
336
337 { 0x131f, 0x2010, 0xffff, 0,
338 "SIIG Cyber I/O PCI 16C550 (20x family)",
339 DEFAULT_RCLK,
340 PUC_PORT_1S1P, 0x10, 4, 0,
341 },
342
343 { 0x131f, 0x2011, 0xffff, 0,
344 "SIIG Cyber I/O PCI 16C650 (20x family)",
345 DEFAULT_RCLK,
346 PUC_PORT_1S1P, 0x10, 4, 0,
347 },
348
349 { 0x131f, 0x2012, 0xffff, 0,
350 "SIIG Cyber I/O PCI 16C850 (20x family)",
351 DEFAULT_RCLK,
352 PUC_PORT_1S1P, 0x10, 4, 0,
353 },
354
355 { 0x131f, 0x2021, 0xffff, 0,
356 "SIIG Cyber Parallel Dual PCI (20x family)",
357 0,
358 PUC_PORT_2P, 0x10, 8, 0,
359 },
360
361 { 0x131f, 0x2030, 0xffff, 0,
362 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
363 DEFAULT_RCLK,
364 PUC_PORT_2S, 0x10, 4, 0,
365 },
366
367 { 0x131f, 0x2031, 0xffff, 0,
368 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
369 DEFAULT_RCLK,
370 PUC_PORT_2S, 0x10, 4, 0,
371 },
372
373 { 0x131f, 0x2032, 0xffff, 0,
374 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
375 DEFAULT_RCLK,
376 PUC_PORT_2S, 0x10, 4, 0,
377 },
378
379 { 0x131f, 0x2040, 0xffff, 0,
380 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
381 DEFAULT_RCLK,
382 PUC_PORT_1S2P, 0x10, -1, 0,
383 .config_function = puc_config_siig
384 },
385
386 { 0x131f, 0x2041, 0xffff, 0,
387 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
388 DEFAULT_RCLK,
389 PUC_PORT_1S2P, 0x10, -1, 0,
390 .config_function = puc_config_siig
391 },
392
393 { 0x131f, 0x2042, 0xffff, 0,
394 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
395 DEFAULT_RCLK,
396 PUC_PORT_1S2P, 0x10, -1, 0,
397 .config_function = puc_config_siig
398 },
399
400 { 0x131f, 0x2050, 0xffff, 0,
401 "SIIG Cyber 4S PCI 16C550 (20x family)",
402 DEFAULT_RCLK,
403 PUC_PORT_4S, 0x10, 4, 0,
404 },
405
406 { 0x131f, 0x2051, 0xffff, 0,
407 "SIIG Cyber 4S PCI 16C650 (20x family)",
408 DEFAULT_RCLK,
409 PUC_PORT_4S, 0x10, 4, 0,
410 },
411
412 { 0x131f, 0x2052, 0xffff, 0,
413 "SIIG Cyber 4S PCI 16C850 (20x family)",
414 DEFAULT_RCLK,
415 PUC_PORT_4S, 0x10, 4, 0,
416 },
417
418 { 0x131f, 0x2060, 0xffff, 0,
419 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
420 DEFAULT_RCLK,
421 PUC_PORT_2S1P, 0x10, 4, 0,
422 },
423
424 { 0x131f, 0x2061, 0xffff, 0,
425 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
426 DEFAULT_RCLK,
427 PUC_PORT_2S1P, 0x10, 4, 0,
428 },
429
430 { 0x131f, 0x2062, 0xffff, 0,
431 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
432 DEFAULT_RCLK,
433 PUC_PORT_2S1P, 0x10, 4, 0,
434 },
435
436 { 0x131f, 0x2081, 0xffff, 0,
437 "SIIG PS8000 8S PCI 16C650 (20x family)",
438 DEFAULT_RCLK,
439 PUC_PORT_8S, 0x10, -1, -1,
440 .config_function = puc_config_siig
441 },
442
443 { 0x135c, 0x0010, 0xffff, 0,
444 "Quatech QSC-100",
445 -3, /* max 8x clock rate */
446 PUC_PORT_4S, 0x14, 0, 8,
447 .config_function = puc_config_quatech
448 },
449
450 { 0x135c, 0x0020, 0xffff, 0,
451 "Quatech DSC-100",
452 -1, /* max 2x clock rate */
453 PUC_PORT_2S, 0x14, 0, 8,
454 .config_function = puc_config_quatech
455 },
456
457 { 0x135c, 0x0030, 0xffff, 0,
458 "Quatech DSC-200/300",
459 -1, /* max 2x clock rate */
460 PUC_PORT_2S, 0x14, 0, 8,
461 .config_function = puc_config_quatech
462 },
463
464 { 0x135c, 0x0040, 0xffff, 0,
465 "Quatech QSC-200/300",
466 -3, /* max 8x clock rate */
467 PUC_PORT_4S, 0x14, 0, 8,
468 .config_function = puc_config_quatech
469 },
470
471 { 0x135c, 0x0050, 0xffff, 0,
472 "Quatech ESC-100D",
473 -3, /* max 8x clock rate */
474 PUC_PORT_8S, 0x14, 0, 8,
475 .config_function = puc_config_quatech
476 },
477
478 { 0x135c, 0x0060, 0xffff, 0,
479 "Quatech ESC-100M",
480 -3, /* max 8x clock rate */
481 PUC_PORT_8S, 0x14, 0, 8,
482 .config_function = puc_config_quatech
483 },
484
485 { 0x135c, 0x0170, 0xffff, 0,
486 "Quatech QSCLP-100",
487 -1, /* max 2x clock rate */
488 PUC_PORT_4S, 0x18, 0, 8,
489 .config_function = puc_config_quatech
490 },
491
492 { 0x135c, 0x0180, 0xffff, 0,
493 "Quatech DSCLP-100",
494 -1, /* max 3x clock rate */
495 PUC_PORT_2S, 0x18, 0, 8,
496 .config_function = puc_config_quatech
497 },
498
499 { 0x135c, 0x01b0, 0xffff, 0,
500 "Quatech DSCLP-200/300",
501 -1, /* max 2x clock rate */
502 PUC_PORT_2S, 0x18, 0, 8,
503 .config_function = puc_config_quatech
504 },
505
506 { 0x135c, 0x01e0, 0xffff, 0,
507 "Quatech ESCLP-100",
508 -3, /* max 8x clock rate */
509 PUC_PORT_8S, 0x10, 0, 8,
510 .config_function = puc_config_quatech
511 },
512
513 { 0x1393, 0x1024, 0xffff, 0,
514 "Moxa Technologies, Smartio CP-102E/PCIe",
515 DEFAULT_RCLK * 8,
516 PUC_PORT_2S, 0x14, 0, -1,
517 .config_function = puc_config_moxa
518 },
519
520 { 0x1393, 0x1025, 0xffff, 0,
521 "Moxa Technologies, Smartio CP-102EL/PCIe",
522 DEFAULT_RCLK * 8,
523 PUC_PORT_2S, 0x14, 0, -1,
524 .config_function = puc_config_moxa
525 },
526
527 { 0x1393, 0x1040, 0xffff, 0,
528 "Moxa Technologies, Smartio C104H/PCI",
529 DEFAULT_RCLK * 8,
530 PUC_PORT_4S, 0x18, 0, 8,
531 },
532
533 { 0x1393, 0x1041, 0xffff, 0,
534 "Moxa Technologies, Smartio CP-104UL/PCI",
535 DEFAULT_RCLK * 8,
536 PUC_PORT_4S, 0x18, 0, 8,
537 },
538
539 { 0x1393, 0x1042, 0xffff, 0,
540 "Moxa Technologies, Smartio CP-104JU/PCI",
541 DEFAULT_RCLK * 8,
542 PUC_PORT_4S, 0x18, 0, 8,
543 },
544
545 { 0x1393, 0x1043, 0xffff, 0,
546 "Moxa Technologies, Smartio CP-104EL/PCIe",
547 DEFAULT_RCLK * 8,
548 PUC_PORT_4S, 0x18, 0, 8,
549 },
550
551 { 0x1393, 0x1045, 0xffff, 0,
552 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
553 DEFAULT_RCLK * 8,
554 PUC_PORT_4S, 0x14, 0, -1,
555 .config_function = puc_config_moxa
556 },
557
558 { 0x1393, 0x1120, 0xffff, 0,
559 "Moxa Technologies, CP-112UL",
560 DEFAULT_RCLK * 8,
561 PUC_PORT_2S, 0x18, 0, 8,
562 },
563
564 { 0x1393, 0x1141, 0xffff, 0,
565 "Moxa Technologies, Industio CP-114",
566 DEFAULT_RCLK * 8,
567 PUC_PORT_4S, 0x18, 0, 8,
568 },
569
570 { 0x1393, 0x1144, 0xffff, 0,
571 "Moxa Technologies, Smartio CP-114EL/PCIe",
572 DEFAULT_RCLK * 8,
573 PUC_PORT_4S, 0x14, 0, -1,
574 .config_function = puc_config_moxa
575 },
576
577 { 0x1393, 0x1182, 0xffff, 0,
578 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
579 DEFAULT_RCLK * 8,
580 PUC_PORT_8S, 0x14, 0, -1,
581 .config_function = puc_config_moxa
582 },
583
584 { 0x1393, 0x1680, 0xffff, 0,
585 "Moxa Technologies, C168H/PCI",
586 DEFAULT_RCLK * 8,
587 PUC_PORT_8S, 0x18, 0, 8,
588 },
589
590 { 0x1393, 0x1681, 0xffff, 0,
591 "Moxa Technologies, C168U/PCI",
592 DEFAULT_RCLK * 8,
593 PUC_PORT_8S, 0x18, 0, 8,
594 },
595
596 { 0x1393, 0x1682, 0xffff, 0,
597 "Moxa Technologies, CP-168EL/PCIe",
598 DEFAULT_RCLK * 8,
599 PUC_PORT_8S, 0x18, 0, 8,
600 },
601
602 { 0x1393, 0x1683, 0xffff, 0,
603 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
604 DEFAULT_RCLK * 8,
605 PUC_PORT_8S, 0x14, 0, -1,
606 .config_function = puc_config_moxa
607 },
608
609 { 0x13a8, 0x0152, 0xffff, 0,
610 "Exar XR17C/D152",
611 DEFAULT_RCLK * 8,
612 PUC_PORT_2S, 0x10, 0, -1,
613 .config_function = puc_config_exar
614 },
615
616 { 0x13a8, 0x0154, 0xffff, 0,
617 "Exar XR17C154",
618 DEFAULT_RCLK * 8,
619 PUC_PORT_4S, 0x10, 0, -1,
620 .config_function = puc_config_exar
621 },
622
623 { 0x13a8, 0x0158, 0xffff, 0,
624 "Exar XR17C158",
625 DEFAULT_RCLK * 8,
626 PUC_PORT_8S, 0x10, 0, -1,
627 .config_function = puc_config_exar
628 },
629
630 { 0x13a8, 0x0258, 0xffff, 0,
631 "Exar XR17V258IV",
632 DEFAULT_RCLK * 8,
633 PUC_PORT_8S, 0x10, 0, -1,
634 .config_function = puc_config_exar
635 },
636
637 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
638 { 0x13a8, 0x0358, 0xffff, 0,
639 "Exar XR17V358",
640 125000000,
641 PUC_PORT_8S, 0x10, 0, -1,
642 .config_function = puc_config_exar_pcie
643 },
644
645 { 0x13fe, 0x1600, 0x1602, 0x0002,
646 "Advantech PCI-1602",
647 DEFAULT_RCLK * 8,
648 PUC_PORT_2S, 0x10, 0, 8,
649 },
650
651 { 0x1407, 0x0100, 0xffff, 0,
652 "Lava Computers Dual Serial",
653 DEFAULT_RCLK,
654 PUC_PORT_2S, 0x10, 4, 0,
655 },
656
657 { 0x1407, 0x0101, 0xffff, 0,
658 "Lava Computers Quatro A",
659 DEFAULT_RCLK,
660 PUC_PORT_2S, 0x10, 4, 0,
661 },
662
663 { 0x1407, 0x0102, 0xffff, 0,
664 "Lava Computers Quatro B",
665 DEFAULT_RCLK,
666 PUC_PORT_2S, 0x10, 4, 0,
667 },
668
669 { 0x1407, 0x0120, 0xffff, 0,
670 "Lava Computers Quattro-PCI A",
671 DEFAULT_RCLK,
672 PUC_PORT_2S, 0x10, 4, 0,
673 },
674
675 { 0x1407, 0x0121, 0xffff, 0,
676 "Lava Computers Quattro-PCI B",
677 DEFAULT_RCLK,
678 PUC_PORT_2S, 0x10, 4, 0,
679 },
680
681 { 0x1407, 0x0180, 0xffff, 0,
682 "Lava Computers Octo A",
683 DEFAULT_RCLK,
684 PUC_PORT_4S, 0x10, 4, 0,
685 },
686
687 { 0x1407, 0x0181, 0xffff, 0,
688 "Lava Computers Octo B",
689 DEFAULT_RCLK,
690 PUC_PORT_4S, 0x10, 4, 0,
691 },
692
693 { 0x1409, 0x7268, 0xffff, 0,
694 "Sunix SUN1888",
695 0,
696 PUC_PORT_2P, 0x10, 0, 8,
697 },
698
699 { 0x1409, 0x7168, 0xffff, 0,
700 NULL,
701 DEFAULT_RCLK * 8,
702 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
703 .config_function = puc_config_timedia
704 },
705
706 /*
707 * Boards with an Oxford Semiconductor chip.
708 *
709 * Oxford Semiconductor provides documentation for their chip at:
710 * <URL:http://www.plxtech.com/products/uart/>
711 *
712 * As sold by Kouwell <URL:http://www.kouwell.com/>.
713 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
714 */
715 {
716 0x1415, 0x9501, 0x10fc, 0xc070,
717 "I-O DATA RSA-PCI2/R",
718 DEFAULT_RCLK * 8,
719 PUC_PORT_2S, 0x10, 0, 8,
720 },
721
722 { 0x1415, 0x9501, 0x131f, 0x2050,
723 "SIIG Cyber 4 PCI 16550",
724 DEFAULT_RCLK * 10,
725 PUC_PORT_4S, 0x10, 0, 8,
726 },
727
728 { 0x1415, 0x9501, 0x131f, 0x2051,
729 "SIIG Cyber 4S PCI 16C650 (20x family)",
730 DEFAULT_RCLK * 10,
731 PUC_PORT_4S, 0x10, 0, 8,
732 },
733
734 { 0x1415, 0x9501, 0x131f, 0x2052,
735 "SIIG Quartet Serial 850",
736 DEFAULT_RCLK * 10,
737 PUC_PORT_4S, 0x10, 0, 8,
738 },
739
740 { 0x1415, 0x9501, 0x14db, 0x2150,
741 "Kuroutoshikou SERIAL4P-LPPCI2",
742 DEFAULT_RCLK * 10,
743 PUC_PORT_4S, 0x10, 0, 8,
744 },
745
746 { 0x1415, 0x9501, 0xffff, 0,
747 "Oxford Semiconductor OX16PCI954 UARTs",
748 0,
749 PUC_PORT_4S, 0x10, 0, 8,
750 .config_function = puc_config_oxford_pci954
751 },
752
753 { 0x1415, 0x950a, 0x131f, 0x2030,
754 "SIIG Cyber 2S PCIe",
755 DEFAULT_RCLK * 10,
756 PUC_PORT_2S, 0x10, 0, 8,
757 },
758
759 { 0x1415, 0x950a, 0x131f, 0x2032,
760 "SIIG Cyber Serial Dual PCI 16C850",
761 DEFAULT_RCLK * 10,
762 PUC_PORT_4S, 0x10, 0, 8,
763 },
764
765 { 0x1415, 0x950a, 0xffff, 0,
766 "Oxford Semiconductor OX16PCI954 UARTs",
767 DEFAULT_RCLK,
768 PUC_PORT_4S, 0x10, 0, 8,
769 },
770
771 { 0x1415, 0x9511, 0xffff, 0,
772 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
773 DEFAULT_RCLK,
774 PUC_PORT_4S, 0x10, 0, 8,
775 },
776
777 { 0x1415, 0x9521, 0xffff, 0,
778 "Oxford Semiconductor OX16PCI952 UARTs",
779 DEFAULT_RCLK,
780 PUC_PORT_2S, 0x10, 4, 0,
781 },
782
783 { 0x1415, 0x9538, 0xffff, 0,
784 "Oxford Semiconductor OX16PCI958 UARTs",
785 DEFAULT_RCLK,
786 PUC_PORT_8S, 0x18, 0, 8,
787 },
788
789 /*
790 * Perle boards use Oxford Semiconductor chips, but they store the
791 * Oxford Semiconductor device ID as a subvendor device ID and use
792 * their own device IDs.
793 */
794
795 { 0x155f, 0x0331, 0xffff, 0,
796 "Perle Ultraport4 Express",
797 DEFAULT_RCLK * 8,
798 PUC_PORT_4S, 0x10, 0, 8,
799 },
800
801 { 0x155f, 0xB012, 0xffff, 0,
802 "Perle Speed2 LE",
803 DEFAULT_RCLK * 8,
804 PUC_PORT_2S, 0x10, 0, 8,
805 },
806
807 { 0x155f, 0xB022, 0xffff, 0,
808 "Perle Speed2 LE",
809 DEFAULT_RCLK * 8,
810 PUC_PORT_2S, 0x10, 0, 8,
811 },
812
813 { 0x155f, 0xB004, 0xffff, 0,
814 "Perle Speed4 LE",
815 DEFAULT_RCLK * 8,
816 PUC_PORT_4S, 0x10, 0, 8,
817 },
818
819 { 0x155f, 0xB008, 0xffff, 0,
820 "Perle Speed8 LE",
821 DEFAULT_RCLK * 8,
822 PUC_PORT_8S, 0x10, 0, 8,
823 },
824
825
826 /*
827 * Oxford Semiconductor PCI Express Expresso family
828 *
829 * Found in many 'native' PCI Express serial boards such as:
830 *
831 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
832 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
833 *
834 * Lindy 51189 (4 port)
835 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
836 *
837 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
838 * <URL:http://www.startech.com>
839 */
840
841 { 0x1415, 0xc11b, 0xffff, 0,
842 "Oxford Semiconductor OXPCIe952 1S1P",
843 DEFAULT_RCLK * 0x22,
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
845 .config_function = puc_config_oxford_pcie
846 },
847
848 { 0x1415, 0xc138, 0xffff, 0,
849 "Oxford Semiconductor OXPCIe952 UARTs",
850 DEFAULT_RCLK * 0x22,
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
852 .config_function = puc_config_oxford_pcie
853 },
854
855 { 0x1415, 0xc158, 0xffff, 0,
856 "Oxford Semiconductor OXPCIe952 UARTs",
857 DEFAULT_RCLK * 0x22,
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
859 .config_function = puc_config_oxford_pcie
860 },
861
862 { 0x1415, 0xc15d, 0xffff, 0,
863 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
864 DEFAULT_RCLK * 0x22,
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
866 .config_function = puc_config_oxford_pcie
867 },
868
869 { 0x1415, 0xc208, 0xffff, 0,
870 "Oxford Semiconductor OXPCIe954 UARTs",
871 DEFAULT_RCLK * 0x22,
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
873 .config_function = puc_config_oxford_pcie
874 },
875
876 { 0x1415, 0xc20d, 0xffff, 0,
877 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
878 DEFAULT_RCLK * 0x22,
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
880 .config_function = puc_config_oxford_pcie
881 },
882
883 { 0x1415, 0xc308, 0xffff, 0,
884 "Oxford Semiconductor OXPCIe958 UARTs",
885 DEFAULT_RCLK * 0x22,
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
887 .config_function = puc_config_oxford_pcie
888 },
889
890 { 0x1415, 0xc30d, 0xffff, 0,
891 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
892 DEFAULT_RCLK * 0x22,
893 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
894 .config_function = puc_config_oxford_pcie
895 },
896
897 { 0x14d2, 0x8010, 0xffff, 0,
898 "VScom PCI-100L",
899 DEFAULT_RCLK * 8,
900 PUC_PORT_1S, 0x14, 0, 0,
901 },
902
903 { 0x14d2, 0x8020, 0xffff, 0,
904 "VScom PCI-200L",
905 DEFAULT_RCLK * 8,
906 PUC_PORT_2S, 0x14, 4, 0,
907 },
908
909 { 0x14d2, 0x8028, 0xffff, 0,
910 "VScom 200Li",
911 DEFAULT_RCLK,
912 PUC_PORT_2S, 0x20, 0, 8,
913 },
914
915 /*
916 * VScom (Titan?) PCI-800L. More modern variant of the
917 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
918 * two of them obviously implemented as macro cells in
919 * the ASIC. This causes the weird port access pattern
920 * below, where two of the IO port ranges each access
921 * one of the ASIC UARTs, and a block of IO addresses
922 * access the external UARTs.
923 */
924 { 0x14d2, 0x8080, 0xffff, 0,
925 "Titan VScom PCI-800L",
926 DEFAULT_RCLK * 8,
927 PUC_PORT_8S, 0x14, -1, -1,
928 .config_function = puc_config_titan
929 },
930
931 /*
932 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
933 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
934 * device ID 3 and PCI device 1 device ID 4.
935 */
936 { 0x14d2, 0xa003, 0xffff, 0,
937 "Titan PCI-800H",
938 DEFAULT_RCLK * 8,
939 PUC_PORT_4S, 0x10, 0, 8,
940 },
941
942 { 0x14d2, 0xa004, 0xffff, 0,
943 "Titan PCI-800H",
944 DEFAULT_RCLK * 8,
945 PUC_PORT_4S, 0x10, 0, 8,
946 },
947
948 { 0x14d2, 0xa005, 0xffff, 0,
949 "Titan PCI-200H",
950 DEFAULT_RCLK * 8,
951 PUC_PORT_2S, 0x10, 0, 8,
952 },
953
954 { 0x14d2, 0xe020, 0xffff, 0,
955 "Titan VScom PCI-200HV2",
956 DEFAULT_RCLK * 8,
957 PUC_PORT_2S, 0x10, 4, 0,
958 },
959
960 { 0x14d2, 0xa007, 0xffff, 0,
961 "Titan VScom PCIex-800H",
962 DEFAULT_RCLK * 8,
963 PUC_PORT_4S, 0x10, 0, 8,
964 },
965
966 { 0x14d2, 0xa008, 0xffff, 0,
967 "Titan VScom PCIex-800H",
968 DEFAULT_RCLK * 8,
969 PUC_PORT_4S, 0x10, 0, 8,
970 },
971
972 { 0x14db, 0x2130, 0xffff, 0,
973 "Avlab Technology, PCI IO 2S",
974 DEFAULT_RCLK,
975 PUC_PORT_2S, 0x10, 4, 0,
976 },
977
978 { 0x14db, 0x2150, 0xffff, 0,
979 "Avlab Low Profile PCI 4 Serial",
980 DEFAULT_RCLK,
981 PUC_PORT_4S, 0x10, 4, 0,
982 },
983
984 { 0x14db, 0x2152, 0xffff, 0,
985 "Avlab Low Profile PCI 4 Serial",
986 DEFAULT_RCLK,
987 PUC_PORT_4S, 0x10, 4, 0,
988 },
989
990 { 0x1592, 0x0781, 0xffff, 0,
991 "Syba Tech Ltd. PCI-4S2P-550-ECP",
992 DEFAULT_RCLK,
993 PUC_PORT_4S1P, 0x10, 0, -1,
994 .config_function = puc_config_syba
995 },
996
997 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
998 "Sunix SER5xxxx 2-port serial",
999 DEFAULT_RCLK * 8,
1000 PUC_PORT_2S, 0x10, 0, 8,
1001 },
1002
1003 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1004 "Sunix SER5xxxx 4-port serial",
1005 DEFAULT_RCLK * 8,
1006 PUC_PORT_4S, 0x10, 0, 8,
1007 },
1008
1009 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1010 "Sunix SER5xxxx 8-port serial",
1011 DEFAULT_RCLK * 8,
1012 PUC_PORT_8S, -1, -1, -1,
1013 .config_function = puc_config_sunix
1014 },
1015
1016 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1017 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1018 DEFAULT_RCLK * 8,
1019 PUC_PORT_1S1P, -1, -1, -1,
1020 .config_function = puc_config_sunix
1021 },
1022
1023 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1024 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1025 DEFAULT_RCLK * 8,
1026 PUC_PORT_2S1P, -1, -1, -1,
1027 .config_function = puc_config_sunix
1028 },
1029
1030 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1031 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1032 DEFAULT_RCLK * 8,
1033 PUC_PORT_4S1P, -1, -1, -1,
1034 .config_function = puc_config_sunix
1035 },
1036
1037 { 0x5372, 0x6872, 0xffff, 0,
1038 "Feasso PCI FPP-02 2S1P",
1039 DEFAULT_RCLK,
1040 PUC_PORT_2S1P, 0x10, 4, 0,
1041 },
1042
1043 { 0x5372, 0x6873, 0xffff, 0,
1044 "Sun 1040 PCI Quad Serial",
1045 DEFAULT_RCLK,
1046 PUC_PORT_4S, 0x10, 4, 0,
1047 },
1048
1049 { 0x6666, 0x0001, 0xffff, 0,
1050 "Decision Computer Inc, PCCOM 4-port serial",
1051 DEFAULT_RCLK,
1052 PUC_PORT_4S, 0x1c, 0, 8,
1053 },
1054
1055 { 0x6666, 0x0002, 0xffff, 0,
1056 "Decision Computer Inc, PCCOM 8-port serial",
1057 DEFAULT_RCLK,
1058 PUC_PORT_8S, 0x1c, 0, 8,
1059 },
1060
1061 { 0x6666, 0x0004, 0xffff, 0,
1062 "PCCOM dual port RS232/422/485",
1063 DEFAULT_RCLK,
1064 PUC_PORT_2S, 0x1c, 0, 8,
1065 },
1066
1067 { 0x9710, 0x9815, 0xffff, 0,
1068 "NetMos NM9815 Dual 1284 Printer port",
1069 0,
1070 PUC_PORT_2P, 0x10, 8, 0,
1071 },
1072
1073 /*
1074 * This is more specific than the generic NM9835 entry, and is placed
1075 * here to _prevent_ puc(4) from claiming this single port card.
1076 *
1077 * uart(4) will claim this device.
1078 */
1079 { 0x9710, 0x9835, 0x1000, 1,
1080 "NetMos NM9835 based 1-port serial",
1081 DEFAULT_RCLK,
1082 PUC_PORT_1S, 0x10, 4, 0,
1083 },
1084
1085 { 0x9710, 0x9835, 0x1000, 2,
1086 "NetMos NM9835 based 2-port serial",
1087 DEFAULT_RCLK,
1088 PUC_PORT_2S, 0x10, 4, 0,
1089 },
1090
1091 { 0x9710, 0x9835, 0xffff, 0,
1092 "NetMos NM9835 Dual UART and 1284 Printer port",
1093 DEFAULT_RCLK,
1094 PUC_PORT_2S1P, 0x10, 4, 0,
1095 },
1096
1097 { 0x9710, 0x9845, 0x1000, 0x0006,
1098 "NetMos NM9845 6 Port UART",
1099 DEFAULT_RCLK,
1100 PUC_PORT_6S, 0x10, 4, 0,
1101 },
1102
1103 { 0x9710, 0x9845, 0xffff, 0,
1104 "NetMos NM9845 Quad UART and 1284 Printer port",
1105 DEFAULT_RCLK,
1106 PUC_PORT_4S1P, 0x10, 4, 0,
1107 },
1108
1109 { 0x9710, 0x9865, 0xa000, 0x3002,
1110 "NetMos NM9865 Dual UART",
1111 DEFAULT_RCLK,
1112 PUC_PORT_2S, 0x10, 4, 0,
1113 },
1114
1115 { 0x9710, 0x9865, 0xa000, 0x3003,
1116 "NetMos NM9865 Triple UART",
1117 DEFAULT_RCLK,
1118 PUC_PORT_3S, 0x10, 4, 0,
1119 },
1120
1121 { 0x9710, 0x9865, 0xa000, 0x3004,
1122 "NetMos NM9865 Quad UART",
1123 DEFAULT_RCLK,
1124 PUC_PORT_4S, 0x10, 4, 0,
1125 },
1126
1127 { 0x9710, 0x9865, 0xa000, 0x3011,
1128 "NetMos NM9865 Single UART and 1284 Printer port",
1129 DEFAULT_RCLK,
1130 PUC_PORT_1S1P, 0x10, 4, 0,
1131 },
1132
1133 { 0x9710, 0x9865, 0xa000, 0x3012,
1134 "NetMos NM9865 Dual UART and 1284 Printer port",
1135 DEFAULT_RCLK,
1136 PUC_PORT_2S1P, 0x10, 4, 0,
1137 },
1138
1139 { 0x9710, 0x9865, 0xa000, 0x3020,
1140 "NetMos NM9865 Dual 1284 Printer port",
1141 DEFAULT_RCLK,
1142 PUC_PORT_2P, 0x10, 4, 0,
1143 },
1144
1145 { 0xb00c, 0x021c, 0xffff, 0,
1146 "IC Book Labs Gunboat x4 Lite",
1147 DEFAULT_RCLK,
1148 PUC_PORT_4S, 0x10, 0, 8,
1149 .config_function = puc_config_icbook
1150 },
1151
1152 { 0xb00c, 0x031c, 0xffff, 0,
1153 "IC Book Labs Gunboat x4 Pro",
1154 DEFAULT_RCLK,
1155 PUC_PORT_4S, 0x10, 0, 8,
1156 .config_function = puc_config_icbook
1157 },
1158
1159 { 0xb00c, 0x041c, 0xffff, 0,
1160 "IC Book Labs Ironclad x8 Lite",
1161 DEFAULT_RCLK,
1162 PUC_PORT_8S, 0x10, 0, 8,
1163 .config_function = puc_config_icbook
1164 },
1165
1166 { 0xb00c, 0x051c, 0xffff, 0,
1167 "IC Book Labs Ironclad x8 Pro",
1168 DEFAULT_RCLK,
1169 PUC_PORT_8S, 0x10, 0, 8,
1170 .config_function = puc_config_icbook
1171 },
1172
1173 { 0xb00c, 0x081c, 0xffff, 0,
1174 "IC Book Labs Dreadnought x16 Pro",
1175 DEFAULT_RCLK * 8,
1176 PUC_PORT_16S, 0x10, 0, 8,
1177 .config_function = puc_config_icbook
1178 },
1179
1180 { 0xb00c, 0x091c, 0xffff, 0,
1181 "IC Book Labs Dreadnought x16 Lite",
1182 DEFAULT_RCLK,
1183 PUC_PORT_16S, 0x10, 0, 8,
1184 .config_function = puc_config_icbook
1185 },
1186
1187 { 0xb00c, 0x0a1c, 0xffff, 0,
1188 "IC Book Labs Gunboat x2 Low Profile",
1189 DEFAULT_RCLK,
1190 PUC_PORT_2S, 0x10, 0, 8,
1191 },
1192
1193 { 0xb00c, 0x0b1c, 0xffff, 0,
1194 "IC Book Labs Gunboat x4 Low Profile",
1195 DEFAULT_RCLK,
1196 PUC_PORT_4S, 0x10, 0, 8,
1197 .config_function = puc_config_icbook
1198 },
1199
1200 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1201};
1202
1203static int
1204puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1205 intptr_t *res)
1206{
1207 switch (cmd) {
1208 case PUC_CFG_GET_OFS:
1209 *res = 8 * (port & 1);
1210 return (0);
1211 case PUC_CFG_GET_RID:
1212 *res = 0x14 + (port >> 1) * 4;
1213 return (0);
1214 default:
1215 break;
1216 }
1217 return (ENXIO);
1218}
1219
1220static int
1221puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1222 intptr_t *res)
1223{
1224 const struct puc_cfg *cfg = sc->sc_cfg;
1225
1226 if (cmd == PUC_CFG_GET_OFS) {
1227 if (cfg->subdevice == 0x1282) /* Everest SP */
1228 port <<= 1;
1229 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1230 port = (port == 3) ? 4 : port;
1231 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1232 return (0);
1233 }
1234 return (ENXIO);
1235}
1236
1237static int
1238puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1239 intptr_t *res)
1240{
1241 if (cmd == PUC_CFG_GET_OFS) {
1242 *res = port * 0x200;
1243 return (0);
1244 }
1245 return (ENXIO);
1246}
1247
1248static int
1249puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1250 intptr_t *res)
1251{
1252 if (cmd == PUC_CFG_GET_OFS) {
1253 *res = port * 0x400;
1254 return (0);
1255 }
1256 return (ENXIO);
1257}
1258
1259static int
1260puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1261 intptr_t *res)
1262{
1263 if (cmd == PUC_CFG_GET_ILR) {
1264 *res = PUC_ILR_DIGI;
1265 return (0);
1266 }
1267 return (ENXIO);
1268}
1269
1270static int
1271puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1272 intptr_t *res)
1273{
1274 if (cmd == PUC_CFG_GET_OFS) {
1275 const struct puc_cfg *cfg = sc->sc_cfg;
1276
1277 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
1278 port = 7;
1279 *res = port * 0x200;
1280
1281 return 0;
1282 }
1283 return (ENXIO);
1284}
1285
1286static int
1287puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1288 intptr_t *res)
1289{
1290 const struct puc_cfg *cfg = sc->sc_cfg;
1291 struct puc_bar *bar;
1292 uint8_t v0, v1;
1293
1294 switch (cmd) {
1295 case PUC_CFG_SETUP:
1296 /*
1297 * Check if the scratchpad register is enabled or if the
1298 * interrupt status and options registers are active.
1299 */
1300 bar = puc_get_bar(sc, cfg->rid);
1301 if (bar == NULL)
1302 return (ENXIO);
1303 /* Set DLAB in the LCR register of UART 0. */
1304 bus_write_1(bar->b_res, 3, 0x80);
1305 /* Write 0 to the SPR register of UART 0. */
1306 bus_write_1(bar->b_res, 7, 0);
1307 /* Read back the contents of the SPR register of UART 0. */
1308 v0 = bus_read_1(bar->b_res, 7);
1309 /* Write a specific value to the SPR register of UART 0. */
1310 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1311 /* Read back the contents of the SPR register of UART 0. */
1312 v1 = bus_read_1(bar->b_res, 7);
1313 /* Clear DLAB in the LCR register of UART 0. */
1314 bus_write_1(bar->b_res, 3, 0);
1315 /* Save the two values read-back from the SPR register. */
1316 sc->sc_cfg_data = (v0 << 8) | v1;
1317 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1318 /*
1319 * The SPR register echoed the two values written
1320 * by us. This means that the SPAD jumper is set.
1321 */
1322 device_printf(sc->sc_dev, "warning: extra features "
1323 "not usable -- SPAD compatibility enabled\n");
1324 return (0);
1325 }
1326 if (v0 != 0) {
1327 /*
1328 * The first value doesn't match. This can only mean
1329 * that the SPAD jumper is not set and that a non-
1330 * standard fixed clock multiplier jumper is set.
1331 */
1332 if (bootverbose)
1333 device_printf(sc->sc_dev, "fixed clock rate "
1334 "multiplier of %d\n", 1 << v0);
1335 if (v0 < -cfg->clock)
1336 device_printf(sc->sc_dev, "warning: "
1337 "suboptimal fixed clock rate multiplier "
1338 "setting\n");
1339 return (0);
1340 }
1341 /*
1342 * The first value matched, but the second didn't. We know
1343 * that the SPAD jumper is not set. We also know that the
1344 * clock rate multiplier is software controlled *and* that
1345 * we just programmed it to the maximum allowed.
1346 */
1347 if (bootverbose)
1348 device_printf(sc->sc_dev, "clock rate multiplier of "
1349 "%d selected\n", 1 << -cfg->clock);
1350 return (0);
1351 case PUC_CFG_GET_CLOCK:
1352 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1353 v1 = sc->sc_cfg_data & 0xff;
1354 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1355 /*
1356 * XXX With the SPAD jumper applied, there's no
1357 * easy way of knowing if there's also a clock
1358 * rate multiplier jumper installed. Let's hope
1359 * not...
1360 */
1361 *res = DEFAULT_RCLK;
1362 } else if (v0 == 0) {
1363 /*
1364 * No clock rate multiplier jumper installed,
1365 * so we programmed the board with the maximum
1366 * multiplier allowed as given to us in the
1367 * clock field of the config record (negated).
1368 */
1369 *res = DEFAULT_RCLK << -cfg->clock;
1370 } else
1371 *res = DEFAULT_RCLK << v0;
1372 return (0);
1373 case PUC_CFG_GET_ILR:
1374 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1375 v1 = sc->sc_cfg_data & 0xff;
1376 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1377 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1378 return (0);
1379 default:
1380 break;
1381 }
1382 return (ENXIO);
1383}
1384
1385static int
1386puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1387 intptr_t *res)
1388{
1389 static int base[] = { 0x251, 0x3f0, 0 };
1390 const struct puc_cfg *cfg = sc->sc_cfg;
1391 struct puc_bar *bar;
1392 int efir, idx, ofs;
1393 uint8_t v;
1394
1395 switch (cmd) {
1396 case PUC_CFG_SETUP:
1397 bar = puc_get_bar(sc, cfg->rid);
1398 if (bar == NULL)
1399 return (ENXIO);
1400
1401 /* configure both W83877TFs */
1402 bus_write_1(bar->b_res, 0x250, 0x89);
1403 bus_write_1(bar->b_res, 0x3f0, 0x87);
1404 bus_write_1(bar->b_res, 0x3f0, 0x87);
1405 idx = 0;
1406 while (base[idx] != 0) {
1407 efir = base[idx];
1408 bus_write_1(bar->b_res, efir, 0x09);
1409 v = bus_read_1(bar->b_res, efir + 1);
1410 if ((v & 0x0f) != 0x0c)
1411 return (ENXIO);
1412 bus_write_1(bar->b_res, efir, 0x16);
1413 v = bus_read_1(bar->b_res, efir + 1);
1414 bus_write_1(bar->b_res, efir, 0x16);
1415 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1416 bus_write_1(bar->b_res, efir, 0x16);
1417 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1418 ofs = base[idx] & 0x300;
1419 bus_write_1(bar->b_res, efir, 0x23);
1420 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1421 bus_write_1(bar->b_res, efir, 0x24);
1422 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1423 bus_write_1(bar->b_res, efir, 0x25);
1424 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1425 bus_write_1(bar->b_res, efir, 0x17);
1426 bus_write_1(bar->b_res, efir + 1, 0x03);
1427 bus_write_1(bar->b_res, efir, 0x28);
1428 bus_write_1(bar->b_res, efir + 1, 0x43);
1429 idx++;
1430 }
1431 bus_write_1(bar->b_res, 0x250, 0xaa);
1432 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1433 return (0);
1434 case PUC_CFG_GET_OFS:
1435 switch (port) {
1436 case 0:
1437 *res = 0x2f8;
1438 return (0);
1439 case 1:
1440 *res = 0x2e8;
1441 return (0);
1442 case 2:
1443 *res = 0x3f8;
1444 return (0);
1445 case 3:
1446 *res = 0x3e8;
1447 return (0);
1448 case 4:
1449 *res = 0x278;
1450 return (0);
1451 }
1452 break;
1453 default:
1454 break;
1455 }
1456 return (ENXIO);
1457}
1458
1459static int
1460puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1461 intptr_t *res)
1462{
1463 const struct puc_cfg *cfg = sc->sc_cfg;
1464
1465 switch (cmd) {
1466 case PUC_CFG_GET_OFS:
1467 if (cfg->ports == PUC_PORT_8S) {
1468 *res = (port > 4) ? 8 * (port - 4) : 0;
1469 return (0);
1470 }
1471 break;
1472 case PUC_CFG_GET_RID:
1473 if (cfg->ports == PUC_PORT_8S) {
1474 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1475 return (0);
1476 }
1477 if (cfg->ports == PUC_PORT_2S1P) {
1478 switch (port) {
1479 case 0: *res = 0x10; return (0);
1480 case 1: *res = 0x14; return (0);
1481 case 2: *res = 0x1c; return (0);
1482 }
1483 }
1484 break;
1485 default:
1486 break;
1487 }
1488 return (ENXIO);
1489}
1490
1491static int
1492puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1493 intptr_t *res)
1494{
1495 static const uint16_t dual[] = {
1496 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1497 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1498 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1499 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1500 0xD079, 0
1501 };
1502 static const uint16_t quad[] = {
1503 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1504 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1505 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1506 0xB157, 0
1507 };
1508 static const uint16_t octa[] = {
1509 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1510 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1511 };
1512 static const struct {
1513 int ports;
1514 const uint16_t *ids;
1515 } subdevs[] = {
1516 { 2, dual },
1517 { 4, quad },
1518 { 8, octa },
1519 { 0, NULL }
1520 };
1521 static char desc[64];
1522 int dev, id;
1523 uint16_t subdev;
1524
1525 switch (cmd) {
1526 case PUC_CFG_GET_CLOCK:
1527 if (port < 2)
1528 *res = DEFAULT_RCLK * 8;
1529 else
1530 *res = DEFAULT_RCLK;
1531 return (0);
1532 case PUC_CFG_GET_DESC:
1533 snprintf(desc, sizeof(desc),
1534 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1535 *res = (intptr_t)desc;
1536 return (0);
1537 case PUC_CFG_GET_NPORTS:
1538 subdev = pci_get_subdevice(sc->sc_dev);
1539 dev = 0;
1540 while (subdevs[dev].ports != 0) {
1541 id = 0;
1542 while (subdevs[dev].ids[id] != 0) {
1543 if (subdev == subdevs[dev].ids[id]) {
1544 sc->sc_cfg_data = subdevs[dev].ports;
1545 *res = sc->sc_cfg_data;
1546 return (0);
1547 }
1548 id++;
1549 }
1550 dev++;
1551 }
1552 return (ENXIO);
1553 case PUC_CFG_GET_OFS:
1554 *res = (port == 1 || port == 3) ? 8 : 0;
1555 return (0);
1556 case PUC_CFG_GET_RID:
1557 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1558 return (0);
1559 case PUC_CFG_GET_TYPE:
1560 *res = PUC_TYPE_SERIAL;
1561 return (0);
1562 default:
1563 break;
1564 }
1565 return (ENXIO);
1566}
1567
1568static int
1569puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1570 int port __unused, intptr_t *res)
1571{
1572
1573 switch (cmd) {
1574 case PUC_CFG_GET_CLOCK:
1575 /*
1576 * OXu16PCI954 use a 14.7456 MHz clock by default while
1577 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1578 */
1579 if (pci_get_revid(sc->sc_dev) == 1)
1580 *res = DEFAULT_RCLK * 8;
1581 else
1582 *res = DEFAULT_RCLK;
1583 return (0);
1584 default:
1585 break;
1586 }
1587 return (ENXIO);
1588}
1589
1590static int
1591puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1592 intptr_t *res)
1593{
1594 const struct puc_cfg *cfg = sc->sc_cfg;
1595 int idx;
1596 struct puc_bar *bar;
1597 uint8_t value;
1598
1599 switch (cmd) {
1600 case PUC_CFG_SETUP:
1601 device_printf(sc->sc_dev, "%d UARTs detected\n",
1602 sc->sc_nports);
1603
1604 /* Set UARTs to enhanced mode */
1605 bar = puc_get_bar(sc, cfg->rid);
1606 if (bar == NULL)
1607 return (ENXIO);
1608 for (idx = 0; idx < sc->sc_nports; idx++) {
1609 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1610 0x92);
1611 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1612 value | 0x10);
1613 }
1614 return (0);
1615 case PUC_CFG_GET_LEN:
1616 *res = 0x200;
1617 return (0);
1618 case PUC_CFG_GET_NPORTS:
1619 /*
1620 * Check if we are being called from puc_bfe_attach()
1621 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1622 * puc_get_bar(), so we return a value of 16. This has cosmetic
1623 * side-effects at worst; in PUC_CFG_GET_DESC,
1624 * (int)sc->sc_cfg_data will not contain the true number of
1625 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1626 * call for this device family anyway.
1627 *
1628 * The check is for initialisation of sc->sc_bar[idx], which is
1629 * only done in puc_bfe_attach().
1630 */
1631 idx = 0;
1632 do {
1633 if (sc->sc_bar[idx++].b_rid != -1) {
1634 sc->sc_cfg_data = 16;
1635 *res = sc->sc_cfg_data;
1636 return (0);
1637 }
1638 } while (idx < PUC_PCI_BARS);
1639
1640 bar = puc_get_bar(sc, cfg->rid);
1641 if (bar == NULL)
1642 return (ENXIO);
1643
1644 value = bus_read_1(bar->b_res, 0x04);
1645 if (value == 0)
1646 return (ENXIO);
1647
1648 sc->sc_cfg_data = value;
1649 *res = sc->sc_cfg_data;
1650 return (0);
1651 case PUC_CFG_GET_OFS:
1652 *res = 0x1000 + (port << 9);
1653 return (0);
1654 case PUC_CFG_GET_TYPE:
1655 *res = PUC_TYPE_SERIAL;
1656 return (0);
1657 default:
1658 break;
1659 }
1660 return (ENXIO);
1661}
1662
1663static int
1664puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1665 intptr_t *res)
1666{
1667 int error;
1668
1669 switch (cmd) {
1670 case PUC_CFG_GET_OFS:
1671 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1672 if (error != 0)
1673 return (error);
1674 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1675 return (0);
1676 case PUC_CFG_GET_RID:
1677 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1678 if (error != 0)
1679 return (error);
1680 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1681 return (0);
1682 default:
1683 break;
1684 }
1685 return (ENXIO);
1686}
1687
1688static int
1689puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1690 intptr_t *res)
1691{
1692 switch (cmd) {
1693 case PUC_CFG_GET_OFS:
1694 *res = (port < 3) ? 0 : (port - 2) << 3;
1695 return (0);
1696 case PUC_CFG_GET_RID:
1697 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1698 return (0);
1699 default:
1700 break;
1701 }
1702 return (ENXIO);
1703}
| 40
41#include <machine/resource.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44
45#include <dev/pci/pcivar.h>
46
47#include <dev/puc/puc_bus.h>
48#include <dev/puc/puc_cfg.h>
49#include <dev/puc/puc_bfe.h>
50
51static puc_config_f puc_config_amc;
52static puc_config_f puc_config_diva;
53static puc_config_f puc_config_exar;
54static puc_config_f puc_config_exar_pcie;
55static puc_config_f puc_config_icbook;
56static puc_config_f puc_config_moxa;
57static puc_config_f puc_config_oxford_pci954;
58static puc_config_f puc_config_oxford_pcie;
59static puc_config_f puc_config_quatech;
60static puc_config_f puc_config_syba;
61static puc_config_f puc_config_siig;
62static puc_config_f puc_config_sunix;
63static puc_config_f puc_config_timedia;
64static puc_config_f puc_config_titan;
65
66const struct puc_cfg puc_pci_devices[] = {
67
68 { 0x0009, 0x7168, 0xffff, 0,
69 "Sunix SUN1889",
70 DEFAULT_RCLK * 8,
71 PUC_PORT_2S, 0x10, 0, 8,
72 },
73
74 { 0x103c, 0x1048, 0x103c, 0x1049,
75 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
76 DEFAULT_RCLK,
77 PUC_PORT_3S, 0x10, 0, -1,
78 .config_function = puc_config_diva
79 },
80
81 { 0x103c, 0x1048, 0x103c, 0x104a,
82 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
83 DEFAULT_RCLK,
84 PUC_PORT_2S, 0x10, 0, -1,
85 .config_function = puc_config_diva
86 },
87
88 { 0x103c, 0x1048, 0x103c, 0x104b,
89 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
90 DEFAULT_RCLK,
91 PUC_PORT_4S, 0x10, 0, -1,
92 .config_function = puc_config_diva
93 },
94
95 { 0x103c, 0x1048, 0x103c, 0x1223,
96 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
97 DEFAULT_RCLK,
98 PUC_PORT_3S, 0x10, 0, -1,
99 .config_function = puc_config_diva
100 },
101
102 { 0x103c, 0x1048, 0x103c, 0x1226,
103 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
104 DEFAULT_RCLK,
105 PUC_PORT_3S, 0x10, 0, -1,
106 .config_function = puc_config_diva
107 },
108
109 { 0x103c, 0x1048, 0x103c, 0x1282,
110 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
111 DEFAULT_RCLK,
112 PUC_PORT_3S, 0x10, 0, -1,
113 .config_function = puc_config_diva
114 },
115
116 { 0x10b5, 0x1076, 0x10b5, 0x1076,
117 "VScom PCI-800",
118 DEFAULT_RCLK * 8,
119 PUC_PORT_8S, 0x18, 0, 8,
120 },
121
122 { 0x10b5, 0x1077, 0x10b5, 0x1077,
123 "VScom PCI-400",
124 DEFAULT_RCLK * 8,
125 PUC_PORT_4S, 0x18, 0, 8,
126 },
127
128 { 0x10b5, 0x1103, 0x10b5, 0x1103,
129 "VScom PCI-200",
130 DEFAULT_RCLK * 8,
131 PUC_PORT_2S, 0x18, 4, 0,
132 },
133
134 /*
135 * Boca Research Turbo Serial 658 (8 serial port) card.
136 * Appears to be the same as Chase Research PLC PCI-FAST8
137 * and Perle PCI-FAST8 Multi-Port serial cards.
138 */
139 { 0x10b5, 0x9050, 0x12e0, 0x0021,
140 "Boca Research Turbo Serial 658",
141 DEFAULT_RCLK * 4,
142 PUC_PORT_8S, 0x18, 0, 8,
143 },
144
145 { 0x10b5, 0x9050, 0x12e0, 0x0031,
146 "Boca Research Turbo Serial 654",
147 DEFAULT_RCLK * 4,
148 PUC_PORT_4S, 0x18, 0, 8,
149 },
150
151 /*
152 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
153 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
154 * into the subsystem fields, and claims that it's a
155 * network/misc (0x02/0x80) device.
156 */
157 { 0x10b5, 0x9050, 0xd84d, 0x6808,
158 "Dolphin Peripherals 4035",
159 DEFAULT_RCLK,
160 PUC_PORT_2S, 0x18, 4, 0,
161 },
162
163 /*
164 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
165 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
166 * into the subsystem fields, and claims that it's a
167 * network/misc (0x02/0x80) device.
168 */
169 { 0x10b5, 0x9050, 0xd84d, 0x6810,
170 "Dolphin Peripherals 4014",
171 0,
172 PUC_PORT_2P, 0x20, 4, 0,
173 },
174
175 { 0x10e8, 0x818e, 0xffff, 0,
176 "Applied Micro Circuits 8 Port UART",
177 DEFAULT_RCLK,
178 PUC_PORT_8S, 0x14, -1, -1,
179 .config_function = puc_config_amc
180 },
181
182 { 0x11fe, 0x8010, 0xffff, 0,
183 "Comtrol RocketPort 550/8 RJ11 part A",
184 DEFAULT_RCLK * 4,
185 PUC_PORT_4S, 0x10, 0, 8,
186 },
187
188 { 0x11fe, 0x8011, 0xffff, 0,
189 "Comtrol RocketPort 550/8 RJ11 part B",
190 DEFAULT_RCLK * 4,
191 PUC_PORT_4S, 0x10, 0, 8,
192 },
193
194 { 0x11fe, 0x8012, 0xffff, 0,
195 "Comtrol RocketPort 550/8 Octa part A",
196 DEFAULT_RCLK * 4,
197 PUC_PORT_4S, 0x10, 0, 8,
198 },
199
200 { 0x11fe, 0x8013, 0xffff, 0,
201 "Comtrol RocketPort 550/8 Octa part B",
202 DEFAULT_RCLK * 4,
203 PUC_PORT_4S, 0x10, 0, 8,
204 },
205
206 { 0x11fe, 0x8014, 0xffff, 0,
207 "Comtrol RocketPort 550/4 RJ45",
208 DEFAULT_RCLK * 4,
209 PUC_PORT_4S, 0x10, 0, 8,
210 },
211
212 { 0x11fe, 0x8015, 0xffff, 0,
213 "Comtrol RocketPort 550/Quad",
214 DEFAULT_RCLK * 4,
215 PUC_PORT_4S, 0x10, 0, 8,
216 },
217
218 { 0x11fe, 0x8016, 0xffff, 0,
219 "Comtrol RocketPort 550/16 part A",
220 DEFAULT_RCLK * 4,
221 PUC_PORT_4S, 0x10, 0, 8,
222 },
223
224 { 0x11fe, 0x8017, 0xffff, 0,
225 "Comtrol RocketPort 550/16 part B",
226 DEFAULT_RCLK * 4,
227 PUC_PORT_12S, 0x10, 0, 8,
228 },
229
230 { 0x11fe, 0x8018, 0xffff, 0,
231 "Comtrol RocketPort 550/8 part A",
232 DEFAULT_RCLK * 4,
233 PUC_PORT_4S, 0x10, 0, 8,
234 },
235
236 { 0x11fe, 0x8019, 0xffff, 0,
237 "Comtrol RocketPort 550/8 part B",
238 DEFAULT_RCLK * 4,
239 PUC_PORT_4S, 0x10, 0, 8,
240 },
241
242 /*
243 * IBM SurePOS 300 Series (481033H) serial ports
244 * Details can be found on the IBM RSS websites
245 */
246
247 { 0x1014, 0x0297, 0xffff, 0,
248 "IBM SurePOS 300 Series (481033H) serial ports",
249 DEFAULT_RCLK,
250 PUC_PORT_4S, 0x10, 4, 0
251 },
252
253 /*
254 * SIIG Boards.
255 *
256 * SIIG provides documentation for their boards at:
257 * <URL:http://www.siig.com/downloads.asp>
258 */
259
260 { 0x131f, 0x1010, 0xffff, 0,
261 "SIIG Cyber I/O PCI 16C550 (10x family)",
262 DEFAULT_RCLK,
263 PUC_PORT_1S1P, 0x18, 4, 0,
264 },
265
266 { 0x131f, 0x1011, 0xffff, 0,
267 "SIIG Cyber I/O PCI 16C650 (10x family)",
268 DEFAULT_RCLK,
269 PUC_PORT_1S1P, 0x18, 4, 0,
270 },
271
272 { 0x131f, 0x1012, 0xffff, 0,
273 "SIIG Cyber I/O PCI 16C850 (10x family)",
274 DEFAULT_RCLK,
275 PUC_PORT_1S1P, 0x18, 4, 0,
276 },
277
278 { 0x131f, 0x1021, 0xffff, 0,
279 "SIIG Cyber Parallel Dual PCI (10x family)",
280 0,
281 PUC_PORT_2P, 0x18, 8, 0,
282 },
283
284 { 0x131f, 0x1030, 0xffff, 0,
285 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
286 DEFAULT_RCLK,
287 PUC_PORT_2S, 0x18, 4, 0,
288 },
289
290 { 0x131f, 0x1031, 0xffff, 0,
291 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
292 DEFAULT_RCLK,
293 PUC_PORT_2S, 0x18, 4, 0,
294 },
295
296 { 0x131f, 0x1032, 0xffff, 0,
297 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
298 DEFAULT_RCLK,
299 PUC_PORT_2S, 0x18, 4, 0,
300 },
301
302 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
303 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
304 DEFAULT_RCLK,
305 PUC_PORT_2S1P, 0x18, 4, 0,
306 },
307
308 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
309 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
310 DEFAULT_RCLK,
311 PUC_PORT_2S1P, 0x18, 4, 0,
312 },
313
314 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
315 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
316 DEFAULT_RCLK,
317 PUC_PORT_2S1P, 0x18, 4, 0,
318 },
319
320 { 0x131f, 0x1050, 0xffff, 0,
321 "SIIG Cyber 4S PCI 16C550 (10x family)",
322 DEFAULT_RCLK,
323 PUC_PORT_4S, 0x18, 4, 0,
324 },
325
326 { 0x131f, 0x1051, 0xffff, 0,
327 "SIIG Cyber 4S PCI 16C650 (10x family)",
328 DEFAULT_RCLK,
329 PUC_PORT_4S, 0x18, 4, 0,
330 },
331
332 { 0x131f, 0x1052, 0xffff, 0,
333 "SIIG Cyber 4S PCI 16C850 (10x family)",
334 DEFAULT_RCLK,
335 PUC_PORT_4S, 0x18, 4, 0,
336 },
337
338 { 0x131f, 0x2010, 0xffff, 0,
339 "SIIG Cyber I/O PCI 16C550 (20x family)",
340 DEFAULT_RCLK,
341 PUC_PORT_1S1P, 0x10, 4, 0,
342 },
343
344 { 0x131f, 0x2011, 0xffff, 0,
345 "SIIG Cyber I/O PCI 16C650 (20x family)",
346 DEFAULT_RCLK,
347 PUC_PORT_1S1P, 0x10, 4, 0,
348 },
349
350 { 0x131f, 0x2012, 0xffff, 0,
351 "SIIG Cyber I/O PCI 16C850 (20x family)",
352 DEFAULT_RCLK,
353 PUC_PORT_1S1P, 0x10, 4, 0,
354 },
355
356 { 0x131f, 0x2021, 0xffff, 0,
357 "SIIG Cyber Parallel Dual PCI (20x family)",
358 0,
359 PUC_PORT_2P, 0x10, 8, 0,
360 },
361
362 { 0x131f, 0x2030, 0xffff, 0,
363 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
364 DEFAULT_RCLK,
365 PUC_PORT_2S, 0x10, 4, 0,
366 },
367
368 { 0x131f, 0x2031, 0xffff, 0,
369 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
370 DEFAULT_RCLK,
371 PUC_PORT_2S, 0x10, 4, 0,
372 },
373
374 { 0x131f, 0x2032, 0xffff, 0,
375 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
376 DEFAULT_RCLK,
377 PUC_PORT_2S, 0x10, 4, 0,
378 },
379
380 { 0x131f, 0x2040, 0xffff, 0,
381 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
382 DEFAULT_RCLK,
383 PUC_PORT_1S2P, 0x10, -1, 0,
384 .config_function = puc_config_siig
385 },
386
387 { 0x131f, 0x2041, 0xffff, 0,
388 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
389 DEFAULT_RCLK,
390 PUC_PORT_1S2P, 0x10, -1, 0,
391 .config_function = puc_config_siig
392 },
393
394 { 0x131f, 0x2042, 0xffff, 0,
395 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
396 DEFAULT_RCLK,
397 PUC_PORT_1S2P, 0x10, -1, 0,
398 .config_function = puc_config_siig
399 },
400
401 { 0x131f, 0x2050, 0xffff, 0,
402 "SIIG Cyber 4S PCI 16C550 (20x family)",
403 DEFAULT_RCLK,
404 PUC_PORT_4S, 0x10, 4, 0,
405 },
406
407 { 0x131f, 0x2051, 0xffff, 0,
408 "SIIG Cyber 4S PCI 16C650 (20x family)",
409 DEFAULT_RCLK,
410 PUC_PORT_4S, 0x10, 4, 0,
411 },
412
413 { 0x131f, 0x2052, 0xffff, 0,
414 "SIIG Cyber 4S PCI 16C850 (20x family)",
415 DEFAULT_RCLK,
416 PUC_PORT_4S, 0x10, 4, 0,
417 },
418
419 { 0x131f, 0x2060, 0xffff, 0,
420 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
421 DEFAULT_RCLK,
422 PUC_PORT_2S1P, 0x10, 4, 0,
423 },
424
425 { 0x131f, 0x2061, 0xffff, 0,
426 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
427 DEFAULT_RCLK,
428 PUC_PORT_2S1P, 0x10, 4, 0,
429 },
430
431 { 0x131f, 0x2062, 0xffff, 0,
432 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
433 DEFAULT_RCLK,
434 PUC_PORT_2S1P, 0x10, 4, 0,
435 },
436
437 { 0x131f, 0x2081, 0xffff, 0,
438 "SIIG PS8000 8S PCI 16C650 (20x family)",
439 DEFAULT_RCLK,
440 PUC_PORT_8S, 0x10, -1, -1,
441 .config_function = puc_config_siig
442 },
443
444 { 0x135c, 0x0010, 0xffff, 0,
445 "Quatech QSC-100",
446 -3, /* max 8x clock rate */
447 PUC_PORT_4S, 0x14, 0, 8,
448 .config_function = puc_config_quatech
449 },
450
451 { 0x135c, 0x0020, 0xffff, 0,
452 "Quatech DSC-100",
453 -1, /* max 2x clock rate */
454 PUC_PORT_2S, 0x14, 0, 8,
455 .config_function = puc_config_quatech
456 },
457
458 { 0x135c, 0x0030, 0xffff, 0,
459 "Quatech DSC-200/300",
460 -1, /* max 2x clock rate */
461 PUC_PORT_2S, 0x14, 0, 8,
462 .config_function = puc_config_quatech
463 },
464
465 { 0x135c, 0x0040, 0xffff, 0,
466 "Quatech QSC-200/300",
467 -3, /* max 8x clock rate */
468 PUC_PORT_4S, 0x14, 0, 8,
469 .config_function = puc_config_quatech
470 },
471
472 { 0x135c, 0x0050, 0xffff, 0,
473 "Quatech ESC-100D",
474 -3, /* max 8x clock rate */
475 PUC_PORT_8S, 0x14, 0, 8,
476 .config_function = puc_config_quatech
477 },
478
479 { 0x135c, 0x0060, 0xffff, 0,
480 "Quatech ESC-100M",
481 -3, /* max 8x clock rate */
482 PUC_PORT_8S, 0x14, 0, 8,
483 .config_function = puc_config_quatech
484 },
485
486 { 0x135c, 0x0170, 0xffff, 0,
487 "Quatech QSCLP-100",
488 -1, /* max 2x clock rate */
489 PUC_PORT_4S, 0x18, 0, 8,
490 .config_function = puc_config_quatech
491 },
492
493 { 0x135c, 0x0180, 0xffff, 0,
494 "Quatech DSCLP-100",
495 -1, /* max 3x clock rate */
496 PUC_PORT_2S, 0x18, 0, 8,
497 .config_function = puc_config_quatech
498 },
499
500 { 0x135c, 0x01b0, 0xffff, 0,
501 "Quatech DSCLP-200/300",
502 -1, /* max 2x clock rate */
503 PUC_PORT_2S, 0x18, 0, 8,
504 .config_function = puc_config_quatech
505 },
506
507 { 0x135c, 0x01e0, 0xffff, 0,
508 "Quatech ESCLP-100",
509 -3, /* max 8x clock rate */
510 PUC_PORT_8S, 0x10, 0, 8,
511 .config_function = puc_config_quatech
512 },
513
514 { 0x1393, 0x1024, 0xffff, 0,
515 "Moxa Technologies, Smartio CP-102E/PCIe",
516 DEFAULT_RCLK * 8,
517 PUC_PORT_2S, 0x14, 0, -1,
518 .config_function = puc_config_moxa
519 },
520
521 { 0x1393, 0x1025, 0xffff, 0,
522 "Moxa Technologies, Smartio CP-102EL/PCIe",
523 DEFAULT_RCLK * 8,
524 PUC_PORT_2S, 0x14, 0, -1,
525 .config_function = puc_config_moxa
526 },
527
528 { 0x1393, 0x1040, 0xffff, 0,
529 "Moxa Technologies, Smartio C104H/PCI",
530 DEFAULT_RCLK * 8,
531 PUC_PORT_4S, 0x18, 0, 8,
532 },
533
534 { 0x1393, 0x1041, 0xffff, 0,
535 "Moxa Technologies, Smartio CP-104UL/PCI",
536 DEFAULT_RCLK * 8,
537 PUC_PORT_4S, 0x18, 0, 8,
538 },
539
540 { 0x1393, 0x1042, 0xffff, 0,
541 "Moxa Technologies, Smartio CP-104JU/PCI",
542 DEFAULT_RCLK * 8,
543 PUC_PORT_4S, 0x18, 0, 8,
544 },
545
546 { 0x1393, 0x1043, 0xffff, 0,
547 "Moxa Technologies, Smartio CP-104EL/PCIe",
548 DEFAULT_RCLK * 8,
549 PUC_PORT_4S, 0x18, 0, 8,
550 },
551
552 { 0x1393, 0x1045, 0xffff, 0,
553 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
554 DEFAULT_RCLK * 8,
555 PUC_PORT_4S, 0x14, 0, -1,
556 .config_function = puc_config_moxa
557 },
558
559 { 0x1393, 0x1120, 0xffff, 0,
560 "Moxa Technologies, CP-112UL",
561 DEFAULT_RCLK * 8,
562 PUC_PORT_2S, 0x18, 0, 8,
563 },
564
565 { 0x1393, 0x1141, 0xffff, 0,
566 "Moxa Technologies, Industio CP-114",
567 DEFAULT_RCLK * 8,
568 PUC_PORT_4S, 0x18, 0, 8,
569 },
570
571 { 0x1393, 0x1144, 0xffff, 0,
572 "Moxa Technologies, Smartio CP-114EL/PCIe",
573 DEFAULT_RCLK * 8,
574 PUC_PORT_4S, 0x14, 0, -1,
575 .config_function = puc_config_moxa
576 },
577
578 { 0x1393, 0x1182, 0xffff, 0,
579 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
580 DEFAULT_RCLK * 8,
581 PUC_PORT_8S, 0x14, 0, -1,
582 .config_function = puc_config_moxa
583 },
584
585 { 0x1393, 0x1680, 0xffff, 0,
586 "Moxa Technologies, C168H/PCI",
587 DEFAULT_RCLK * 8,
588 PUC_PORT_8S, 0x18, 0, 8,
589 },
590
591 { 0x1393, 0x1681, 0xffff, 0,
592 "Moxa Technologies, C168U/PCI",
593 DEFAULT_RCLK * 8,
594 PUC_PORT_8S, 0x18, 0, 8,
595 },
596
597 { 0x1393, 0x1682, 0xffff, 0,
598 "Moxa Technologies, CP-168EL/PCIe",
599 DEFAULT_RCLK * 8,
600 PUC_PORT_8S, 0x18, 0, 8,
601 },
602
603 { 0x1393, 0x1683, 0xffff, 0,
604 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
605 DEFAULT_RCLK * 8,
606 PUC_PORT_8S, 0x14, 0, -1,
607 .config_function = puc_config_moxa
608 },
609
610 { 0x13a8, 0x0152, 0xffff, 0,
611 "Exar XR17C/D152",
612 DEFAULT_RCLK * 8,
613 PUC_PORT_2S, 0x10, 0, -1,
614 .config_function = puc_config_exar
615 },
616
617 { 0x13a8, 0x0154, 0xffff, 0,
618 "Exar XR17C154",
619 DEFAULT_RCLK * 8,
620 PUC_PORT_4S, 0x10, 0, -1,
621 .config_function = puc_config_exar
622 },
623
624 { 0x13a8, 0x0158, 0xffff, 0,
625 "Exar XR17C158",
626 DEFAULT_RCLK * 8,
627 PUC_PORT_8S, 0x10, 0, -1,
628 .config_function = puc_config_exar
629 },
630
631 { 0x13a8, 0x0258, 0xffff, 0,
632 "Exar XR17V258IV",
633 DEFAULT_RCLK * 8,
634 PUC_PORT_8S, 0x10, 0, -1,
635 .config_function = puc_config_exar
636 },
637
638 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
639 { 0x13a8, 0x0358, 0xffff, 0,
640 "Exar XR17V358",
641 125000000,
642 PUC_PORT_8S, 0x10, 0, -1,
643 .config_function = puc_config_exar_pcie
644 },
645
646 { 0x13fe, 0x1600, 0x1602, 0x0002,
647 "Advantech PCI-1602",
648 DEFAULT_RCLK * 8,
649 PUC_PORT_2S, 0x10, 0, 8,
650 },
651
652 { 0x1407, 0x0100, 0xffff, 0,
653 "Lava Computers Dual Serial",
654 DEFAULT_RCLK,
655 PUC_PORT_2S, 0x10, 4, 0,
656 },
657
658 { 0x1407, 0x0101, 0xffff, 0,
659 "Lava Computers Quatro A",
660 DEFAULT_RCLK,
661 PUC_PORT_2S, 0x10, 4, 0,
662 },
663
664 { 0x1407, 0x0102, 0xffff, 0,
665 "Lava Computers Quatro B",
666 DEFAULT_RCLK,
667 PUC_PORT_2S, 0x10, 4, 0,
668 },
669
670 { 0x1407, 0x0120, 0xffff, 0,
671 "Lava Computers Quattro-PCI A",
672 DEFAULT_RCLK,
673 PUC_PORT_2S, 0x10, 4, 0,
674 },
675
676 { 0x1407, 0x0121, 0xffff, 0,
677 "Lava Computers Quattro-PCI B",
678 DEFAULT_RCLK,
679 PUC_PORT_2S, 0x10, 4, 0,
680 },
681
682 { 0x1407, 0x0180, 0xffff, 0,
683 "Lava Computers Octo A",
684 DEFAULT_RCLK,
685 PUC_PORT_4S, 0x10, 4, 0,
686 },
687
688 { 0x1407, 0x0181, 0xffff, 0,
689 "Lava Computers Octo B",
690 DEFAULT_RCLK,
691 PUC_PORT_4S, 0x10, 4, 0,
692 },
693
694 { 0x1409, 0x7268, 0xffff, 0,
695 "Sunix SUN1888",
696 0,
697 PUC_PORT_2P, 0x10, 0, 8,
698 },
699
700 { 0x1409, 0x7168, 0xffff, 0,
701 NULL,
702 DEFAULT_RCLK * 8,
703 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
704 .config_function = puc_config_timedia
705 },
706
707 /*
708 * Boards with an Oxford Semiconductor chip.
709 *
710 * Oxford Semiconductor provides documentation for their chip at:
711 * <URL:http://www.plxtech.com/products/uart/>
712 *
713 * As sold by Kouwell <URL:http://www.kouwell.com/>.
714 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
715 */
716 {
717 0x1415, 0x9501, 0x10fc, 0xc070,
718 "I-O DATA RSA-PCI2/R",
719 DEFAULT_RCLK * 8,
720 PUC_PORT_2S, 0x10, 0, 8,
721 },
722
723 { 0x1415, 0x9501, 0x131f, 0x2050,
724 "SIIG Cyber 4 PCI 16550",
725 DEFAULT_RCLK * 10,
726 PUC_PORT_4S, 0x10, 0, 8,
727 },
728
729 { 0x1415, 0x9501, 0x131f, 0x2051,
730 "SIIG Cyber 4S PCI 16C650 (20x family)",
731 DEFAULT_RCLK * 10,
732 PUC_PORT_4S, 0x10, 0, 8,
733 },
734
735 { 0x1415, 0x9501, 0x131f, 0x2052,
736 "SIIG Quartet Serial 850",
737 DEFAULT_RCLK * 10,
738 PUC_PORT_4S, 0x10, 0, 8,
739 },
740
741 { 0x1415, 0x9501, 0x14db, 0x2150,
742 "Kuroutoshikou SERIAL4P-LPPCI2",
743 DEFAULT_RCLK * 10,
744 PUC_PORT_4S, 0x10, 0, 8,
745 },
746
747 { 0x1415, 0x9501, 0xffff, 0,
748 "Oxford Semiconductor OX16PCI954 UARTs",
749 0,
750 PUC_PORT_4S, 0x10, 0, 8,
751 .config_function = puc_config_oxford_pci954
752 },
753
754 { 0x1415, 0x950a, 0x131f, 0x2030,
755 "SIIG Cyber 2S PCIe",
756 DEFAULT_RCLK * 10,
757 PUC_PORT_2S, 0x10, 0, 8,
758 },
759
760 { 0x1415, 0x950a, 0x131f, 0x2032,
761 "SIIG Cyber Serial Dual PCI 16C850",
762 DEFAULT_RCLK * 10,
763 PUC_PORT_4S, 0x10, 0, 8,
764 },
765
766 { 0x1415, 0x950a, 0xffff, 0,
767 "Oxford Semiconductor OX16PCI954 UARTs",
768 DEFAULT_RCLK,
769 PUC_PORT_4S, 0x10, 0, 8,
770 },
771
772 { 0x1415, 0x9511, 0xffff, 0,
773 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
774 DEFAULT_RCLK,
775 PUC_PORT_4S, 0x10, 0, 8,
776 },
777
778 { 0x1415, 0x9521, 0xffff, 0,
779 "Oxford Semiconductor OX16PCI952 UARTs",
780 DEFAULT_RCLK,
781 PUC_PORT_2S, 0x10, 4, 0,
782 },
783
784 { 0x1415, 0x9538, 0xffff, 0,
785 "Oxford Semiconductor OX16PCI958 UARTs",
786 DEFAULT_RCLK,
787 PUC_PORT_8S, 0x18, 0, 8,
788 },
789
790 /*
791 * Perle boards use Oxford Semiconductor chips, but they store the
792 * Oxford Semiconductor device ID as a subvendor device ID and use
793 * their own device IDs.
794 */
795
796 { 0x155f, 0x0331, 0xffff, 0,
797 "Perle Ultraport4 Express",
798 DEFAULT_RCLK * 8,
799 PUC_PORT_4S, 0x10, 0, 8,
800 },
801
802 { 0x155f, 0xB012, 0xffff, 0,
803 "Perle Speed2 LE",
804 DEFAULT_RCLK * 8,
805 PUC_PORT_2S, 0x10, 0, 8,
806 },
807
808 { 0x155f, 0xB022, 0xffff, 0,
809 "Perle Speed2 LE",
810 DEFAULT_RCLK * 8,
811 PUC_PORT_2S, 0x10, 0, 8,
812 },
813
814 { 0x155f, 0xB004, 0xffff, 0,
815 "Perle Speed4 LE",
816 DEFAULT_RCLK * 8,
817 PUC_PORT_4S, 0x10, 0, 8,
818 },
819
820 { 0x155f, 0xB008, 0xffff, 0,
821 "Perle Speed8 LE",
822 DEFAULT_RCLK * 8,
823 PUC_PORT_8S, 0x10, 0, 8,
824 },
825
826
827 /*
828 * Oxford Semiconductor PCI Express Expresso family
829 *
830 * Found in many 'native' PCI Express serial boards such as:
831 *
832 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
833 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
834 *
835 * Lindy 51189 (4 port)
836 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
837 *
838 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
839 * <URL:http://www.startech.com>
840 */
841
842 { 0x1415, 0xc11b, 0xffff, 0,
843 "Oxford Semiconductor OXPCIe952 1S1P",
844 DEFAULT_RCLK * 0x22,
845 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
846 .config_function = puc_config_oxford_pcie
847 },
848
849 { 0x1415, 0xc138, 0xffff, 0,
850 "Oxford Semiconductor OXPCIe952 UARTs",
851 DEFAULT_RCLK * 0x22,
852 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
853 .config_function = puc_config_oxford_pcie
854 },
855
856 { 0x1415, 0xc158, 0xffff, 0,
857 "Oxford Semiconductor OXPCIe952 UARTs",
858 DEFAULT_RCLK * 0x22,
859 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
860 .config_function = puc_config_oxford_pcie
861 },
862
863 { 0x1415, 0xc15d, 0xffff, 0,
864 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
865 DEFAULT_RCLK * 0x22,
866 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
867 .config_function = puc_config_oxford_pcie
868 },
869
870 { 0x1415, 0xc208, 0xffff, 0,
871 "Oxford Semiconductor OXPCIe954 UARTs",
872 DEFAULT_RCLK * 0x22,
873 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
874 .config_function = puc_config_oxford_pcie
875 },
876
877 { 0x1415, 0xc20d, 0xffff, 0,
878 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
879 DEFAULT_RCLK * 0x22,
880 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
881 .config_function = puc_config_oxford_pcie
882 },
883
884 { 0x1415, 0xc308, 0xffff, 0,
885 "Oxford Semiconductor OXPCIe958 UARTs",
886 DEFAULT_RCLK * 0x22,
887 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
888 .config_function = puc_config_oxford_pcie
889 },
890
891 { 0x1415, 0xc30d, 0xffff, 0,
892 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
893 DEFAULT_RCLK * 0x22,
894 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
895 .config_function = puc_config_oxford_pcie
896 },
897
898 { 0x14d2, 0x8010, 0xffff, 0,
899 "VScom PCI-100L",
900 DEFAULT_RCLK * 8,
901 PUC_PORT_1S, 0x14, 0, 0,
902 },
903
904 { 0x14d2, 0x8020, 0xffff, 0,
905 "VScom PCI-200L",
906 DEFAULT_RCLK * 8,
907 PUC_PORT_2S, 0x14, 4, 0,
908 },
909
910 { 0x14d2, 0x8028, 0xffff, 0,
911 "VScom 200Li",
912 DEFAULT_RCLK,
913 PUC_PORT_2S, 0x20, 0, 8,
914 },
915
916 /*
917 * VScom (Titan?) PCI-800L. More modern variant of the
918 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
919 * two of them obviously implemented as macro cells in
920 * the ASIC. This causes the weird port access pattern
921 * below, where two of the IO port ranges each access
922 * one of the ASIC UARTs, and a block of IO addresses
923 * access the external UARTs.
924 */
925 { 0x14d2, 0x8080, 0xffff, 0,
926 "Titan VScom PCI-800L",
927 DEFAULT_RCLK * 8,
928 PUC_PORT_8S, 0x14, -1, -1,
929 .config_function = puc_config_titan
930 },
931
932 /*
933 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
934 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
935 * device ID 3 and PCI device 1 device ID 4.
936 */
937 { 0x14d2, 0xa003, 0xffff, 0,
938 "Titan PCI-800H",
939 DEFAULT_RCLK * 8,
940 PUC_PORT_4S, 0x10, 0, 8,
941 },
942
943 { 0x14d2, 0xa004, 0xffff, 0,
944 "Titan PCI-800H",
945 DEFAULT_RCLK * 8,
946 PUC_PORT_4S, 0x10, 0, 8,
947 },
948
949 { 0x14d2, 0xa005, 0xffff, 0,
950 "Titan PCI-200H",
951 DEFAULT_RCLK * 8,
952 PUC_PORT_2S, 0x10, 0, 8,
953 },
954
955 { 0x14d2, 0xe020, 0xffff, 0,
956 "Titan VScom PCI-200HV2",
957 DEFAULT_RCLK * 8,
958 PUC_PORT_2S, 0x10, 4, 0,
959 },
960
961 { 0x14d2, 0xa007, 0xffff, 0,
962 "Titan VScom PCIex-800H",
963 DEFAULT_RCLK * 8,
964 PUC_PORT_4S, 0x10, 0, 8,
965 },
966
967 { 0x14d2, 0xa008, 0xffff, 0,
968 "Titan VScom PCIex-800H",
969 DEFAULT_RCLK * 8,
970 PUC_PORT_4S, 0x10, 0, 8,
971 },
972
973 { 0x14db, 0x2130, 0xffff, 0,
974 "Avlab Technology, PCI IO 2S",
975 DEFAULT_RCLK,
976 PUC_PORT_2S, 0x10, 4, 0,
977 },
978
979 { 0x14db, 0x2150, 0xffff, 0,
980 "Avlab Low Profile PCI 4 Serial",
981 DEFAULT_RCLK,
982 PUC_PORT_4S, 0x10, 4, 0,
983 },
984
985 { 0x14db, 0x2152, 0xffff, 0,
986 "Avlab Low Profile PCI 4 Serial",
987 DEFAULT_RCLK,
988 PUC_PORT_4S, 0x10, 4, 0,
989 },
990
991 { 0x1592, 0x0781, 0xffff, 0,
992 "Syba Tech Ltd. PCI-4S2P-550-ECP",
993 DEFAULT_RCLK,
994 PUC_PORT_4S1P, 0x10, 0, -1,
995 .config_function = puc_config_syba
996 },
997
998 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
999 "Sunix SER5xxxx 2-port serial",
1000 DEFAULT_RCLK * 8,
1001 PUC_PORT_2S, 0x10, 0, 8,
1002 },
1003
1004 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1005 "Sunix SER5xxxx 4-port serial",
1006 DEFAULT_RCLK * 8,
1007 PUC_PORT_4S, 0x10, 0, 8,
1008 },
1009
1010 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1011 "Sunix SER5xxxx 8-port serial",
1012 DEFAULT_RCLK * 8,
1013 PUC_PORT_8S, -1, -1, -1,
1014 .config_function = puc_config_sunix
1015 },
1016
1017 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1018 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1019 DEFAULT_RCLK * 8,
1020 PUC_PORT_1S1P, -1, -1, -1,
1021 .config_function = puc_config_sunix
1022 },
1023
1024 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1025 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1026 DEFAULT_RCLK * 8,
1027 PUC_PORT_2S1P, -1, -1, -1,
1028 .config_function = puc_config_sunix
1029 },
1030
1031 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1032 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1033 DEFAULT_RCLK * 8,
1034 PUC_PORT_4S1P, -1, -1, -1,
1035 .config_function = puc_config_sunix
1036 },
1037
1038 { 0x5372, 0x6872, 0xffff, 0,
1039 "Feasso PCI FPP-02 2S1P",
1040 DEFAULT_RCLK,
1041 PUC_PORT_2S1P, 0x10, 4, 0,
1042 },
1043
1044 { 0x5372, 0x6873, 0xffff, 0,
1045 "Sun 1040 PCI Quad Serial",
1046 DEFAULT_RCLK,
1047 PUC_PORT_4S, 0x10, 4, 0,
1048 },
1049
1050 { 0x6666, 0x0001, 0xffff, 0,
1051 "Decision Computer Inc, PCCOM 4-port serial",
1052 DEFAULT_RCLK,
1053 PUC_PORT_4S, 0x1c, 0, 8,
1054 },
1055
1056 { 0x6666, 0x0002, 0xffff, 0,
1057 "Decision Computer Inc, PCCOM 8-port serial",
1058 DEFAULT_RCLK,
1059 PUC_PORT_8S, 0x1c, 0, 8,
1060 },
1061
1062 { 0x6666, 0x0004, 0xffff, 0,
1063 "PCCOM dual port RS232/422/485",
1064 DEFAULT_RCLK,
1065 PUC_PORT_2S, 0x1c, 0, 8,
1066 },
1067
1068 { 0x9710, 0x9815, 0xffff, 0,
1069 "NetMos NM9815 Dual 1284 Printer port",
1070 0,
1071 PUC_PORT_2P, 0x10, 8, 0,
1072 },
1073
1074 /*
1075 * This is more specific than the generic NM9835 entry, and is placed
1076 * here to _prevent_ puc(4) from claiming this single port card.
1077 *
1078 * uart(4) will claim this device.
1079 */
1080 { 0x9710, 0x9835, 0x1000, 1,
1081 "NetMos NM9835 based 1-port serial",
1082 DEFAULT_RCLK,
1083 PUC_PORT_1S, 0x10, 4, 0,
1084 },
1085
1086 { 0x9710, 0x9835, 0x1000, 2,
1087 "NetMos NM9835 based 2-port serial",
1088 DEFAULT_RCLK,
1089 PUC_PORT_2S, 0x10, 4, 0,
1090 },
1091
1092 { 0x9710, 0x9835, 0xffff, 0,
1093 "NetMos NM9835 Dual UART and 1284 Printer port",
1094 DEFAULT_RCLK,
1095 PUC_PORT_2S1P, 0x10, 4, 0,
1096 },
1097
1098 { 0x9710, 0x9845, 0x1000, 0x0006,
1099 "NetMos NM9845 6 Port UART",
1100 DEFAULT_RCLK,
1101 PUC_PORT_6S, 0x10, 4, 0,
1102 },
1103
1104 { 0x9710, 0x9845, 0xffff, 0,
1105 "NetMos NM9845 Quad UART and 1284 Printer port",
1106 DEFAULT_RCLK,
1107 PUC_PORT_4S1P, 0x10, 4, 0,
1108 },
1109
1110 { 0x9710, 0x9865, 0xa000, 0x3002,
1111 "NetMos NM9865 Dual UART",
1112 DEFAULT_RCLK,
1113 PUC_PORT_2S, 0x10, 4, 0,
1114 },
1115
1116 { 0x9710, 0x9865, 0xa000, 0x3003,
1117 "NetMos NM9865 Triple UART",
1118 DEFAULT_RCLK,
1119 PUC_PORT_3S, 0x10, 4, 0,
1120 },
1121
1122 { 0x9710, 0x9865, 0xa000, 0x3004,
1123 "NetMos NM9865 Quad UART",
1124 DEFAULT_RCLK,
1125 PUC_PORT_4S, 0x10, 4, 0,
1126 },
1127
1128 { 0x9710, 0x9865, 0xa000, 0x3011,
1129 "NetMos NM9865 Single UART and 1284 Printer port",
1130 DEFAULT_RCLK,
1131 PUC_PORT_1S1P, 0x10, 4, 0,
1132 },
1133
1134 { 0x9710, 0x9865, 0xa000, 0x3012,
1135 "NetMos NM9865 Dual UART and 1284 Printer port",
1136 DEFAULT_RCLK,
1137 PUC_PORT_2S1P, 0x10, 4, 0,
1138 },
1139
1140 { 0x9710, 0x9865, 0xa000, 0x3020,
1141 "NetMos NM9865 Dual 1284 Printer port",
1142 DEFAULT_RCLK,
1143 PUC_PORT_2P, 0x10, 4, 0,
1144 },
1145
1146 { 0xb00c, 0x021c, 0xffff, 0,
1147 "IC Book Labs Gunboat x4 Lite",
1148 DEFAULT_RCLK,
1149 PUC_PORT_4S, 0x10, 0, 8,
1150 .config_function = puc_config_icbook
1151 },
1152
1153 { 0xb00c, 0x031c, 0xffff, 0,
1154 "IC Book Labs Gunboat x4 Pro",
1155 DEFAULT_RCLK,
1156 PUC_PORT_4S, 0x10, 0, 8,
1157 .config_function = puc_config_icbook
1158 },
1159
1160 { 0xb00c, 0x041c, 0xffff, 0,
1161 "IC Book Labs Ironclad x8 Lite",
1162 DEFAULT_RCLK,
1163 PUC_PORT_8S, 0x10, 0, 8,
1164 .config_function = puc_config_icbook
1165 },
1166
1167 { 0xb00c, 0x051c, 0xffff, 0,
1168 "IC Book Labs Ironclad x8 Pro",
1169 DEFAULT_RCLK,
1170 PUC_PORT_8S, 0x10, 0, 8,
1171 .config_function = puc_config_icbook
1172 },
1173
1174 { 0xb00c, 0x081c, 0xffff, 0,
1175 "IC Book Labs Dreadnought x16 Pro",
1176 DEFAULT_RCLK * 8,
1177 PUC_PORT_16S, 0x10, 0, 8,
1178 .config_function = puc_config_icbook
1179 },
1180
1181 { 0xb00c, 0x091c, 0xffff, 0,
1182 "IC Book Labs Dreadnought x16 Lite",
1183 DEFAULT_RCLK,
1184 PUC_PORT_16S, 0x10, 0, 8,
1185 .config_function = puc_config_icbook
1186 },
1187
1188 { 0xb00c, 0x0a1c, 0xffff, 0,
1189 "IC Book Labs Gunboat x2 Low Profile",
1190 DEFAULT_RCLK,
1191 PUC_PORT_2S, 0x10, 0, 8,
1192 },
1193
1194 { 0xb00c, 0x0b1c, 0xffff, 0,
1195 "IC Book Labs Gunboat x4 Low Profile",
1196 DEFAULT_RCLK,
1197 PUC_PORT_4S, 0x10, 0, 8,
1198 .config_function = puc_config_icbook
1199 },
1200
1201 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1202};
1203
1204static int
1205puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1206 intptr_t *res)
1207{
1208 switch (cmd) {
1209 case PUC_CFG_GET_OFS:
1210 *res = 8 * (port & 1);
1211 return (0);
1212 case PUC_CFG_GET_RID:
1213 *res = 0x14 + (port >> 1) * 4;
1214 return (0);
1215 default:
1216 break;
1217 }
1218 return (ENXIO);
1219}
1220
1221static int
1222puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1223 intptr_t *res)
1224{
1225 const struct puc_cfg *cfg = sc->sc_cfg;
1226
1227 if (cmd == PUC_CFG_GET_OFS) {
1228 if (cfg->subdevice == 0x1282) /* Everest SP */
1229 port <<= 1;
1230 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1231 port = (port == 3) ? 4 : port;
1232 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1233 return (0);
1234 }
1235 return (ENXIO);
1236}
1237
1238static int
1239puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1240 intptr_t *res)
1241{
1242 if (cmd == PUC_CFG_GET_OFS) {
1243 *res = port * 0x200;
1244 return (0);
1245 }
1246 return (ENXIO);
1247}
1248
1249static int
1250puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1251 intptr_t *res)
1252{
1253 if (cmd == PUC_CFG_GET_OFS) {
1254 *res = port * 0x400;
1255 return (0);
1256 }
1257 return (ENXIO);
1258}
1259
1260static int
1261puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1262 intptr_t *res)
1263{
1264 if (cmd == PUC_CFG_GET_ILR) {
1265 *res = PUC_ILR_DIGI;
1266 return (0);
1267 }
1268 return (ENXIO);
1269}
1270
1271static int
1272puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1273 intptr_t *res)
1274{
1275 if (cmd == PUC_CFG_GET_OFS) {
1276 const struct puc_cfg *cfg = sc->sc_cfg;
1277
1278 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
1279 port = 7;
1280 *res = port * 0x200;
1281
1282 return 0;
1283 }
1284 return (ENXIO);
1285}
1286
1287static int
1288puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1289 intptr_t *res)
1290{
1291 const struct puc_cfg *cfg = sc->sc_cfg;
1292 struct puc_bar *bar;
1293 uint8_t v0, v1;
1294
1295 switch (cmd) {
1296 case PUC_CFG_SETUP:
1297 /*
1298 * Check if the scratchpad register is enabled or if the
1299 * interrupt status and options registers are active.
1300 */
1301 bar = puc_get_bar(sc, cfg->rid);
1302 if (bar == NULL)
1303 return (ENXIO);
1304 /* Set DLAB in the LCR register of UART 0. */
1305 bus_write_1(bar->b_res, 3, 0x80);
1306 /* Write 0 to the SPR register of UART 0. */
1307 bus_write_1(bar->b_res, 7, 0);
1308 /* Read back the contents of the SPR register of UART 0. */
1309 v0 = bus_read_1(bar->b_res, 7);
1310 /* Write a specific value to the SPR register of UART 0. */
1311 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1312 /* Read back the contents of the SPR register of UART 0. */
1313 v1 = bus_read_1(bar->b_res, 7);
1314 /* Clear DLAB in the LCR register of UART 0. */
1315 bus_write_1(bar->b_res, 3, 0);
1316 /* Save the two values read-back from the SPR register. */
1317 sc->sc_cfg_data = (v0 << 8) | v1;
1318 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1319 /*
1320 * The SPR register echoed the two values written
1321 * by us. This means that the SPAD jumper is set.
1322 */
1323 device_printf(sc->sc_dev, "warning: extra features "
1324 "not usable -- SPAD compatibility enabled\n");
1325 return (0);
1326 }
1327 if (v0 != 0) {
1328 /*
1329 * The first value doesn't match. This can only mean
1330 * that the SPAD jumper is not set and that a non-
1331 * standard fixed clock multiplier jumper is set.
1332 */
1333 if (bootverbose)
1334 device_printf(sc->sc_dev, "fixed clock rate "
1335 "multiplier of %d\n", 1 << v0);
1336 if (v0 < -cfg->clock)
1337 device_printf(sc->sc_dev, "warning: "
1338 "suboptimal fixed clock rate multiplier "
1339 "setting\n");
1340 return (0);
1341 }
1342 /*
1343 * The first value matched, but the second didn't. We know
1344 * that the SPAD jumper is not set. We also know that the
1345 * clock rate multiplier is software controlled *and* that
1346 * we just programmed it to the maximum allowed.
1347 */
1348 if (bootverbose)
1349 device_printf(sc->sc_dev, "clock rate multiplier of "
1350 "%d selected\n", 1 << -cfg->clock);
1351 return (0);
1352 case PUC_CFG_GET_CLOCK:
1353 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1354 v1 = sc->sc_cfg_data & 0xff;
1355 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1356 /*
1357 * XXX With the SPAD jumper applied, there's no
1358 * easy way of knowing if there's also a clock
1359 * rate multiplier jumper installed. Let's hope
1360 * not...
1361 */
1362 *res = DEFAULT_RCLK;
1363 } else if (v0 == 0) {
1364 /*
1365 * No clock rate multiplier jumper installed,
1366 * so we programmed the board with the maximum
1367 * multiplier allowed as given to us in the
1368 * clock field of the config record (negated).
1369 */
1370 *res = DEFAULT_RCLK << -cfg->clock;
1371 } else
1372 *res = DEFAULT_RCLK << v0;
1373 return (0);
1374 case PUC_CFG_GET_ILR:
1375 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1376 v1 = sc->sc_cfg_data & 0xff;
1377 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1378 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1379 return (0);
1380 default:
1381 break;
1382 }
1383 return (ENXIO);
1384}
1385
1386static int
1387puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1388 intptr_t *res)
1389{
1390 static int base[] = { 0x251, 0x3f0, 0 };
1391 const struct puc_cfg *cfg = sc->sc_cfg;
1392 struct puc_bar *bar;
1393 int efir, idx, ofs;
1394 uint8_t v;
1395
1396 switch (cmd) {
1397 case PUC_CFG_SETUP:
1398 bar = puc_get_bar(sc, cfg->rid);
1399 if (bar == NULL)
1400 return (ENXIO);
1401
1402 /* configure both W83877TFs */
1403 bus_write_1(bar->b_res, 0x250, 0x89);
1404 bus_write_1(bar->b_res, 0x3f0, 0x87);
1405 bus_write_1(bar->b_res, 0x3f0, 0x87);
1406 idx = 0;
1407 while (base[idx] != 0) {
1408 efir = base[idx];
1409 bus_write_1(bar->b_res, efir, 0x09);
1410 v = bus_read_1(bar->b_res, efir + 1);
1411 if ((v & 0x0f) != 0x0c)
1412 return (ENXIO);
1413 bus_write_1(bar->b_res, efir, 0x16);
1414 v = bus_read_1(bar->b_res, efir + 1);
1415 bus_write_1(bar->b_res, efir, 0x16);
1416 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1417 bus_write_1(bar->b_res, efir, 0x16);
1418 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1419 ofs = base[idx] & 0x300;
1420 bus_write_1(bar->b_res, efir, 0x23);
1421 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1422 bus_write_1(bar->b_res, efir, 0x24);
1423 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1424 bus_write_1(bar->b_res, efir, 0x25);
1425 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1426 bus_write_1(bar->b_res, efir, 0x17);
1427 bus_write_1(bar->b_res, efir + 1, 0x03);
1428 bus_write_1(bar->b_res, efir, 0x28);
1429 bus_write_1(bar->b_res, efir + 1, 0x43);
1430 idx++;
1431 }
1432 bus_write_1(bar->b_res, 0x250, 0xaa);
1433 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1434 return (0);
1435 case PUC_CFG_GET_OFS:
1436 switch (port) {
1437 case 0:
1438 *res = 0x2f8;
1439 return (0);
1440 case 1:
1441 *res = 0x2e8;
1442 return (0);
1443 case 2:
1444 *res = 0x3f8;
1445 return (0);
1446 case 3:
1447 *res = 0x3e8;
1448 return (0);
1449 case 4:
1450 *res = 0x278;
1451 return (0);
1452 }
1453 break;
1454 default:
1455 break;
1456 }
1457 return (ENXIO);
1458}
1459
1460static int
1461puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1462 intptr_t *res)
1463{
1464 const struct puc_cfg *cfg = sc->sc_cfg;
1465
1466 switch (cmd) {
1467 case PUC_CFG_GET_OFS:
1468 if (cfg->ports == PUC_PORT_8S) {
1469 *res = (port > 4) ? 8 * (port - 4) : 0;
1470 return (0);
1471 }
1472 break;
1473 case PUC_CFG_GET_RID:
1474 if (cfg->ports == PUC_PORT_8S) {
1475 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1476 return (0);
1477 }
1478 if (cfg->ports == PUC_PORT_2S1P) {
1479 switch (port) {
1480 case 0: *res = 0x10; return (0);
1481 case 1: *res = 0x14; return (0);
1482 case 2: *res = 0x1c; return (0);
1483 }
1484 }
1485 break;
1486 default:
1487 break;
1488 }
1489 return (ENXIO);
1490}
1491
1492static int
1493puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1494 intptr_t *res)
1495{
1496 static const uint16_t dual[] = {
1497 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1498 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1499 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1500 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1501 0xD079, 0
1502 };
1503 static const uint16_t quad[] = {
1504 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1505 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1506 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1507 0xB157, 0
1508 };
1509 static const uint16_t octa[] = {
1510 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1511 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1512 };
1513 static const struct {
1514 int ports;
1515 const uint16_t *ids;
1516 } subdevs[] = {
1517 { 2, dual },
1518 { 4, quad },
1519 { 8, octa },
1520 { 0, NULL }
1521 };
1522 static char desc[64];
1523 int dev, id;
1524 uint16_t subdev;
1525
1526 switch (cmd) {
1527 case PUC_CFG_GET_CLOCK:
1528 if (port < 2)
1529 *res = DEFAULT_RCLK * 8;
1530 else
1531 *res = DEFAULT_RCLK;
1532 return (0);
1533 case PUC_CFG_GET_DESC:
1534 snprintf(desc, sizeof(desc),
1535 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1536 *res = (intptr_t)desc;
1537 return (0);
1538 case PUC_CFG_GET_NPORTS:
1539 subdev = pci_get_subdevice(sc->sc_dev);
1540 dev = 0;
1541 while (subdevs[dev].ports != 0) {
1542 id = 0;
1543 while (subdevs[dev].ids[id] != 0) {
1544 if (subdev == subdevs[dev].ids[id]) {
1545 sc->sc_cfg_data = subdevs[dev].ports;
1546 *res = sc->sc_cfg_data;
1547 return (0);
1548 }
1549 id++;
1550 }
1551 dev++;
1552 }
1553 return (ENXIO);
1554 case PUC_CFG_GET_OFS:
1555 *res = (port == 1 || port == 3) ? 8 : 0;
1556 return (0);
1557 case PUC_CFG_GET_RID:
1558 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1559 return (0);
1560 case PUC_CFG_GET_TYPE:
1561 *res = PUC_TYPE_SERIAL;
1562 return (0);
1563 default:
1564 break;
1565 }
1566 return (ENXIO);
1567}
1568
1569static int
1570puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1571 int port __unused, intptr_t *res)
1572{
1573
1574 switch (cmd) {
1575 case PUC_CFG_GET_CLOCK:
1576 /*
1577 * OXu16PCI954 use a 14.7456 MHz clock by default while
1578 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1579 */
1580 if (pci_get_revid(sc->sc_dev) == 1)
1581 *res = DEFAULT_RCLK * 8;
1582 else
1583 *res = DEFAULT_RCLK;
1584 return (0);
1585 default:
1586 break;
1587 }
1588 return (ENXIO);
1589}
1590
1591static int
1592puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1593 intptr_t *res)
1594{
1595 const struct puc_cfg *cfg = sc->sc_cfg;
1596 int idx;
1597 struct puc_bar *bar;
1598 uint8_t value;
1599
1600 switch (cmd) {
1601 case PUC_CFG_SETUP:
1602 device_printf(sc->sc_dev, "%d UARTs detected\n",
1603 sc->sc_nports);
1604
1605 /* Set UARTs to enhanced mode */
1606 bar = puc_get_bar(sc, cfg->rid);
1607 if (bar == NULL)
1608 return (ENXIO);
1609 for (idx = 0; idx < sc->sc_nports; idx++) {
1610 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1611 0x92);
1612 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1613 value | 0x10);
1614 }
1615 return (0);
1616 case PUC_CFG_GET_LEN:
1617 *res = 0x200;
1618 return (0);
1619 case PUC_CFG_GET_NPORTS:
1620 /*
1621 * Check if we are being called from puc_bfe_attach()
1622 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1623 * puc_get_bar(), so we return a value of 16. This has cosmetic
1624 * side-effects at worst; in PUC_CFG_GET_DESC,
1625 * (int)sc->sc_cfg_data will not contain the true number of
1626 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1627 * call for this device family anyway.
1628 *
1629 * The check is for initialisation of sc->sc_bar[idx], which is
1630 * only done in puc_bfe_attach().
1631 */
1632 idx = 0;
1633 do {
1634 if (sc->sc_bar[idx++].b_rid != -1) {
1635 sc->sc_cfg_data = 16;
1636 *res = sc->sc_cfg_data;
1637 return (0);
1638 }
1639 } while (idx < PUC_PCI_BARS);
1640
1641 bar = puc_get_bar(sc, cfg->rid);
1642 if (bar == NULL)
1643 return (ENXIO);
1644
1645 value = bus_read_1(bar->b_res, 0x04);
1646 if (value == 0)
1647 return (ENXIO);
1648
1649 sc->sc_cfg_data = value;
1650 *res = sc->sc_cfg_data;
1651 return (0);
1652 case PUC_CFG_GET_OFS:
1653 *res = 0x1000 + (port << 9);
1654 return (0);
1655 case PUC_CFG_GET_TYPE:
1656 *res = PUC_TYPE_SERIAL;
1657 return (0);
1658 default:
1659 break;
1660 }
1661 return (ENXIO);
1662}
1663
1664static int
1665puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1666 intptr_t *res)
1667{
1668 int error;
1669
1670 switch (cmd) {
1671 case PUC_CFG_GET_OFS:
1672 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1673 if (error != 0)
1674 return (error);
1675 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1676 return (0);
1677 case PUC_CFG_GET_RID:
1678 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1679 if (error != 0)
1680 return (error);
1681 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1682 return (0);
1683 default:
1684 break;
1685 }
1686 return (ENXIO);
1687}
1688
1689static int
1690puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1691 intptr_t *res)
1692{
1693 switch (cmd) {
1694 case PUC_CFG_GET_OFS:
1695 *res = (port < 3) ? 0 : (port - 2) << 3;
1696 return (0);
1697 case PUC_CFG_GET_RID:
1698 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1699 return (0);
1700 default:
1701 break;
1702 }
1703 return (ENXIO);
1704}
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