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nfc_at91.c (259379) nfc_at91.c (266087)
1/*-
2 * Copyright (C) 2013 Ian Lepore.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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28 * Atmel at91-family integrated NAND controller driver.
29 *
30 * This code relies on the board setup code (in at91/board_whatever.c) having
31 * set up the EBI and SMC registers appropriately for whatever type of nand part
32 * is on the board.
33 */
34
35#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2013 Ian Lepore.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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28 * Atmel at91-family integrated NAND controller driver.
29 *
30 * This code relies on the board setup code (in at91/board_whatever.c) having
31 * set up the EBI and SMC registers appropriately for whatever type of nand part
32 * is on the board.
33 */
34
35#include <sys/cdefs.h>
36__FBSDID("$FreeBSD: stable/10/sys/dev/nand/nfc_at91.c 259379 2013-12-14 01:15:26Z ian $");
36__FBSDID("$FreeBSD: stable/10/sys/dev/nand/nfc_at91.c 266087 2014-05-14 20:31:54Z ian $");
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/proc.h>
41#include <sys/bus.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>

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49#include <sys/time.h>
50
51#include <machine/bus.h>
52
53#include <dev/nand/nand.h>
54#include <dev/nand/nandbus.h>
55#include "nfc_if.h"
56
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/proc.h>
41#include <sys/bus.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>

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49#include <sys/time.h>
50
51#include <machine/bus.h>
52
53#include <dev/nand/nand.h>
54#include <dev/nand/nandbus.h>
55#include "nfc_if.h"
56
57#include <dev/nand/nfc_at91.h>
58#include <arm/at91/at91_smc.h>
59
57/*
58 * Data cycles are triggered by access to any address within the EBI CS3 region
59 * that has A21 and A22 clear. Command cycles are any access with bit A21
60/*
61 * Data cycles are triggered by access to any address within the EBI CS3 region
62 * that has A21 and A22 clear. Command cycles are any access with bit A21
60 * asserted. Address cycles are any access with bit A22 asserted.
61 *
62 * XXX The atmel docs say that any address bits can be used instead of A21 and
63 * A22; these values should be configurable.
63 * asserted. Address cycles are any access with bit A22 asserted. Or vice versa.
64 * We get these parameters from the nand_param that the board is required to
65 * call at91_enable_nand, and enable the GPIO lines properly (that will be moved
66 * into at91_enable_nand when the great GPIO pin renumbering happens). We use
67 * ale (Address Latch Enable) and cle (Comand Latch Enable) to match the hardware
68 * names used in NAND.
64 */
65#define AT91_NAND_DATA 0
69 */
70#define AT91_NAND_DATA 0
66#define AT91_NAND_COMMAND (1 << 21)
67#define AT91_NAND_ADDRESS (1 << 22)
68
69struct at91_nand_softc {
70 struct nand_softc nand_sc;
71 struct resource *res;
71
72struct at91_nand_softc {
73 struct nand_softc nand_sc;
74 struct resource *res;
75 struct at91_nand_params *nand_param;
72};
73
76};
77
78static struct at91_nand_params nand_param;
79
74static int at91_nand_attach(device_t);
75static int at91_nand_probe(device_t);
76static uint8_t at91_nand_read_byte(device_t);
77static void at91_nand_read_buf(device_t, void *, uint32_t);
78static int at91_nand_read_rnb(device_t);
79static int at91_nand_select_cs(device_t, uint8_t);
80static int at91_nand_send_command(device_t, uint8_t);
81static int at91_nand_send_address(device_t, uint8_t);
82static void at91_nand_write_buf(device_t, void *, uint32_t);
83
80static int at91_nand_attach(device_t);
81static int at91_nand_probe(device_t);
82static uint8_t at91_nand_read_byte(device_t);
83static void at91_nand_read_buf(device_t, void *, uint32_t);
84static int at91_nand_read_rnb(device_t);
85static int at91_nand_select_cs(device_t, uint8_t);
86static int at91_nand_send_command(device_t, uint8_t);
87static int at91_nand_send_address(device_t, uint8_t);
88static void at91_nand_write_buf(device_t, void *, uint32_t);
89
90void
91at91_enable_nand(const struct at91_nand_params *np)
92{
93 nand_param = *np;
94}
95
84static inline u_int8_t
85dev_read_1(struct at91_nand_softc *sc, bus_size_t offset)
86{
87 return bus_read_1(sc->res, offset);
88}
89
90static inline void
91dev_write_1(struct at91_nand_softc *sc, bus_size_t offset, u_int8_t value)

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103
104static int
105at91_nand_attach(device_t dev)
106{
107 struct at91_nand_softc *sc;
108 int err, rid;
109
110 sc = device_get_softc(dev);
96static inline u_int8_t
97dev_read_1(struct at91_nand_softc *sc, bus_size_t offset)
98{
99 return bus_read_1(sc->res, offset);
100}
101
102static inline void
103dev_write_1(struct at91_nand_softc *sc, bus_size_t offset, u_int8_t value)

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115
116static int
117at91_nand_attach(device_t dev)
118{
119 struct at91_nand_softc *sc;
120 int err, rid;
121
122 sc = device_get_softc(dev);
123 sc->nand_param = &nand_param;
124 if (sc->nand_param->width != 8 && sc->nand_param->width != 16) {
125 device_printf(dev, "Bad bus width (%d) defaulting to 8 bits\n",
126 sc->nand_param->width);
127 sc->nand_param->width = 8;
128 }
129 at91_ebi_enable(sc->nand_param->cs);
130
111 rid = 0;
112 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
113 RF_ACTIVE);
114 if (sc->res == NULL) {
115 device_printf(dev, "could not allocate resources!\n");
116 return (ENXIO);
117 }
118

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123 return (err);
124}
125
126static int
127at91_nand_send_command(device_t dev, uint8_t command)
128{
129 struct at91_nand_softc *sc;
130
131 rid = 0;
132 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
133 RF_ACTIVE);
134 if (sc->res == NULL) {
135 device_printf(dev, "could not allocate resources!\n");
136 return (ENXIO);
137 }
138

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143 return (err);
144}
145
146static int
147at91_nand_send_command(device_t dev, uint8_t command)
148{
149 struct at91_nand_softc *sc;
150
131 /* nand_debug(NDBG_DRV,"at91_nand_send_command: 0x%02x", command); */
151 nand_debug(NDBG_DRV,"at91_nand_send_command: 0x%02x", command);
132
133 sc = device_get_softc(dev);
152
153 sc = device_get_softc(dev);
134 dev_write_1(sc, AT91_NAND_COMMAND, command);
154 dev_write_1(sc, sc->nand_param->cle, command);
135 return (0);
136}
137
138static int
139at91_nand_send_address(device_t dev, uint8_t addr)
140{
141 struct at91_nand_softc *sc;
142
155 return (0);
156}
157
158static int
159at91_nand_send_address(device_t dev, uint8_t addr)
160{
161 struct at91_nand_softc *sc;
162
143 /* nand_debug(NDBG_DRV,"at91_nand_send_address: x%02x", addr); */
163 nand_debug(NDBG_DRV,"at91_nand_send_address: x%02x", addr);
144
145 sc = device_get_softc(dev);
164
165 sc = device_get_softc(dev);
146 dev_write_1(sc, AT91_NAND_ADDRESS, addr);
166 dev_write_1(sc, sc->nand_param->ale, addr);
147 return (0);
148}
149
150static uint8_t
151at91_nand_read_byte(device_t dev)
152{
153 struct at91_nand_softc *sc;
154 uint8_t data;
155
156 sc = device_get_softc(dev);
157 data = dev_read_1(sc, AT91_NAND_DATA);
158
167 return (0);
168}
169
170static uint8_t
171at91_nand_read_byte(device_t dev)
172{
173 struct at91_nand_softc *sc;
174 uint8_t data;
175
176 sc = device_get_softc(dev);
177 data = dev_read_1(sc, AT91_NAND_DATA);
178
159 /* nand_debug(NDBG_DRV,"at91_nand_read_byte: 0x%02x", data); */
179 nand_debug(NDBG_DRV,"at91_nand_read_byte: 0x%02x", data);
160
161 return (data);
162}
163
164
165static void
166at91_nand_dump_buf(const char *op, void* buf, uint32_t len)
167{

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181 return (data);
182}
183
184
185static void
186at91_nand_dump_buf(const char *op, void* buf, uint32_t len)
187{

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