1/*-
2 * Copyright (c) 2004
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 213893 2010-10-15 14:52:11Z marius $");
35
36/*
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/ciphyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60
61static int ciphy_probe(device_t);
62static int ciphy_attach(device_t);
63
64static device_method_t ciphy_methods[] = {
65 /* device interface */
66 DEVMETHOD(device_probe, ciphy_probe),
67 DEVMETHOD(device_attach, ciphy_attach),
68 DEVMETHOD(device_detach, mii_phy_detach),
69 DEVMETHOD(device_shutdown, bus_generic_shutdown),
70 { 0, 0 }
71};
72
73static devclass_t ciphy_devclass;
74
75static driver_t ciphy_driver = {
76 "ciphy",
77 ciphy_methods,
78 sizeof(struct mii_softc)
79};
80
81DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
82
83static int ciphy_service(struct mii_softc *, struct mii_data *, int);
84static void ciphy_status(struct mii_softc *);
85static void ciphy_reset(struct mii_softc *);
86static void ciphy_fixup(struct mii_softc *);
87
88static const struct mii_phydesc ciphys[] = {
89 MII_PHY_DESC(CICADA, CS8201),
90 MII_PHY_DESC(CICADA, CS8201A),
91 MII_PHY_DESC(CICADA, CS8201B),
92 MII_PHY_DESC(CICADA, CS8204),
93 MII_PHY_DESC(CICADA, VSC8211),
94 MII_PHY_DESC(CICADA, CS8244),
95 MII_PHY_DESC(VITESSE, VSC8601),
96 MII_PHY_END
97};
98
99static int
100ciphy_probe(device_t dev)
101{
102
103 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
104}
105
106static int
107ciphy_attach(device_t dev)
108{
109 struct mii_softc *sc;
110 struct mii_attach_args *ma;
111 struct mii_data *mii;
112
113 sc = device_get_softc(dev);
114 ma = device_get_ivars(dev);
115 sc->mii_dev = device_get_parent(dev);
116 mii = ma->mii_data;
117 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
118
119 sc->mii_flags = miibus_get_flags(dev);
120 sc->mii_inst = mii->mii_instance++;
121 sc->mii_phy = ma->mii_phyno;
122 sc->mii_service = ciphy_service;
123 sc->mii_pdata = mii;
124
125 sc->mii_flags |= MIIF_NOISOLATE;
126
127 ciphy_reset(sc);
128
129 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
130 if (sc->mii_capabilities & BMSR_EXTSTAT)
131 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
132 device_printf(dev, " ");
133 mii_phy_add_media(sc);
134 printf("\n");
135
136 MIIBUS_MEDIAINIT(sc->mii_dev);
137 return (0);
138}
139
140static int
141ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
142{
143 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
144 int reg, speed, gig;
145
146 switch (cmd) {
147 case MII_POLLSTAT:
148 break;
149
150 case MII_MEDIACHG:
151 /*
152 * If the interface is not up, don't do anything.
153 */
154 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
155 break;
156
157 ciphy_fixup(sc); /* XXX hardware bug work-around */
158
159 switch (IFM_SUBTYPE(ife->ifm_media)) {
160 case IFM_AUTO:
161#ifdef foo
162 /*
163 * If we're already in auto mode, just return.
164 */
165 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
166 return (0);
167#endif
168 (void) mii_phy_auto(sc);
169 break;
170 case IFM_1000_T:
171 speed = CIPHY_S1000;
172 goto setit;
173 case IFM_100_TX:
174 speed = CIPHY_S100;
175 goto setit;
176 case IFM_10_T:
177 speed = CIPHY_S10;
178setit:
179 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
180 speed |= CIPHY_BMCR_FDX;
181 gig = CIPHY_1000CTL_AFD;
182 } else {
183 gig = CIPHY_1000CTL_AHD;
184 }
185
186 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
187 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
188 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
189
190 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
191 break;
192
193 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
194 PHY_WRITE(sc, CIPHY_MII_BMCR,
195 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
196
197 /*
198 * When setting the link manually, one side must
199 * be the master and the other the slave. However
200 * ifmedia doesn't give us a good way to specify
201 * this, so we fake it by using one of the LINK
202 * flags. If LINK0 is set, we program the PHY to
203 * be a master, otherwise it's a slave.
204 */
205 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
206 PHY_WRITE(sc, CIPHY_MII_1000CTL,
207 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
208 } else {
209 PHY_WRITE(sc, CIPHY_MII_1000CTL,
210 gig|CIPHY_1000CTL_MSE);
211 }
212 break;
213 case IFM_NONE:
214 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
215 break;
216 case IFM_100_T4:
217 default:
218 return (EINVAL);
219 }
220 break;
221
222 case MII_TICK:
223 /*
224 * Is the interface even up?
225 */
226 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
227 return (0);
228
229 /*
230 * Only used for autonegotiation.
231 */
232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
233 break;
234
235 /*
236 * Check to see if we have link. If we do, we don't
237 * need to restart the autonegotiation process. Read
238 * the BMSR twice in case it's latched.
239 */
240 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
241 if (reg & BMSR_LINK)
242 break;
243
244 /* Announce link loss right after it happens. */
245 if (++sc->mii_ticks == 0)
246 break;
247 /*
248 * Only retry autonegotiation every mii_anegticks seconds.
249 */
250 if (sc->mii_ticks <= sc->mii_anegticks)
251 break;
252
253 sc->mii_ticks = 0;
254 mii_phy_auto(sc);
255 break;
256 }
257
258 /* Update the media status. */
259 ciphy_status(sc);
260
261 /*
262 * Callback if something changed. Note that we need to poke
263 * apply fixups for certain PHY revs.
264 */
265 if (sc->mii_media_active != mii->mii_media_active ||
266 sc->mii_media_status != mii->mii_media_status ||
267 cmd == MII_MEDIACHG) {
268 ciphy_fixup(sc);
269 }
270 mii_phy_update(sc, cmd);
271 return (0);
272}
273
274static void
275ciphy_status(struct mii_softc *sc)
276{
277 struct mii_data *mii = sc->mii_pdata;
278 int bmsr, bmcr;
279
280 mii->mii_media_status = IFM_AVALID;
281 mii->mii_media_active = IFM_ETHER;
282
283 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
284
285 if (bmsr & BMSR_LINK)
286 mii->mii_media_status |= IFM_ACTIVE;
287
288 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
289
290 if (bmcr & CIPHY_BMCR_LOOP)
291 mii->mii_media_active |= IFM_LOOP;
292
293 if (bmcr & CIPHY_BMCR_AUTOEN) {
294 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
295 /* Erg, still trying, I guess... */
296 mii->mii_media_active |= IFM_NONE;
297 return;
298 }
299 }
300
301 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
302 switch (bmsr & CIPHY_AUXCSR_SPEED) {
303 case CIPHY_SPEED10:
304 mii->mii_media_active |= IFM_10_T;
305 break;
306 case CIPHY_SPEED100:
307 mii->mii_media_active |= IFM_100_TX;
308 break;
309 case CIPHY_SPEED1000:
310 mii->mii_media_active |= IFM_1000_T;
311 break;
312 default:
313 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
314 bmsr & CIPHY_AUXCSR_SPEED);
315 break;
316 }
317
318 if (bmsr & CIPHY_AUXCSR_FDX)
319 mii->mii_media_active |= IFM_FDX;
320 else
321 mii->mii_media_active |= IFM_HDX;
322}
323
324static void
325ciphy_reset(struct mii_softc *sc)
326{
327
328 mii_phy_reset(sc);
329 DELAY(1000);
330}
331
332#define PHY_SETBIT(x, y, z) \
333 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
334#define PHY_CLRBIT(x, y, z) \
335 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
336
337static void
338ciphy_fixup(struct mii_softc *sc)
339{
340 uint16_t model;
341 uint16_t status, speed;
342 uint16_t val;
343
344 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
345 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
346 speed = status & CIPHY_AUXCSR_SPEED;
347
348 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
349 "nfe") == 0) {
350 /* need to set for 2.5V RGMII for NVIDIA adapters */
351 val = PHY_READ(sc, CIPHY_MII_ECTL1);
352 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
353 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
354 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
355 /* From Linux. */
356 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
357 val |= CIPHY_AUXCSR_MDPPS;
358 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
359 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
360 val |= CIPHY_10BTCSR_ECHO;
361 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
362 }
363
364 switch (model) {
365 case MII_MODEL_CICADA_CS8204:
366 case MII_MODEL_CICADA_CS8201:
367
368 /* Turn off "aux mode" (whatever that means) */
369 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
370
371 /*
372 * Work around speed polling bug in VT3119/VT3216
373 * when using MII in full duplex mode.
374 */
375 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
376 (status & CIPHY_AUXCSR_FDX)) {
377 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
378 } else {
379 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
380 }
381
382 /* Enable link/activity LED blink. */
383 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
384
385 break;
386
387 case MII_MODEL_CICADA_CS8201A:
388 case MII_MODEL_CICADA_CS8201B:
389
390 /*
391 * Work around speed polling bug in VT3119/VT3216
392 * when using MII in full duplex mode.
393 */
394 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
395 (status & CIPHY_AUXCSR_FDX)) {
396 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
397 } else {
398 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
399 }
400
401 break;
402 case MII_MODEL_CICADA_VSC8211:
403 case MII_MODEL_CICADA_CS8244:
404 case MII_MODEL_VITESSE_VSC8601:
405 break;
406 default:
407 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
408 model);
409 break;
410 }
411}
2 * Copyright (c) 2004
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 213893 2010-10-15 14:52:11Z marius $");
35
36/*
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/ciphyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60
61static int ciphy_probe(device_t);
62static int ciphy_attach(device_t);
63
64static device_method_t ciphy_methods[] = {
65 /* device interface */
66 DEVMETHOD(device_probe, ciphy_probe),
67 DEVMETHOD(device_attach, ciphy_attach),
68 DEVMETHOD(device_detach, mii_phy_detach),
69 DEVMETHOD(device_shutdown, bus_generic_shutdown),
70 { 0, 0 }
71};
72
73static devclass_t ciphy_devclass;
74
75static driver_t ciphy_driver = {
76 "ciphy",
77 ciphy_methods,
78 sizeof(struct mii_softc)
79};
80
81DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
82
83static int ciphy_service(struct mii_softc *, struct mii_data *, int);
84static void ciphy_status(struct mii_softc *);
85static void ciphy_reset(struct mii_softc *);
86static void ciphy_fixup(struct mii_softc *);
87
88static const struct mii_phydesc ciphys[] = {
89 MII_PHY_DESC(CICADA, CS8201),
90 MII_PHY_DESC(CICADA, CS8201A),
91 MII_PHY_DESC(CICADA, CS8201B),
92 MII_PHY_DESC(CICADA, CS8204),
93 MII_PHY_DESC(CICADA, VSC8211),
94 MII_PHY_DESC(CICADA, CS8244),
95 MII_PHY_DESC(VITESSE, VSC8601),
96 MII_PHY_END
97};
98
99static int
100ciphy_probe(device_t dev)
101{
102
103 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
104}
105
106static int
107ciphy_attach(device_t dev)
108{
109 struct mii_softc *sc;
110 struct mii_attach_args *ma;
111 struct mii_data *mii;
112
113 sc = device_get_softc(dev);
114 ma = device_get_ivars(dev);
115 sc->mii_dev = device_get_parent(dev);
116 mii = ma->mii_data;
117 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
118
119 sc->mii_flags = miibus_get_flags(dev);
120 sc->mii_inst = mii->mii_instance++;
121 sc->mii_phy = ma->mii_phyno;
122 sc->mii_service = ciphy_service;
123 sc->mii_pdata = mii;
124
125 sc->mii_flags |= MIIF_NOISOLATE;
126
127 ciphy_reset(sc);
128
129 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
130 if (sc->mii_capabilities & BMSR_EXTSTAT)
131 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
132 device_printf(dev, " ");
133 mii_phy_add_media(sc);
134 printf("\n");
135
136 MIIBUS_MEDIAINIT(sc->mii_dev);
137 return (0);
138}
139
140static int
141ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
142{
143 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
144 int reg, speed, gig;
145
146 switch (cmd) {
147 case MII_POLLSTAT:
148 break;
149
150 case MII_MEDIACHG:
151 /*
152 * If the interface is not up, don't do anything.
153 */
154 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
155 break;
156
157 ciphy_fixup(sc); /* XXX hardware bug work-around */
158
159 switch (IFM_SUBTYPE(ife->ifm_media)) {
160 case IFM_AUTO:
161#ifdef foo
162 /*
163 * If we're already in auto mode, just return.
164 */
165 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
166 return (0);
167#endif
168 (void) mii_phy_auto(sc);
169 break;
170 case IFM_1000_T:
171 speed = CIPHY_S1000;
172 goto setit;
173 case IFM_100_TX:
174 speed = CIPHY_S100;
175 goto setit;
176 case IFM_10_T:
177 speed = CIPHY_S10;
178setit:
179 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
180 speed |= CIPHY_BMCR_FDX;
181 gig = CIPHY_1000CTL_AFD;
182 } else {
183 gig = CIPHY_1000CTL_AHD;
184 }
185
186 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
187 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
188 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
189
190 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
191 break;
192
193 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
194 PHY_WRITE(sc, CIPHY_MII_BMCR,
195 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
196
197 /*
198 * When setting the link manually, one side must
199 * be the master and the other the slave. However
200 * ifmedia doesn't give us a good way to specify
201 * this, so we fake it by using one of the LINK
202 * flags. If LINK0 is set, we program the PHY to
203 * be a master, otherwise it's a slave.
204 */
205 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
206 PHY_WRITE(sc, CIPHY_MII_1000CTL,
207 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
208 } else {
209 PHY_WRITE(sc, CIPHY_MII_1000CTL,
210 gig|CIPHY_1000CTL_MSE);
211 }
212 break;
213 case IFM_NONE:
214 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
215 break;
216 case IFM_100_T4:
217 default:
218 return (EINVAL);
219 }
220 break;
221
222 case MII_TICK:
223 /*
224 * Is the interface even up?
225 */
226 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
227 return (0);
228
229 /*
230 * Only used for autonegotiation.
231 */
232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
233 break;
234
235 /*
236 * Check to see if we have link. If we do, we don't
237 * need to restart the autonegotiation process. Read
238 * the BMSR twice in case it's latched.
239 */
240 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
241 if (reg & BMSR_LINK)
242 break;
243
244 /* Announce link loss right after it happens. */
245 if (++sc->mii_ticks == 0)
246 break;
247 /*
248 * Only retry autonegotiation every mii_anegticks seconds.
249 */
250 if (sc->mii_ticks <= sc->mii_anegticks)
251 break;
252
253 sc->mii_ticks = 0;
254 mii_phy_auto(sc);
255 break;
256 }
257
258 /* Update the media status. */
259 ciphy_status(sc);
260
261 /*
262 * Callback if something changed. Note that we need to poke
263 * apply fixups for certain PHY revs.
264 */
265 if (sc->mii_media_active != mii->mii_media_active ||
266 sc->mii_media_status != mii->mii_media_status ||
267 cmd == MII_MEDIACHG) {
268 ciphy_fixup(sc);
269 }
270 mii_phy_update(sc, cmd);
271 return (0);
272}
273
274static void
275ciphy_status(struct mii_softc *sc)
276{
277 struct mii_data *mii = sc->mii_pdata;
278 int bmsr, bmcr;
279
280 mii->mii_media_status = IFM_AVALID;
281 mii->mii_media_active = IFM_ETHER;
282
283 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
284
285 if (bmsr & BMSR_LINK)
286 mii->mii_media_status |= IFM_ACTIVE;
287
288 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
289
290 if (bmcr & CIPHY_BMCR_LOOP)
291 mii->mii_media_active |= IFM_LOOP;
292
293 if (bmcr & CIPHY_BMCR_AUTOEN) {
294 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
295 /* Erg, still trying, I guess... */
296 mii->mii_media_active |= IFM_NONE;
297 return;
298 }
299 }
300
301 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
302 switch (bmsr & CIPHY_AUXCSR_SPEED) {
303 case CIPHY_SPEED10:
304 mii->mii_media_active |= IFM_10_T;
305 break;
306 case CIPHY_SPEED100:
307 mii->mii_media_active |= IFM_100_TX;
308 break;
309 case CIPHY_SPEED1000:
310 mii->mii_media_active |= IFM_1000_T;
311 break;
312 default:
313 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
314 bmsr & CIPHY_AUXCSR_SPEED);
315 break;
316 }
317
318 if (bmsr & CIPHY_AUXCSR_FDX)
319 mii->mii_media_active |= IFM_FDX;
320 else
321 mii->mii_media_active |= IFM_HDX;
322}
323
324static void
325ciphy_reset(struct mii_softc *sc)
326{
327
328 mii_phy_reset(sc);
329 DELAY(1000);
330}
331
332#define PHY_SETBIT(x, y, z) \
333 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
334#define PHY_CLRBIT(x, y, z) \
335 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
336
337static void
338ciphy_fixup(struct mii_softc *sc)
339{
340 uint16_t model;
341 uint16_t status, speed;
342 uint16_t val;
343
344 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
345 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
346 speed = status & CIPHY_AUXCSR_SPEED;
347
348 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
349 "nfe") == 0) {
350 /* need to set for 2.5V RGMII for NVIDIA adapters */
351 val = PHY_READ(sc, CIPHY_MII_ECTL1);
352 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
353 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
354 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
355 /* From Linux. */
356 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
357 val |= CIPHY_AUXCSR_MDPPS;
358 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
359 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
360 val |= CIPHY_10BTCSR_ECHO;
361 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
362 }
363
364 switch (model) {
365 case MII_MODEL_CICADA_CS8204:
366 case MII_MODEL_CICADA_CS8201:
367
368 /* Turn off "aux mode" (whatever that means) */
369 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
370
371 /*
372 * Work around speed polling bug in VT3119/VT3216
373 * when using MII in full duplex mode.
374 */
375 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
376 (status & CIPHY_AUXCSR_FDX)) {
377 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
378 } else {
379 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
380 }
381
382 /* Enable link/activity LED blink. */
383 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
384
385 break;
386
387 case MII_MODEL_CICADA_CS8201A:
388 case MII_MODEL_CICADA_CS8201B:
389
390 /*
391 * Work around speed polling bug in VT3119/VT3216
392 * when using MII in full duplex mode.
393 */
394 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
395 (status & CIPHY_AUXCSR_FDX)) {
396 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
397 } else {
398 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
399 }
400
401 break;
402 case MII_MODEL_CICADA_VSC8211:
403 case MII_MODEL_CICADA_CS8244:
404 case MII_MODEL_VITESSE_VSC8601:
405 break;
406 default:
407 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
408 model);
409 break;
410 }
411}