| ispreg.h (52346) | ispreg.h (54671) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 52346 1999-10-17 18:41:47Z mjacob $ */ | 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 54671 1999-12-16 05:42:02Z mjacob $ */ |
| 2/* 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 * --- 82 unchanged lines hidden (view full) --- 92#define SXP_BLOCK (2 << _BLK_REG_SHFT) 93#define RISC_BLOCK (3 << _BLK_REG_SHFT) 94#define DMA_BLOCK (4 << _BLK_REG_SHFT) 95 96/* 97 * Bus Interface Block Register Offsets 98 */ 99 | 2/* 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 * --- 82 unchanged lines hidden (view full) --- 92#define SXP_BLOCK (2 << _BLK_REG_SHFT) 93#define RISC_BLOCK (3 << _BLK_REG_SHFT) 94#define DMA_BLOCK (4 << _BLK_REG_SHFT) 95 96/* 97 * Bus Interface Block Register Offsets 98 */ 99 |
| 100#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 101#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 102#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 103#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 104#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 105#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 106#define BIU2100_CSR BIU_BLOCK+0x6 107#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 108#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 109#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 110#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 111#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ | 100#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 101#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 102#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 103#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 104#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 105#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 106#define BIU2100_CSR (BIU_BLOCK+0x6) 107#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 108#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 109#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 110#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 111#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ |
| 112#define RDMA2100_CONTROL DFIFO_COMMAND | 112#define RDMA2100_CONTROL DFIFO_COMMAND |
| 113#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ | 113#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ |
| 114 115/* 116 * Putzed DMA register layouts. 117 */ | 114 115/* 116 * Putzed DMA register layouts. 117 */ |
| 118#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */ | 118#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ |
| 119#define CDMA2100_CONTROL CDMA_CONF | 119#define CDMA2100_CONTROL CDMA_CONF |
| 120#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */ 121#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */ 122#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */ 123#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */ 124#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 125#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 126#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 127#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ | 120#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 121#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 122#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 123#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 124#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 125#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 126#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 127#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ |
| 128 | 128 |
| 129#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */ | 129#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ |
| 130#define TDMA2100_CONTROL DDMA_CONF | 130#define TDMA2100_CONTROL DDMA_CONF |
| 131#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */ 132#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */ 133#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */ 134#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 135#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 136#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 137#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ | 131#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 132#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 133#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 134#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 135#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 136#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 137#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ |
| 138/* these are for the 1040A cards */ | 138/* these are for the 1040A cards */ |
| 139#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 140#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ | 139#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 140#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ |
| 141 142 143/* 144 * Bus Interface Block Register Definitions 145 */ 146/* BUS CONFIGURATION REGISTER #0 */ 147#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 148/* BUS CONFIGURATION REGISTER #1 */ --- 8 unchanged lines hidden (view full) --- 157#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 158#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 159#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 160#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 161#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 162#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 163#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 164 | 141 142 143/* 144 * Bus Interface Block Register Definitions 145 */ 146/* BUS CONFIGURATION REGISTER #0 */ 147#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 148/* BUS CONFIGURATION REGISTER #1 */ --- 8 unchanged lines hidden (view full) --- 157#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 158#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 159#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 160#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 161#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 162#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 163#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 164 |
| 165#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */ | 165#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 166#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ |
| 166#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 167 168/* ISP2100 Bus Control/Status Register */ 169 170#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 171#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 172#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 173#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ --- 139 unchanged lines hidden (view full) --- 313#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 314#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 315#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 316 317/* 318 * Mailbox Block Register Offsets 319 */ 320 | 167#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 168 169/* ISP2100 Bus Control/Status Register */ 170 171#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 172#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 173#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 174#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ --- 139 unchanged lines hidden (view full) --- 314#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 315#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 316#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 317 318/* 319 * Mailbox Block Register Offsets 320 */ 321 |
| 321#define INMAILBOX0 MBOX_BLOCK+0x0 322#define INMAILBOX1 MBOX_BLOCK+0x2 323#define INMAILBOX2 MBOX_BLOCK+0x4 324#define INMAILBOX3 MBOX_BLOCK+0x6 325#define INMAILBOX4 MBOX_BLOCK+0x8 326#define INMAILBOX5 MBOX_BLOCK+0xA 327#define INMAILBOX6 MBOX_BLOCK+0xC 328#define INMAILBOX7 MBOX_BLOCK+0xE | 322#define INMAILBOX0 (MBOX_BLOCK+0x0) 323#define INMAILBOX1 (MBOX_BLOCK+0x2) 324#define INMAILBOX2 (MBOX_BLOCK+0x4) 325#define INMAILBOX3 (MBOX_BLOCK+0x6) 326#define INMAILBOX4 (MBOX_BLOCK+0x8) 327#define INMAILBOX5 (MBOX_BLOCK+0xA) 328#define INMAILBOX6 (MBOX_BLOCK+0xC) 329#define INMAILBOX7 (MBOX_BLOCK+0xE) |
| 329 | 330 |
| 330#define OUTMAILBOX0 MBOX_BLOCK+0x0 331#define OUTMAILBOX1 MBOX_BLOCK+0x2 332#define OUTMAILBOX2 MBOX_BLOCK+0x4 333#define OUTMAILBOX3 MBOX_BLOCK+0x6 334#define OUTMAILBOX4 MBOX_BLOCK+0x8 335#define OUTMAILBOX5 MBOX_BLOCK+0xA 336#define OUTMAILBOX6 MBOX_BLOCK+0xC 337#define OUTMAILBOX7 MBOX_BLOCK+0xE | 331#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 332#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 333#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 334#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 335#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 336#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 337#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 338#define OUTMAILBOX7 (MBOX_BLOCK+0xE) |
| 338 339#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 340#define NMBOX(isp) \ 341 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 342 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 343 344/* 345 * SXP Block Register Offsets 346 */ | 339 340#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 341#define NMBOX(isp) \ 342 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 343 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 344 345/* 346 * SXP Block Register Offsets 347 */ |
| 347#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 348#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 349#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 350#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 351#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 352#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 353#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 354#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 355#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 356#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 357#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 358#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 359#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 360#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 361#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 362#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 363#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 364#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 365#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 366#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 367#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 368#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 369#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 370#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 371#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 372#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 373#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 374#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 375#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 376#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 377#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 378#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 379#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 380#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 381#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 382#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 383#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 384#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 385#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ | 348#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 349#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 350#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 351#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 352#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 353#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 354#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 355#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 356#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 357#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 358#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 359#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 360#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 361#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 362#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 363#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 364#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 365#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 366#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 367#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 368#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 369#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 370#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 371#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 372#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 373#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 374#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 375#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 376#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 377#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 378#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 379#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 380#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 381#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 382#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 383#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 384#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 385#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 386#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ |
| 386 | 387 |
| 388/* for 1080/1280/1240 only */ 389#define SXP_BANK1_SELECT 0x100 |
|
| 387 | 390 |
| 391 |
|
| 388/* SXP CONF1 REGISTER */ 389#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 390#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 391#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 392#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 393#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 394 395/* SXP CONF2 REGISTER */ --- 110 unchanged lines hidden (view full) --- 506/* SXP DIFF PINS REGISTER */ 507#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 508#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 509#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 510#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 511#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 512#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 513 | 392/* SXP CONF1 REGISTER */ 393#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 394#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 395#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 396#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 397#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 398 399/* SXP CONF2 REGISTER */ --- 110 unchanged lines hidden (view full) --- 510/* SXP DIFF PINS REGISTER */ 511#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 512#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 513#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 514#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 515#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 516#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 517 |
| 514/* 1080 only */ | 518/* Ultra2 only */ |
| 515#define SXP_PINS_LVD_MODE 0x1000 516#define SXP_PINS_HVD_MODE 0x0800 517#define SXP_PINS_SE_MODE 0x0400 518 519/* The above have to be put together with the DIFFM pin to make sense */ 520#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 521#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 522#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) --- 321 unchanged lines hidden --- | 519#define SXP_PINS_LVD_MODE 0x1000 520#define SXP_PINS_HVD_MODE 0x0800 521#define SXP_PINS_SE_MODE 0x0400 522 523/* The above have to be put together with the DIFFM pin to make sense */ 524#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 525#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 526#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) --- 321 unchanged lines hidden --- |