1/* $FreeBSD: stable/10/sys/dev/isp/ispmbox.h 291519 2015-11-30 21:44:03Z mav $ */
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30/*
31 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
32 */
33#ifndef _ISPMBOX_H
34#define _ISPMBOX_H
35
36/*
37 * Mailbox Command Opcodes
38 */
39#define MBOX_NO_OP 0x0000
40#define MBOX_LOAD_RAM 0x0001
41#define MBOX_EXEC_FIRMWARE 0x0002
42#define MBOX_DUMP_RAM 0x0003
43#define MBOX_WRITE_RAM_WORD 0x0004
44#define MBOX_READ_RAM_WORD 0x0005
45#define MBOX_MAILBOX_REG_TEST 0x0006
46#define MBOX_VERIFY_CHECKSUM 0x0007
47#define MBOX_ABOUT_FIRMWARE 0x0008
48#define MBOX_LOAD_RISC_RAM_2100 0x0009
49 /* a */
50#define MBOX_LOAD_RISC_RAM 0x000b
51#define MBOX_DUMP_RISC_RAM 0x000c
52#define MBOX_WRITE_RAM_WORD_EXTENDED 0x000d
53#define MBOX_CHECK_FIRMWARE 0x000e
54#define MBOX_READ_RAM_WORD_EXTENDED 0x000f
55#define MBOX_INIT_REQ_QUEUE 0x0010
56#define MBOX_INIT_RES_QUEUE 0x0011
57#define MBOX_EXECUTE_IOCB 0x0012
58#define MBOX_WAKE_UP 0x0013
59#define MBOX_STOP_FIRMWARE 0x0014
60#define MBOX_ABORT 0x0015
61#define MBOX_ABORT_DEVICE 0x0016
62#define MBOX_ABORT_TARGET 0x0017
63#define MBOX_BUS_RESET 0x0018
64#define MBOX_STOP_QUEUE 0x0019
65#define MBOX_START_QUEUE 0x001a
66#define MBOX_SINGLE_STEP_QUEUE 0x001b
67#define MBOX_ABORT_QUEUE 0x001c
68#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
69 /* 1e */
70#define MBOX_GET_FIRMWARE_STATUS 0x001f
71#define MBOX_GET_INIT_SCSI_ID 0x0020
72#define MBOX_GET_SELECT_TIMEOUT 0x0021
73#define MBOX_GET_RETRY_COUNT 0x0022
74#define MBOX_GET_TAG_AGE_LIMIT 0x0023
75#define MBOX_GET_CLOCK_RATE 0x0024
76#define MBOX_GET_ACT_NEG_STATE 0x0025
77#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
78#define MBOX_GET_SBUS_PARAMS 0x0027
79#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS
80#define MBOX_GET_TARGET_PARAMS 0x0028
81#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
82#define MBOX_GET_RESET_DELAY_PARAMS 0x002a
83 /* 2b */
84 /* 2c */
85 /* 2d */
86 /* 2e */
87 /* 2f */
88#define MBOX_SET_INIT_SCSI_ID 0x0030
89#define MBOX_SET_SELECT_TIMEOUT 0x0031
90#define MBOX_SET_RETRY_COUNT 0x0032
91#define MBOX_SET_TAG_AGE_LIMIT 0x0033
92#define MBOX_SET_CLOCK_RATE 0x0034
93#define MBOX_SET_ACT_NEG_STATE 0x0035
94#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
95#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
96#define MBOX_SET_PCI_PARAMETERS 0x0037
97#define MBOX_SET_TARGET_PARAMS 0x0038
98#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
99#define MBOX_SET_RESET_DELAY_PARAMS 0x003a
100 /* 3b */
101 /* 3c */
102 /* 3d */
103 /* 3e */
104 /* 3f */
105#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
106#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
107#define MBOX_EXEC_BIOS_IOCB 0x0042
108#define MBOX_SET_FW_FEATURES 0x004a
109#define MBOX_GET_FW_FEATURES 0x004b
110#define FW_FEATURE_FAST_POST 0x1
111#define FW_FEATURE_LVD_NOTIFY 0x2
112#define FW_FEATURE_RIO_32BIT 0x4
113#define FW_FEATURE_RIO_16BIT 0x8
114
115#define MBOX_INIT_REQ_QUEUE_A64 0x0052
116#define MBOX_INIT_RES_QUEUE_A64 0x0053
117
118#define MBOX_ENABLE_TARGET_MODE 0x0055
119#define ENABLE_TARGET_FLAG 0x8000
120#define ENABLE_TQING_FLAG 0x0004
121#define ENABLE_MANDATORY_DISC 0x0002
122#define MBOX_GET_TARGET_STATUS 0x0056
123
124/* These are for the ISP2X00 FC cards */
125#define MBOX_WRITE_FC_SERDES_REG 0x0003 /* FC only */
126#define MBOX_READ_FC_SERDES_REG 0x0004 /* FC only */
127#define MBOX_GET_IO_STATUS 0x0012
128#define MBOX_SET_TRANSMIT_PARAMS 0x0019
129#define MBOX_SET_PORT_PARAMS 0x001a
130#define MBOX_LOAD_OP_FW_PARAMS 0x001b
131#define MBOX_INIT_MULTIPLE_QUEUE 0x001f
132#define MBOX_GET_LOOP_ID 0x0020
133/* for 24XX cards, outgoing mailbox 7 has these values for F or FL topologies */
134#define ISP24XX_INORDER 0x0100
135#define ISP24XX_NPIV_SAN 0x0400
136#define ISP24XX_VSAN_SAN 0x1000
137#define ISP24XX_FC_SP_SAN 0x2000
138#define MBOX_GET_TIMEOUT_PARAMS 0x0022
139#define MBOX_GET_FIRMWARE_OPTIONS 0x0028
140#define MBOX_GENERATE_SYSTEM_ERROR 0x002a
141#define MBOX_WRITE_SFP 0x0030
142#define MBOX_READ_SFP 0x0031
143#define MBOX_SET_TIMEOUT_PARAMS 0x0032
144#define MBOX_SET_FIRMWARE_OPTIONS 0x0038
145#define MBOX_GET_SET_FC_LED_CONF 0x003b
146#define MBOX_RESTART_NIC_FIRMWARE 0x003d /* FCoE only */
147#define MBOX_ACCESS_CONTROL 0x003e
148#define MBOX_LOOP_PORT_BYPASS 0x0040 /* FC only */
149#define MBOX_LOOP_PORT_ENABLE 0x0041 /* FC only */
150#define MBOX_GET_RESOURCE_COUNT 0x0042
151#define MBOX_REQUEST_OFFLINE_MODE 0x0043
152#define MBOX_DIAGNOSTIC_ECHO_TEST 0x0044
153#define MBOX_DIAGNOSTIC_LOOPBACK 0x0045
154#define MBOX_ENHANCED_GET_PDB 0x0047
155#define MBOX_INIT_FIRMWARE_MULTI_ID 0x0048 /* 2400 only */
156#define MBOX_GET_VP_DATABASE 0x0049 /* 2400 only */
157#define MBOX_GET_VP_DATABASE_ENTRY 0x004a /* 2400 only */
158#define MBOX_GET_FCF_LIST 0x0050 /* FCoE only */
159#define MBOX_GET_DCBX_PARAMETERS 0x0051 /* FCoE only */
160#define MBOX_HOST_MEMORY_COPY 0x0053
161#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054
162#define MBOX_SEND_RNID 0x0057
163#define MBOX_SET_PARAMETERS 0x0059
164#define MBOX_GET_PARAMETERS 0x005a
165#define MBOX_DRIVER_HEARTBEAT 0x005B /* FC only */
166#define MBOX_FW_HEARTBEAT 0x005C
167#define MBOX_GET_SET_DATA_RATE 0x005D /* >=23XX only */
168#define MBGSD_GET_RATE 0
169#define MBGSD_SET_RATE 1
170#define MBGSD_SET_RATE_NOW 2 /* 24XX only */
171#define MBGSD_1GB 0x00
172#define MBGSD_2GB 0x01
173#define MBGSD_AUTO 0x02
174#define MBGSD_4GB 0x03 /* 24XX only */
175#define MBGSD_8GB 0x04 /* 25XX only */
176#define MBGSD_16GB 0x05 /* 26XX only */
177#define MBGSD_10GB 0x13 /* 26XX only */
178#define MBOX_SEND_RNFT 0x005e
179#define MBOX_INIT_FIRMWARE 0x0060
180#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061
181#define MBOX_INIT_LIP 0x0062
182#define MBOX_GET_FC_AL_POSITION_MAP 0x0063
183#define MBOX_GET_PORT_DB 0x0064
184#define MBOX_CLEAR_ACA 0x0065
185#define MBOX_TARGET_RESET 0x0066
186#define MBOX_CLEAR_TASK_SET 0x0067
187#define MBOX_ABORT_TASK_SET 0x0068
188#define MBOX_GET_FW_STATE 0x0069
189#define MBOX_GET_PORT_NAME 0x006A
190#define MBOX_GET_LINK_STATUS 0x006B
191#define MBOX_INIT_LIP_RESET 0x006C
192#define MBOX_GET_LINK_STAT_PR_DATA_CNT 0x006D
193#define MBOX_SEND_SNS 0x006E
194#define MBOX_FABRIC_LOGIN 0x006F
195#define MBOX_SEND_CHANGE_REQUEST 0x0070
196#define MBOX_FABRIC_LOGOUT 0x0071
197#define MBOX_INIT_LIP_LOGIN 0x0072
198#define MBOX_GET_PORT_NODE_NAME_LIST 0x0075
199#define MBOX_SET_VENDOR_ID 0x0076
200#define MBOX_GET_XGMAC_STATS 0x007a
201#define MBOX_GET_ID_LIST 0x007C
202#define MBOX_SEND_LFA 0x007d
203#define MBOX_LUN_RESET 0x007E
204
205#define ISP2100_SET_PCI_PARAM 0x00ff
206
207#define MBOX_BUSY 0x04
208
209/*
210 * Mailbox Command Complete Status Codes
211 */
212#define MBOX_COMMAND_COMPLETE 0x4000
213#define MBOX_INVALID_COMMAND 0x4001
214#define MBOX_HOST_INTERFACE_ERROR 0x4002
215#define MBOX_TEST_FAILED 0x4003
216#define MBOX_COMMAND_ERROR 0x4005
217#define MBOX_COMMAND_PARAM_ERROR 0x4006
218#define MBOX_PORT_ID_USED 0x4007
219#define MBOX_LOOP_ID_USED 0x4008
220#define MBOX_ALL_IDS_USED 0x4009
221#define MBOX_NOT_LOGGED_IN 0x400A
222#define MBOX_LINK_DOWN_ERROR 0x400B
223#define MBOX_LOOPBACK_ERROR 0x400C
224#define MBOX_CHECKSUM_ERROR 0x4010
225#define MBOX_INVALID_PRODUCT_KEY 0x4020
226/* pseudo mailbox completion codes */
227#define MBOX_REGS_BUSY 0x6000 /* registers in use */
228#define MBOX_TIMEOUT 0x6001 /* command timed out */
229
230#define MBLOGALL 0xffffffff
231#define MBLOGNONE 0x00000000
232#define MBLOGMASK(x) (1 << (((x) - 1) & 0x1f))
233
234/*
235 * Asynchronous event status codes
236 */
237#define ASYNC_BUS_RESET 0x8001
238#define ASYNC_SYSTEM_ERROR 0x8002
239#define ASYNC_RQS_XFER_ERR 0x8003
240#define ASYNC_RSP_XFER_ERR 0x8004
241#define ASYNC_QWAKEUP 0x8005
242#define ASYNC_TIMEOUT_RESET 0x8006
243#define ASYNC_DEVICE_RESET 0x8007
244#define ASYNC_EXTMSG_UNDERRUN 0x800A
245#define ASYNC_SCAM_INT 0x800B
246#define ASYNC_HUNG_SCSI 0x800C
247#define ASYNC_KILLED_BUS 0x800D
248#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
249#define ASYNC_LIP_OCCURRED 0x8010
250#define ASYNC_LOOP_UP 0x8011
251#define ASYNC_LOOP_DOWN 0x8012
252#define ASYNC_LOOP_RESET 0x8013
253#define ASYNC_PDB_CHANGED 0x8014
254#define ASYNC_CHANGE_NOTIFY 0x8015
255#define ASYNC_LIP_F8 0x8016
256#define ASYNC_LIP_ERROR 0x8017
257#define ASYNC_SECURITY_UPDATE 0x801B
258#define ASYNC_CMD_CMPLT 0x8020
259#define ASYNC_CTIO_DONE 0x8021
260#define ASYNC_RIO32_1 0x8021
261#define ASYNC_RIO32_2 0x8022
262#define ASYNC_IP_XMIT_DONE 0x8022
263#define ASYNC_IP_RECV_DONE 0x8023
264#define ASYNC_IP_BROADCAST 0x8024
265#define ASYNC_IP_RCVQ_LOW 0x8025
266#define ASYNC_IP_RCVQ_EMPTY 0x8026
267#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027
268#define ASYNC_PTPMODE 0x8030
269#define ASYNC_RIO16_1 0x8031
270#define ASYNC_RIO16_2 0x8032
271#define ASYNC_RIO16_3 0x8033
272#define ASYNC_RIO16_4 0x8034
273#define ASYNC_RIO16_5 0x8035
274#define ASYNC_CONNMODE 0x8036
275#define ISP_CONN_LOOP 1
276#define ISP_CONN_PTP 2
277#define ISP_CONN_BADLIP 3
278#define ISP_CONN_FATAL 4
279#define ISP_CONN_LOOPBACK 5
280#define ASYNC_RIOZIO_STALL 0x8040 /* there's a RIO/ZIO entry that hasn't been serviced */
281#define ASYNC_RIO32_2_2200 0x8042 /* same as ASYNC_RIO32_2, but for 2100/2200 */
282#define ASYNC_RCV_ERR 0x8048
283
284/*
285 * Firmware Options. There are a lot of them.
286 *
287 * IFCOPTN - ISP Fibre Channel Option Word N
288 */
289#define IFCOPT1_EQFQASYNC (1 << 13) /* enable QFULL notification */
290#define IFCOPT1_EAABSRCVD (1 << 12)
291#define IFCOPT1_RJTASYNC (1 << 11) /* enable 8018 notification */
292#define IFCOPT1_ENAPURE (1 << 10)
293#define IFCOPT1_ENA8017 (1 << 7)
294#define IFCOPT1_DISGPIO67 (1 << 6)
295#define IFCOPT1_LIPLOSSIMM (1 << 5)
296#define IFCOPT1_DISF7SWTCH (1 << 4)
297#define IFCOPT1_CTIO_RETRY (1 << 3)
298#define IFCOPT1_LIPASYNC (1 << 1)
299#define IFCOPT1_LIPF8 (1 << 0)
300
301#define IFCOPT2_LOOPBACK (1 << 1)
302#define IFCOPT2_ATIO3_ONLY (1 << 0)
303
304#define IFCOPT3_NOPRLI (1 << 4) /* disable automatic sending of PRLI on local loops */
305#define IFCOPT3_RNDASYNC (1 << 1)
306/*
307 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
308 * mailbox command to enable this.
309 */
310#define ASYNC_QFULL_SENT 0x8049
311
312/*
313 * Needs to be enabled
314 */
315#define ASYNC_AUTO_PLOGI_RJT 0x8018
316/*
317 * 24XX only
318 */
319#define ASYNC_RJT_SENT 0x8049
320
321/*
322 * All IOCB Queue entries are this size
323 */
324#define QENTRY_LEN 64
325
326/*
327 * Command Structure Definitions
328 */
329
330typedef struct {
331 uint32_t ds_base;
332 uint32_t ds_count;
333} ispds_t;
334
335typedef struct {
336 uint32_t ds_base;
337 uint32_t ds_basehi;
338 uint32_t ds_count;
339} ispds64_t;
340
341#define DSTYPE_32BIT 0
342#define DSTYPE_64BIT 1
343typedef struct {
344 uint16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */
345 uint32_t ds_segment; /* unused */
346 uint32_t ds_base; /* 32 bit address of DSD list */
347} ispdslist_t;
348
349
350typedef struct {
351 uint8_t rqs_entry_type;
352 uint8_t rqs_entry_count;
353 uint8_t rqs_seqno;
354 uint8_t rqs_flags;
355} isphdr_t;
356
357/* RQS Flag definitions */
358#define RQSFLAG_CONTINUATION 0x01
359#define RQSFLAG_FULL 0x02
360#define RQSFLAG_BADHEADER 0x04
361#define RQSFLAG_BADPACKET 0x08
362#define RQSFLAG_BADCOUNT 0x10
363#define RQSFLAG_BADORDER 0x20
364#define RQSFLAG_MASK 0x3f
365
366/* RQS entry_type definitions */
367#define RQSTYPE_REQUEST 0x01
368#define RQSTYPE_DATASEG 0x02
369#define RQSTYPE_RESPONSE 0x03
370#define RQSTYPE_MARKER 0x04
371#define RQSTYPE_CMDONLY 0x05
372#define RQSTYPE_ATIO 0x06 /* Target Mode */
373#define RQSTYPE_CTIO 0x07 /* Target Mode */
374#define RQSTYPE_SCAM 0x08
375#define RQSTYPE_A64 0x09
376#define RQSTYPE_A64_CONT 0x0a
377#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
378#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
379#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
380#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
381#define RQSTYPE_CTIO1 0x0f /* Target Mode */
382#define RQSTYPE_STATUS_CONT 0x10
383#define RQSTYPE_T2RQS 0x11
384#define RQSTYPE_CTIO7 0x12
385#define RQSTYPE_IP_XMIT 0x13
386#define RQSTYPE_TSK_MGMT 0x14
387#define RQSTYPE_T4RQS 0x15
388#define RQSTYPE_ATIO2 0x16 /* Target Mode */
389#define RQSTYPE_CTIO2 0x17 /* Target Mode */
390#define RQSTYPE_T7RQS 0x18
391#define RQSTYPE_T3RQS 0x19
392#define RQSTYPE_IP_XMIT_64 0x1b
393#define RQSTYPE_CTIO4 0x1e /* Target Mode */
394#define RQSTYPE_CTIO3 0x1f /* Target Mode */
395#define RQSTYPE_RIO1 0x21
396#define RQSTYPE_RIO2 0x22
397#define RQSTYPE_IP_RECV 0x23
398#define RQSTYPE_IP_RECV_CONT 0x24
399#define RQSTYPE_CT_PASSTHRU 0x29
400#define RQSTYPE_MS_PASSTHRU 0x29
401#define RQSTYPE_VP_CTRL 0x30 /* 24XX only */
402#define RQSTYPE_VP_MODIFY 0x31 /* 24XX only */
403#define RQSTYPE_RPT_ID_ACQ 0x32 /* 24XX only */
404#define RQSTYPE_ABORT_IO 0x33
405#define RQSTYPE_T6RQS 0x48
406#define RQSTYPE_LOGIN 0x52
407#define RQSTYPE_ABTS_RCVD 0x54 /* 24XX only */
408#define RQSTYPE_ABTS_RSP 0x55 /* 24XX only */
409
410
411#define ISP_RQDSEG 4
412typedef struct {
413 isphdr_t req_header;
414 uint32_t req_handle;
415 uint8_t req_lun_trn;
416 uint8_t req_target;
417 uint16_t req_cdblen;
418 uint16_t req_flags;
419 uint16_t req_reserved;
420 uint16_t req_time;
421 uint16_t req_seg_count;
422 uint8_t req_cdb[12];
423 ispds_t req_dataseg[ISP_RQDSEG];
424} ispreq_t;
425#define ISP_RQDSEG_A64 2
426
427typedef struct {
428 isphdr_t mrk_header;
429 uint32_t mrk_handle;
430 uint8_t mrk_reserved0;
431 uint8_t mrk_target;
432 uint16_t mrk_modifier;
433 uint16_t mrk_flags;
434 uint16_t mrk_lun;
435 uint8_t mrk_reserved1[48];
436} isp_marker_t;
437
438typedef struct {
439 isphdr_t mrk_header;
440 uint32_t mrk_handle;
441 uint16_t mrk_nphdl;
442 uint8_t mrk_modifier;
443 uint8_t mrk_reserved0;
444 uint8_t mrk_reserved1;
445 uint8_t mrk_vphdl;
446 uint16_t mrk_reserved2;
447 uint8_t mrk_lun[8];
448 uint8_t mrk_reserved3[40];
449} isp_marker_24xx_t;
450
451
452#define SYNC_DEVICE 0
453#define SYNC_TARGET 1
454#define SYNC_ALL 2
455#define SYNC_LIP 3
456
457#define ISP_RQDSEG_T2 3
458typedef struct {
459 isphdr_t req_header;
460 uint32_t req_handle;
461 uint8_t req_lun_trn;
462 uint8_t req_target;
463 uint16_t req_scclun;
464 uint16_t req_flags;
465 uint8_t req_crn;
466 uint8_t req_reserved;
467 uint16_t req_time;
468 uint16_t req_seg_count;
469 uint8_t req_cdb[16];
470 uint32_t req_totalcnt;
471 ispds_t req_dataseg[ISP_RQDSEG_T2];
472} ispreqt2_t;
473
474typedef struct {
475 isphdr_t req_header;
476 uint32_t req_handle;
477 uint16_t req_target;
478 uint16_t req_scclun;
479 uint16_t req_flags;
480 uint16_t req_reserved;
481 uint16_t req_time;
482 uint16_t req_seg_count;
483 uint8_t req_cdb[16];
484 uint32_t req_totalcnt;
485 ispds_t req_dataseg[ISP_RQDSEG_T2];
486} ispreqt2e_t;
487
488#define ISP_RQDSEG_T3 2
489typedef struct {
490 isphdr_t req_header;
491 uint32_t req_handle;
492 uint8_t req_lun_trn;
493 uint8_t req_target;
494 uint16_t req_scclun;
495 uint16_t req_flags;
496 uint8_t req_crn;
497 uint8_t req_reserved;
498 uint16_t req_time;
499 uint16_t req_seg_count;
500 uint8_t req_cdb[16];
501 uint32_t req_totalcnt;
502 ispds64_t req_dataseg[ISP_RQDSEG_T3];
503} ispreqt3_t;
504#define ispreq64_t ispreqt3_t /* same as.... */
505
506typedef struct {
507 isphdr_t req_header;
508 uint32_t req_handle;
509 uint16_t req_target;
510 uint16_t req_scclun;
511 uint16_t req_flags;
512 uint8_t req_crn;
513 uint8_t req_reserved;
514 uint16_t req_time;
515 uint16_t req_seg_count;
516 uint8_t req_cdb[16];
517 uint32_t req_totalcnt;
518 ispds64_t req_dataseg[ISP_RQDSEG_T3];
519} ispreqt3e_t;
520
521/* req_flag values */
522#define REQFLAG_NODISCON 0x0001
523#define REQFLAG_HTAG 0x0002
524#define REQFLAG_OTAG 0x0004
525#define REQFLAG_STAG 0x0008
526#define REQFLAG_TARGET_RTN 0x0010
527
528#define REQFLAG_NODATA 0x0000
529#define REQFLAG_DATA_IN 0x0020
530#define REQFLAG_DATA_OUT 0x0040
531#define REQFLAG_DATA_UNKNOWN 0x0060
532
533#define REQFLAG_DISARQ 0x0100
534#define REQFLAG_FRC_ASYNC 0x0200
535#define REQFLAG_FRC_SYNC 0x0400
536#define REQFLAG_FRC_WIDE 0x0800
537#define REQFLAG_NOPARITY 0x1000
538#define REQFLAG_STOPQ 0x2000
539#define REQFLAG_XTRASNS 0x4000
540#define REQFLAG_PRIORITY 0x8000
541
542typedef struct {
543 isphdr_t req_header;
544 uint32_t req_handle;
545 uint8_t req_lun_trn;
546 uint8_t req_target;
547 uint16_t req_cdblen;
548 uint16_t req_flags;
549 uint16_t req_reserved;
550 uint16_t req_time;
551 uint16_t req_seg_count;
552 uint8_t req_cdb[44];
553} ispextreq_t;
554
555
556/*
557 * ISP24XX structures
558 */
559typedef struct {
560 isphdr_t req_header;
561 uint32_t req_handle;
562 uint16_t req_nphdl;
563 uint16_t req_time;
564 uint16_t req_seg_count;
565 uint16_t req_reserved;
566 uint8_t req_lun[8];
567 uint8_t req_alen_datadir;
568 uint8_t req_task_management;
569 uint8_t req_task_attribute;
570 uint8_t req_crn;
571 uint8_t req_cdb[16];
572 uint32_t req_dl;
573 uint16_t req_tidlo;
574 uint8_t req_tidhi;
575 uint8_t req_vpidx;
576 ispds64_t req_dataseg;
577} ispreqt7_t;
578
579/* Task Management Request Function */
580typedef struct {
581 isphdr_t tmf_header;
582 uint32_t tmf_handle;
583 uint16_t tmf_nphdl;
584 uint8_t tmf_reserved0[2];
585 uint16_t tmf_delay;
586 uint16_t tmf_timeout;
587 uint8_t tmf_lun[8];
588 uint32_t tmf_flags;
589 uint8_t tmf_reserved1[20];
590 uint16_t tmf_tidlo;
591 uint8_t tmf_tidhi;
592 uint8_t tmf_vpidx;
593 uint8_t tmf_reserved2[12];
594} isp24xx_tmf_t;
595
596#define ISP24XX_TMF_NOSEND 0x80000000
597
598#define ISP24XX_TMF_LUN_RESET 0x00000010
599#define ISP24XX_TMF_ABORT_TASK_SET 0x00000008
600#define ISP24XX_TMF_CLEAR_TASK_SET 0x00000004
601#define ISP24XX_TMF_TARGET_RESET 0x00000002
602#define ISP24XX_TMF_CLEAR_ACA 0x00000001
603
604/* I/O Abort Structure */
605typedef struct {
606 isphdr_t abrt_header;
607 uint32_t abrt_handle;
608 uint16_t abrt_nphdl;
609 uint16_t abrt_options;
610 uint32_t abrt_cmd_handle;
611 uint16_t abrt_queue_number;
612 uint8_t abrt_reserved[30];
613 uint16_t abrt_tidlo;
614 uint8_t abrt_tidhi;
615 uint8_t abrt_vpidx;
616 uint8_t abrt_reserved1[12];
617} isp24xx_abrt_t;
618
619#define ISP24XX_ABRT_NOSEND 0x01 /* don't actually send ABTS */
620#define ISP24XX_ABRT_OKAY 0x00 /* in nphdl on return */
621#define ISP24XX_ABRT_ENXIO 0x31 /* in nphdl on return */
622
623#define ISP_CDSEG 7
624typedef struct {
625 isphdr_t req_header;
626 uint32_t req_reserved;
627 ispds_t req_dataseg[ISP_CDSEG];
628} ispcontreq_t;
629
630#define ISP_CDSEG64 5
631typedef struct {
632 isphdr_t req_header;
633 ispds64_t req_dataseg[ISP_CDSEG64];
634} ispcontreq64_t;
635
636typedef struct {
637 isphdr_t req_header;
638 uint32_t req_handle;
639 uint16_t req_scsi_status;
640 uint16_t req_completion_status;
641 uint16_t req_state_flags;
642 uint16_t req_status_flags;
643 uint16_t req_time;
644#define req_response_len req_time /* FC only */
645 uint16_t req_sense_len;
646 uint32_t req_resid;
647 uint8_t req_response[8]; /* FC only */
648 uint8_t req_sense_data[32];
649} ispstatusreq_t;
650
651/*
652 * Status Continuation
653 */
654typedef struct {
655 isphdr_t req_header;
656 uint8_t req_sense_data[60];
657} ispstatus_cont_t;
658
659/*
660 * 24XX Type 0 status
661 */
662typedef struct {
663 isphdr_t req_header;
664 uint32_t req_handle;
665 uint16_t req_completion_status;
666 uint16_t req_oxid;
667 uint32_t req_resid;
668 uint16_t req_reserved0;
669 uint16_t req_state_flags;
670 uint16_t req_retry_delay; /* aka Status Qualifier */
671 uint16_t req_scsi_status;
672 uint32_t req_fcp_residual;
673 uint32_t req_sense_len;
674 uint32_t req_response_len;
675 uint8_t req_rsp_sense[28];
676} isp24xx_statusreq_t;
677
678/*
679 * For Qlogic 2X00, the high order byte of SCSI status has
680 * additional meaning.
681 */
682#define RQCS_CR 0x1000 /* Confirmation Request */
683#define RQCS_RU 0x0800 /* Residual Under */
684#define RQCS_RO 0x0400 /* Residual Over */
685#define RQCS_RESID (RQCS_RU|RQCS_RO)
686#define RQCS_SV 0x0200 /* Sense Length Valid */
687#define RQCS_RV 0x0100 /* FCP Response Length Valid */
688
689/*
690 * CT Passthru IOCB
691 */
692typedef struct {
693 isphdr_t ctp_header;
694 uint32_t ctp_handle;
695 uint16_t ctp_status;
696 uint16_t ctp_nphdl; /* n-port handle */
697 uint16_t ctp_cmd_cnt; /* Command DSD count */
698 uint8_t ctp_vpidx;
699 uint8_t ctp_reserved0;
700 uint16_t ctp_time;
701 uint16_t ctp_reserved1;
702 uint16_t ctp_rsp_cnt; /* Response DSD count */
703 uint16_t ctp_reserved2[5];
704 uint32_t ctp_rsp_bcnt; /* Response byte count */
705 uint32_t ctp_cmd_bcnt; /* Command byte count */
706 ispds64_t ctp_dataseg[2];
707} isp_ct_pt_t;
708
709/*
710 * MS Passthru IOCB
711 */
712typedef struct {
713 isphdr_t ms_header;
714 uint32_t ms_handle;
715 uint16_t ms_nphdl; /* handle in high byte for !2k f/w */
716 uint16_t ms_status;
717 uint16_t ms_flags;
718 uint16_t ms_reserved1; /* low 8 bits */
719 uint16_t ms_time;
720 uint16_t ms_cmd_cnt; /* Command DSD count */
721 uint16_t ms_tot_cnt; /* Total DSD Count */
722 uint8_t ms_type; /* MS type */
723 uint8_t ms_r_ctl; /* R_CTL */
724 uint16_t ms_rxid; /* RX_ID */
725 uint16_t ms_reserved2;
726 uint32_t ms_handle2;
727 uint32_t ms_rsp_bcnt; /* Response byte count */
728 uint32_t ms_cmd_bcnt; /* Command byte count */
729 ispds64_t ms_dataseg[2];
730} isp_ms_t;
731
732/*
733 * Completion Status Codes.
734 */
735#define RQCS_COMPLETE 0x0000
736#define RQCS_DMA_ERROR 0x0002
737#define RQCS_RESET_OCCURRED 0x0004
738#define RQCS_ABORTED 0x0005
739#define RQCS_TIMEOUT 0x0006
740#define RQCS_DATA_OVERRUN 0x0007
741#define RQCS_DATA_UNDERRUN 0x0015
742#define RQCS_QUEUE_FULL 0x001C
743
744/* 1X00 Only Completion Codes */
745#define RQCS_INCOMPLETE 0x0001
746#define RQCS_TRANSPORT_ERROR 0x0003
747#define RQCS_COMMAND_OVERRUN 0x0008
748#define RQCS_STATUS_OVERRUN 0x0009
749#define RQCS_BAD_MESSAGE 0x000a
750#define RQCS_NO_MESSAGE_OUT 0x000b
751#define RQCS_EXT_ID_FAILED 0x000c
752#define RQCS_IDE_MSG_FAILED 0x000d
753#define RQCS_ABORT_MSG_FAILED 0x000e
754#define RQCS_REJECT_MSG_FAILED 0x000f
755#define RQCS_NOP_MSG_FAILED 0x0010
756#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
757#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
758#define RQCS_ID_MSG_FAILED 0x0013
759#define RQCS_UNEXP_BUS_FREE 0x0014
760#define RQCS_XACT_ERR1 0x0018
761#define RQCS_XACT_ERR2 0x0019
762#define RQCS_XACT_ERR3 0x001A
763#define RQCS_BAD_ENTRY 0x001B
764#define RQCS_PHASE_SKIPPED 0x001D
765#define RQCS_ARQS_FAILED 0x001E
766#define RQCS_WIDE_FAILED 0x001F
767#define RQCS_SYNCXFER_FAILED 0x0020
768#define RQCS_LVD_BUSERR 0x0021
769
770/* 2X00 Only Completion Codes */
771#define RQCS_PORT_UNAVAILABLE 0x0028
772#define RQCS_PORT_LOGGED_OUT 0x0029
773#define RQCS_PORT_CHANGED 0x002A
774#define RQCS_PORT_BUSY 0x002B
775
776/* 24XX Only Completion Codes */
777#define RQCS_24XX_DRE 0x0011 /* data reassembly error */
778#define RQCS_24XX_TABORT 0x0013 /* aborted by target */
779#define RQCS_24XX_ENOMEM 0x002C /* f/w resource unavailable */
780#define RQCS_24XX_TMO 0x0030 /* task management overrun */
781
782
783/*
784 * 1X00 specific State Flags
785 */
786#define RQSF_GOT_BUS 0x0100
787#define RQSF_GOT_TARGET 0x0200
788#define RQSF_SENT_CDB 0x0400
789#define RQSF_XFRD_DATA 0x0800
790#define RQSF_GOT_STATUS 0x1000
791#define RQSF_GOT_SENSE 0x2000
792#define RQSF_XFER_COMPLETE 0x4000
793
794/*
795 * 2X00 specific State Flags
796 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
797 */
798#define RQSF_DATA_IN 0x0020
799#define RQSF_DATA_OUT 0x0040
800#define RQSF_STAG 0x0008
801#define RQSF_OTAG 0x0004
802#define RQSF_HTAG 0x0002
803/*
804 * 1X00 Status Flags
805 */
806#define RQSTF_DISCONNECT 0x0001
807#define RQSTF_SYNCHRONOUS 0x0002
808#define RQSTF_PARITY_ERROR 0x0004
809#define RQSTF_BUS_RESET 0x0008
810#define RQSTF_DEVICE_RESET 0x0010
811#define RQSTF_ABORTED 0x0020
812#define RQSTF_TIMEOUT 0x0040
813#define RQSTF_NEGOTIATION 0x0080
814
815/*
816 * 2X00 specific state flags
817 */
818/* RQSF_SENT_CDB */
819/* RQSF_XFRD_DATA */
820/* RQSF_GOT_STATUS */
821/* RQSF_XFER_COMPLETE */
822
823/*
824 * 2X00 specific status flags
825 */
826/* RQSTF_ABORTED */
827/* RQSTF_TIMEOUT */
828#define RQSTF_DMA_ERROR 0x0080
829#define RQSTF_LOGOUT 0x2000
830
831/*
832 * Miscellaneous
833 */
834#ifndef ISP_EXEC_THROTTLE
835#define ISP_EXEC_THROTTLE 16
836#endif
837
838/*
839 * About Firmware returns an 'attribute' word in mailbox 6.
840 * These attributes are for 2200 and 2300.
841 */
842#define ISP_FW_ATTR_TMODE 0x0001
843#define ISP_FW_ATTR_SCCLUN 0x0002
844#define ISP_FW_ATTR_FABRIC 0x0004
845#define ISP_FW_ATTR_CLASS2 0x0008
846#define ISP_FW_ATTR_FCTAPE 0x0010
847#define ISP_FW_ATTR_IP 0x0020
848#define ISP_FW_ATTR_VI 0x0040
849#define ISP_FW_ATTR_VI_SOLARIS 0x0080
850#define ISP_FW_ATTR_2KLOGINS 0x0100 /* just a guess... */
851
852/* and these are for the 2400 */
853#define ISP2400_FW_ATTR_CLASS2 0x0001
854#define ISP2400_FW_ATTR_IP 0x0002
855#define ISP2400_FW_ATTR_MULTIID 0x0004
856#define ISP2400_FW_ATTR_SB2 0x0008
857#define ISP2400_FW_ATTR_T10CRC 0x0010
858#define ISP2400_FW_ATTR_VI 0x0020
859#define ISP2400_FW_ATTR_MQ 0x0040
860#define ISP2400_FW_ATTR_MSIX 0x0080
861#define ISP2400_FW_ATTR_FCOE 0x0800
862#define ISP2400_FW_ATTR_VP0 0x1000
863#define ISP2400_FW_ATTR_EXPFW 0x2000
864#define ISP2400_FW_ATTR_HOTFW 0x4000
865#define ISP2400_FW_ATTR_EXTNDED 0x8000
866#define ISP2400_FW_ATTR_EXTVP 0x00010000
867#define ISP2400_FW_ATTR_VN2VN 0x00040000
868#define ISP2400_FW_ATTR_EXMOFF 0x00080000
869#define ISP2400_FW_ATTR_NPMOFF 0x00100000
870#define ISP2400_FW_ATTR_DIFCHOP 0x00400000
871#define ISP2400_FW_ATTR_SRIOV 0x02000000
872#define ISP2400_FW_ATTR_ASICTMP 0x0200000000
873#define ISP2400_FW_ATTR_ATIOMQ 0x0400000000
874
875/*
876 * These are either manifestly true or are dependent on f/w attributes
877 */
878#define ISP_CAP_TMODE(isp) \
879 (IS_24XX(isp)? 1 : (isp->isp_fwattr & ISP_FW_ATTR_TMODE))
880#define ISP_CAP_SCCFW(isp) \
881 (IS_24XX(isp)? 1 : (isp->isp_fwattr & ISP_FW_ATTR_SCCLUN))
882#define ISP_CAP_2KLOGIN(isp) \
883 (IS_24XX(isp)? 1 : (isp->isp_fwattr & ISP_FW_ATTR_2KLOGINS))
884
885/*
886 * This is only true for 24XX cards with this f/w attribute
887 */
888#define ISP_CAP_MULTI_ID(isp) \
889 (IS_24XX(isp)? (isp->isp_fwattr & ISP2400_FW_ATTR_MULTIID) : 0)
890#define ISP_GET_VPIDX(isp, tag) \
891 (ISP_CAP_MULTI_ID(isp) ? tag : 0)
892#define ISP_CAP_VP0(isp) \
893 (IS_24XX(isp)? (isp->isp_fwattr & ISP2400_FW_ATTR_VP0) : 0)
894
895/*
896 * This is true manifestly or is dependent on a f/w attribute
897 * but may or may not actually be *enabled*. In any case, it
898 * is enabled on a per-channel basis.
899 */
900#define ISP_CAP_FCTAPE(isp) \
901 (IS_24XX(isp)? 1 : (isp->isp_fwattr & ISP_FW_ATTR_FCTAPE))
902
903#define ISP_FCTAPE_ENABLED(isp, chan) \
904 (IS_24XX(isp)? (FCPARAM(isp, chan)->isp_xfwoptions & ICB2400_OPT2_FCTAPE) != 0 : (FCPARAM(isp, chan)->isp_xfwoptions & ICBXOPT_FCTAPE) != 0)
905
906/*
907 * Reduced Interrupt Operation Response Queue Entries
908 */
909
910typedef struct {
911 isphdr_t req_header;
912 uint32_t req_handles[15];
913} isp_rio1_t;
914
915typedef struct {
916 isphdr_t req_header;
917 uint16_t req_handles[30];
918} isp_rio2_t;
919
920/*
921 * FC (ISP2100/ISP2200/ISP2300/ISP2400) specific data structures
922 */
923
924/*
925 * Initialization Control Block
926 *
927 * Version One (prime) format.
928 */
929typedef struct {
930 uint8_t icb_version;
931 uint8_t icb_reserved0;
932 uint16_t icb_fwoptions;
933 uint16_t icb_maxfrmlen;
934 uint16_t icb_maxalloc;
935 uint16_t icb_execthrottle;
936 uint8_t icb_retry_count;
937 uint8_t icb_retry_delay;
938 uint8_t icb_portname[8];
939 uint16_t icb_hardaddr;
940 uint8_t icb_iqdevtype;
941 uint8_t icb_logintime;
942 uint8_t icb_nodename[8];
943 uint16_t icb_rqstout;
944 uint16_t icb_rspnsin;
945 uint16_t icb_rqstqlen;
946 uint16_t icb_rsltqlen;
947 uint16_t icb_rqstaddr[4];
948 uint16_t icb_respaddr[4];
949 uint16_t icb_lunenables;
950 uint8_t icb_ccnt;
951 uint8_t icb_icnt;
952 uint16_t icb_lunetimeout;
953 uint16_t icb_reserved1;
954 uint16_t icb_xfwoptions;
955 uint8_t icb_racctimer;
956 uint8_t icb_idelaytimer;
957 uint16_t icb_zfwoptions;
958 uint16_t icb_reserved2[13];
959} isp_icb_t;
960
961#define ICB_VERSION1 1
962
963#define ICBOPT_EXTENDED 0x8000
964#define ICBOPT_BOTH_WWNS 0x4000
965#define ICBOPT_FULL_LOGIN 0x2000
966#define ICBOPT_STOP_ON_QFULL 0x1000 /* 2200/2100 only */
967#define ICBOPT_PREV_ADDRESS 0x0800
968#define ICBOPT_SRCHDOWN 0x0400
969#define ICBOPT_NOLIP 0x0200
970#define ICBOPT_PDBCHANGE_AE 0x0100
971#define ICBOPT_TGT_TYPE 0x0080
972#define ICBOPT_INI_ADISC 0x0040
973#define ICBOPT_INI_DISABLE 0x0020
974#define ICBOPT_TGT_ENABLE 0x0010
975#define ICBOPT_FAST_POST 0x0008
976#define ICBOPT_FULL_DUPLEX 0x0004
977#define ICBOPT_FAIRNESS 0x0002
978#define ICBOPT_HARD_ADDRESS 0x0001
979
980#define ICBXOPT_NO_LOGOUT 0x8000 /* no logout on link failure */
981#define ICBXOPT_FCTAPE_CCQ 0x4000 /* FC-Tape Command Queueing */
982#define ICBXOPT_FCTAPE_CONFIRM 0x2000
983#define ICBXOPT_FCTAPE 0x1000
984#define ICBXOPT_CLASS2_ACK0 0x0200
985#define ICBXOPT_CLASS2 0x0100
986#define ICBXOPT_NO_PLAY 0x0080 /* don't play if can't get hard addr */
987#define ICBXOPT_TOPO_MASK 0x0070
988#define ICBXOPT_LOOP_ONLY 0x0000
989#define ICBXOPT_PTP_ONLY 0x0010
990#define ICBXOPT_LOOP_2_PTP 0x0020
991#define ICBXOPT_PTP_2_LOOP 0x0030
992/*
993 * The lower 4 bits of the xfwoptions field are the OPERATION MODE bits.
994 * RIO is not defined for the 23XX cards (just 2200)
995 */
996#define ICBXOPT_RIO_OFF 0
997#define ICBXOPT_RIO_16BIT 1
998#define ICBXOPT_RIO_32BIT 2
999#define ICBXOPT_RIO_16BIT_IOCB 3
1000#define ICBXOPT_RIO_32BIT_IOCB 4
1001#define ICBXOPT_ZIO 5
1002#define ICBXOPT_TIMER_MASK 0x7
1003
1004#define ICBZOPT_RATE_MASK 0xC000
1005#define ICBZOPT_RATE_ONEGB 0x0000
1006#define ICBZOPT_RATE_AUTO 0x8000
1007#define ICBZOPT_RATE_TWOGB 0x4000
1008#define ICBZOPT_50_OHM 0x2000
1009#define ICBZOPT_ENA_OOF 0x0040 /* out of order frame handling */
1010#define ICBZOPT_RSPSZ_MASK 0x0030
1011#define ICBZOPT_RSPSZ_24 0x0000
1012#define ICBZOPT_RSPSZ_12 0x0010
1013#define ICBZOPT_RSPSZ_24A 0x0020
1014#define ICBZOPT_RSPSZ_32 0x0030
1015#define ICBZOPT_SOFTID 0x0002
1016#define ICBZOPT_ENA_RDXFR_RDY 0x0001
1017
1018/* 2400 F/W options */
1019#define ICB2400_OPT1_BOTH_WWNS 0x00004000
1020#define ICB2400_OPT1_FULL_LOGIN 0x00002000
1021#define ICB2400_OPT1_PREV_ADDRESS 0x00000800
1022#define ICB2400_OPT1_SRCHDOWN 0x00000400
1023#define ICB2400_OPT1_NOLIP 0x00000200
1024#define ICB2400_OPT1_INI_DISABLE 0x00000020
1025#define ICB2400_OPT1_TGT_ENABLE 0x00000010
1026#define ICB2400_OPT1_FULL_DUPLEX 0x00000004
1027#define ICB2400_OPT1_FAIRNESS 0x00000002
1028#define ICB2400_OPT1_HARD_ADDRESS 0x00000001
1029
1030#define ICB2400_OPT2_ENA_ATIOMQ 0x08000000
1031#define ICB2400_OPT2_ENA_IHA 0x04000000
1032#define ICB2400_OPT2_QOS 0x02000000
1033#define ICB2400_OPT2_IOCBS 0x01000000
1034#define ICB2400_OPT2_ENA_IHR 0x00400000
1035#define ICB2400_OPT2_ENA_VMS 0x00200000
1036#define ICB2400_OPT2_ENA_TA 0x00100000
1037#define ICB2400_OPT2_TPRLIC 0x00004000
1038#define ICB2400_OPT2_FCTAPE 0x00001000
1039#define ICB2400_OPT2_FCSP 0x00000800
1040#define ICB2400_OPT2_CLASS2_ACK0 0x00000200
1041#define ICB2400_OPT2_CLASS2 0x00000100
1042#define ICB2400_OPT2_NO_PLAY 0x00000080
1043#define ICB2400_OPT2_TOPO_MASK 0x00000070
1044#define ICB2400_OPT2_LOOP_ONLY 0x00000000
1045#define ICB2400_OPT2_PTP_ONLY 0x00000010
1046#define ICB2400_OPT2_LOOP_2_PTP 0x00000020
1047#define ICB2400_OPT2_TIMER_MASK 0x0000000f
1048#define ICB2400_OPT2_ZIO 0x00000005
1049#define ICB2400_OPT2_ZIO1 0x00000006
1050
1051#define ICB2400_OPT3_NO_CTXDIS 0x40000000
1052#define ICB2400_OPT3_ENA_ETH_RESP 0x08000000
1053#define ICB2400_OPT3_ENA_ETH_ATIO 0x04000000
1054#define ICB2400_OPT3_ENA_MFCF 0x00020000
1055#define ICB2400_OPT3_SKIP_FOURGB 0x00010000
1056#define ICB2400_OPT3_RATE_MASK 0x0000E000
1057#define ICB2400_OPT3_RATE_ONEGB 0x00000000
1058#define ICB2400_OPT3_RATE_TWOGB 0x00002000
1059#define ICB2400_OPT3_RATE_AUTO 0x00004000
1060#define ICB2400_OPT3_RATE_FOURGB 0x00006000
1061#define ICB2400_OPT3_RATE_EIGHTGB 0x00008000
1062#define ICB2400_OPT3_RATE_SIXTEENGB 0x0000A000
1063#define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200
1064#define ICB2400_OPT3_NO_N2N_LOGI 0x00000100
1065#define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080
1066#define ICB2400_OPT3_ENA_OOF 0x00000040
1067/* note that a response size flag of zero is reserved! */
1068#define ICB2400_OPT3_RSPSZ_MASK 0x00000030
1069#define ICB2400_OPT3_RSPSZ_12 0x00000010
1070#define ICB2400_OPT3_RSPSZ_24 0x00000020
1071#define ICB2400_OPT3_RSPSZ_32 0x00000030
1072#define ICB2400_OPT3_SOFTID 0x00000002
1073
1074#define ICB_MIN_FRMLEN 256
1075#define ICB_MAX_FRMLEN 2112
1076#define ICB_DFLT_FRMLEN 1024
1077#define ICB_DFLT_ALLOC 256
1078#define ICB_DFLT_THROTTLE 16
1079#define ICB_DFLT_RDELAY 5
1080#define ICB_DFLT_RCOUNT 3
1081
1082#define ICB_LOGIN_TOV 30
1083#define ICB_LUN_ENABLE_TOV 15
1084
1085
1086/*
1087 * And somebody at QLogic had a great idea that you could just change
1088 * the structure *and* keep the version number the same as the other cards.
1089 */
1090typedef struct {
1091 uint16_t icb_version;
1092 uint16_t icb_reserved0;
1093 uint16_t icb_maxfrmlen;
1094 uint16_t icb_execthrottle;
1095 uint16_t icb_xchgcnt;
1096 uint16_t icb_hardaddr;
1097 uint8_t icb_portname[8];
1098 uint8_t icb_nodename[8];
1099 uint16_t icb_rspnsin;
1100 uint16_t icb_rqstout;
1101 uint16_t icb_retry_count;
1102 uint16_t icb_priout;
1103 uint16_t icb_rsltqlen;
1104 uint16_t icb_rqstqlen;
1105 uint16_t icb_ldn_nols;
1106 uint16_t icb_prqstqlen;
1107 uint16_t icb_rqstaddr[4];
1108 uint16_t icb_respaddr[4];
1109 uint16_t icb_priaddr[4];
1110 uint16_t icb_msixresp;
1111 uint16_t icb_msixatio;
1112 uint16_t icb_reserved1[2];
1113 uint16_t icb_atio_in;
1114 uint16_t icb_atioqlen;
1115 uint16_t icb_atioqaddr[4];
1116 uint16_t icb_idelaytimer;
1117 uint16_t icb_logintime;
1118 uint32_t icb_fwoptions1;
1119 uint32_t icb_fwoptions2;
1120 uint32_t icb_fwoptions3;
1121 uint16_t icb_qos;
1122 uint16_t icb_reserved2[3];
1123 uint16_t icb_enodemac[3];
1124 uint16_t icb_disctime;
1125 uint16_t icb_reserved3[4];
1126} isp_icb_2400_t;
1127
1128#define RQRSP_ADDR0015 0
1129#define RQRSP_ADDR1631 1
1130#define RQRSP_ADDR3247 2
1131#define RQRSP_ADDR4863 3
1132
1133
1134#define ICB_NNM0 7
1135#define ICB_NNM1 6
1136#define ICB_NNM2 5
1137#define ICB_NNM3 4
1138#define ICB_NNM4 3
1139#define ICB_NNM5 2
1140#define ICB_NNM6 1
1141#define ICB_NNM7 0
1142
1143#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
1144 array[ICB_NNM0] = (uint8_t) ((wwn >> 0) & 0xff), \
1145 array[ICB_NNM1] = (uint8_t) ((wwn >> 8) & 0xff), \
1146 array[ICB_NNM2] = (uint8_t) ((wwn >> 16) & 0xff), \
1147 array[ICB_NNM3] = (uint8_t) ((wwn >> 24) & 0xff), \
1148 array[ICB_NNM4] = (uint8_t) ((wwn >> 32) & 0xff), \
1149 array[ICB_NNM5] = (uint8_t) ((wwn >> 40) & 0xff), \
1150 array[ICB_NNM6] = (uint8_t) ((wwn >> 48) & 0xff), \
1151 array[ICB_NNM7] = (uint8_t) ((wwn >> 56) & 0xff)
1152
1153#define MAKE_WWN_FROM_NODE_NAME(wwn, array) \
1154 wwn = ((uint64_t) array[ICB_NNM0]) | \
1155 ((uint64_t) array[ICB_NNM1] << 8) | \
1156 ((uint64_t) array[ICB_NNM2] << 16) | \
1157 ((uint64_t) array[ICB_NNM3] << 24) | \
1158 ((uint64_t) array[ICB_NNM4] << 32) | \
1159 ((uint64_t) array[ICB_NNM5] << 40) | \
1160 ((uint64_t) array[ICB_NNM6] << 48) | \
1161 ((uint64_t) array[ICB_NNM7] << 56)
1162
1163
1164/*
1165 * For MULTI_ID firmware, this describes a
1166 * virtual port entity for getting status.
1167 */
1168typedef struct {
1169 uint16_t vp_port_status;
1170 uint8_t vp_port_options;
1171 uint8_t vp_port_loopid;
1172 uint8_t vp_port_portname[8];
1173 uint8_t vp_port_nodename[8];
1174 uint16_t vp_port_portid_lo; /* not present when trailing icb */
1175 uint16_t vp_port_portid_hi; /* not present when trailing icb */
1176} vp_port_info_t;
1177
1178#define ICB2400_VPOPT_ENA_SNSLOGIN 0x00000040 /* Enable SNS Login and SCR for Virtual Ports */
1179#define ICB2400_VPOPT_TGT_DISABLE 0x00000020 /* Target Mode Disabled */
1180#define ICB2400_VPOPT_INI_ENABLE 0x00000010 /* Initiator Mode Enabled */
1181#define ICB2400_VPOPT_ENABLED 0x00000008 /* VP Enabled */
1182#define ICB2400_VPOPT_NOPLAY 0x00000004 /* ID Not Acquired */
1183#define ICB2400_VPOPT_PREV_ADDRESS 0x00000002 /* Previously Assigned ID */
1184#define ICB2400_VPOPT_HARD_ADDRESS 0x00000001 /* Hard Assigned ID */
1185
1186#define ICB2400_VPOPT_WRITE_SIZE 20
1187
1188/*
1189 * For MULTI_ID firmware, we append this structure
1190 * to the isp_icb_2400_t above, followed by a list
1191 * structures that are *most* of the vp_port_info_t.
1192 */
1193typedef struct {
1194 uint16_t vp_count;
1195 uint16_t vp_global_options;
1196} isp_icb_2400_vpinfo_t;
1197
1198#define ICB2400_VPINFO_OFF 0x80 /* offset from start of ICB */
1199#define ICB2400_VPINFO_PORT_OFF(chan) \
1200 (ICB2400_VPINFO_OFF + \
1201 sizeof (isp_icb_2400_vpinfo_t) + (chan * ICB2400_VPOPT_WRITE_SIZE))
1202
1203#define ICB2400_VPGOPT_FCA 0x01 /* Assume Clean Address bit in FLOGI ACC set (works only in static configurations) */
1204#define ICB2400_VPGOPT_MID_DISABLE 0x02 /* when set, connection mode2 will work with NPIV-capable switched */
1205#define ICB2400_VPGOPT_VP0_DECOUPLE 0x04 /* Allow VP0 decoupling if firmware supports it */
1206#define ICB2400_VPGOPT_SUSP_FDISK 0x10 /* Suspend FDISC for Enabled VPs */
1207#define ICB2400_VPGOPT_GEN_RIDA 0x20 /* Generate RIDA if FLOGI Fails */
1208
1209typedef struct {
1210 isphdr_t vp_ctrl_hdr;
1211 uint32_t vp_ctrl_handle;
1212 uint16_t vp_ctrl_index_fail;
1213 uint16_t vp_ctrl_status;
1214 uint16_t vp_ctrl_command;
1215 uint16_t vp_ctrl_vp_count;
1216 uint16_t vp_ctrl_idmap[16];
1217 uint16_t vp_ctrl_reserved[7];
1218 uint16_t vp_ctrl_fcf_index;
1219} vp_ctrl_info_t;
1220
1221#define VP_CTRL_CMD_ENABLE_VP 0x00
1222#define VP_CTRL_CMD_DISABLE_VP 0x08
1223#define VP_CTRL_CMD_DISABLE_VP_REINIT_LINK 0x09
1224#define VP_CTRL_CMD_DISABLE_VP_LOGO 0x0A
1225#define VP_CTRL_CMD_DISABLE_VP_LOGO_ALL 0x0B
1226
1227/*
1228 * We can use this structure for modifying either one or two VP ports after initialization
1229 */
1230typedef struct {
1231 isphdr_t vp_mod_hdr;
1232 uint32_t vp_mod_hdl;
1233 uint16_t vp_mod_reserved0;
1234 uint16_t vp_mod_status;
1235 uint8_t vp_mod_cmd;
1236 uint8_t vp_mod_cnt;
1237 uint8_t vp_mod_idx0;
1238 uint8_t vp_mod_idx1;
1239 struct {
1240 uint8_t options;
1241 uint8_t loopid;
1242 uint16_t reserved1;
1243 uint8_t wwpn[8];
1244 uint8_t wwnn[8];
1245 } vp_mod_ports[2];
1246 uint8_t vp_mod_reserved2[8];
1247} vp_modify_t;
1248
1249#define VP_STS_OK 0x00
1250#define VP_STS_ERR 0x01
1251#define VP_CNT_ERR 0x02
1252#define VP_GEN_ERR 0x03
1253#define VP_IDX_ERR 0x04
1254#define VP_STS_BSY 0x05
1255
1256#define VP_MODIFY 0x00
1257#define VP_MODIFY_ENA 0x01
1258#define VP_MODIFY_OPT 0x02
1259#define VP_RESUME 0x03
1260
1261/*
1262 * Port Data Base Element
1263 */
1264
1265typedef struct {
1266 uint16_t pdb_options;
1267 uint8_t pdb_mstate;
1268 uint8_t pdb_sstate;
1269 uint8_t pdb_hardaddr_bits[4];
1270 uint8_t pdb_portid_bits[4];
1271 uint8_t pdb_nodename[8];
1272 uint8_t pdb_portname[8];
1273 uint16_t pdb_execthrottle;
1274 uint16_t pdb_exec_count;
1275 uint8_t pdb_retry_count;
1276 uint8_t pdb_retry_delay;
1277 uint16_t pdb_resalloc;
1278 uint16_t pdb_curalloc;
1279 uint16_t pdb_qhead;
1280 uint16_t pdb_qtail;
1281 uint16_t pdb_tl_next;
1282 uint16_t pdb_tl_last;
1283 uint16_t pdb_features; /* PLOGI, Common Service */
1284 uint16_t pdb_pconcurrnt; /* PLOGI, Common Service */
1285 uint16_t pdb_roi; /* PLOGI, Common Service */
1286 uint8_t pdb_target;
1287 uint8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */
1288 uint16_t pdb_rdsiz; /* PLOGI, Class 3 */
1289 uint16_t pdb_ncseq; /* PLOGI, Class 3 */
1290 uint16_t pdb_noseq; /* PLOGI, Class 3 */
1291 uint16_t pdb_labrtflg;
1292 uint16_t pdb_lstopflg;
1293 uint16_t pdb_sqhead;
1294 uint16_t pdb_sqtail;
1295 uint16_t pdb_ptimer;
1296 uint16_t pdb_nxt_seqid;
1297 uint16_t pdb_fcount;
1298 uint16_t pdb_prli_len;
1299 uint16_t pdb_prli_svc0;
1300 uint16_t pdb_prli_svc3;
1301 uint16_t pdb_loopid;
1302 uint16_t pdb_il_ptr;
1303 uint16_t pdb_sl_ptr;
1304} isp_pdb_21xx_t;
1305
1306#define PDB_OPTIONS_XMITTING (1<<11)
1307#define PDB_OPTIONS_LNKXMIT (1<<10)
1308#define PDB_OPTIONS_ABORTED (1<<9)
1309#define PDB_OPTIONS_ADISC (1<<1)
1310
1311#define PDB_STATE_DISCOVERY 0
1312#define PDB_STATE_WDISC_ACK 1
1313#define PDB_STATE_PLOGI 2
1314#define PDB_STATE_PLOGI_ACK 3
1315#define PDB_STATE_PRLI 4
1316#define PDB_STATE_PRLI_ACK 5
1317#define PDB_STATE_LOGGED_IN 6
1318#define PDB_STATE_PORT_UNAVAIL 7
1319#define PDB_STATE_PRLO 8
1320#define PDB_STATE_PRLO_ACK 9
1321#define PDB_STATE_PLOGO 10
1322#define PDB_STATE_PLOG_ACK 11
1323
1324#define SVC3_ROLE_MASK 0x30
1325#define SVC3_ROLE_SHIFT 4
1326
1327#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2])
1328#define BITS2WORD_24XX(x) ((x)[0] << 16 | (x)[1] << 8 | (x)[2])
1329
1330/*
1331 * Port Data Base Element- 24XX cards
1332 */
1333typedef struct {
1334 uint16_t pdb_flags;
1335 uint8_t pdb_curstate;
1336 uint8_t pdb_laststate;
1337 uint8_t pdb_hardaddr_bits[4];
1338 uint8_t pdb_portid_bits[4];
1339#define pdb_nxt_seqid_2400 pdb_portid_bits[3]
1340 uint16_t pdb_retry_timer;
1341 uint16_t pdb_handle;
1342 uint16_t pdb_rcv_dsize;
1343 uint16_t pdb_reserved0;
1344 uint16_t pdb_prli_svc0;
1345 uint16_t pdb_prli_svc3;
1346 uint8_t pdb_portname[8];
1347 uint8_t pdb_nodename[8];
1348 uint8_t pdb_reserved1[24];
1349} isp_pdb_24xx_t;
1350
1351#define PDB2400_TID_SUPPORTED 0x4000
1352#define PDB2400_FC_TAPE 0x0080
1353#define PDB2400_CLASS2_ACK0 0x0040
1354#define PDB2400_FCP_CONF 0x0020
1355#define PDB2400_CLASS2 0x0010
1356#define PDB2400_ADDR_VALID 0x0002
1357
1358#define PDB2400_STATE_PLOGI_PEND 0x03
1359#define PDB2400_STATE_PLOGI_DONE 0x04
1360#define PDB2400_STATE_PRLI_PEND 0x05
1361#define PDB2400_STATE_LOGGED_IN 0x06
1362#define PDB2400_STATE_PORT_UNAVAIL 0x07
1363#define PDB2400_STATE_PRLO_PEND 0x09
1364#define PDB2400_STATE_LOGO_PEND 0x0B
1365
1366/*
1367 * Common elements from the above two structures that are actually useful to us.
1368 */
1369typedef struct {
1370 uint16_t handle;
1371 uint16_t prli_word3;
1372 uint32_t : 8,
1373 portid : 24;
1374 uint8_t portname[8];
1375 uint8_t nodename[8];
1376} isp_pdb_t;
1377
1378/*
1379 * Port/Node Name List Element
1380 */
1381typedef struct {
1382 uint8_t pnnle_name[8];
1383 uint16_t pnnle_handle;
1384 uint16_t pnnle_reserved;
1385} isp_pnnle_t;
1386
1387#define PNNL_OPTIONS_NODE_NAMES (1<<0)
1388#define PNNL_OPTIONS_PORT_DATA (1<<2)
1389#define PNNL_OPTIONS_INITIATORS (1<<3)
1390
1391/*
1392 * Port and N-Port Handle List Element
1393 */
1394typedef struct {
1395 uint16_t pnhle_port_id_lo;
1396 uint16_t pnhle_port_id_hi_handle;
1397} isp_pnhle_21xx_t;
1398
1399typedef struct {
1400 uint16_t pnhle_port_id_lo;
1401 uint16_t pnhle_port_id_hi;
1402 uint16_t pnhle_handle;
1403} isp_pnhle_23xx_t;
1404
1405typedef struct {
1406 uint16_t pnhle_port_id_lo;
1407 uint16_t pnhle_port_id_hi;
1408 uint16_t pnhle_handle;
1409 uint16_t pnhle_reserved;
1410} isp_pnhle_24xx_t;
1411
1412/*
1413 * Port Database Changed Async Event information for 24XX cards
1414 */
1415#define PDB24XX_AE_OK 0x00
1416#define PDB24XX_AE_IMPL_LOGO_1 0x01
1417#define PDB24XX_AE_IMPL_LOGO_2 0x02
1418#define PDB24XX_AE_IMPL_LOGO_3 0x03
1419#define PDB24XX_AE_PLOGI_RCVD 0x04
1420#define PDB24XX_AE_PLOGI_RJT 0x05
1421#define PDB24XX_AE_PRLI_RCVD 0x06
1422#define PDB24XX_AE_PRLI_RJT 0x07
1423#define PDB24XX_AE_TPRLO 0x08
1424#define PDB24XX_AE_TPRLO_RJT 0x09
1425#define PDB24XX_AE_PRLO_RCVD 0x0a
1426#define PDB24XX_AE_LOGO_RCVD 0x0b
1427#define PDB24XX_AE_TOPO_CHG 0x0c
1428#define PDB24XX_AE_NPORT_CHG 0x0d
1429#define PDB24XX_AE_FLOGI_RJT 0x0e
1430#define PDB24XX_AE_BAD_FANN 0x0f
1431#define PDB24XX_AE_FLOGI_TIMO 0x10
1432#define PDB24XX_AE_ABX_LOGO 0x11
1433#define PDB24XX_AE_PLOGI_DONE 0x12
1434#define PDB24XX_AE_PRLI_DONJE 0x13
1435#define PDB24XX_AE_OPN_1 0x14
1436#define PDB24XX_AE_OPN_2 0x15
1437#define PDB24XX_AE_TXERR 0x16
1438#define PDB24XX_AE_FORCED_LOGO 0x17
1439#define PDB24XX_AE_DISC_TIMO 0x18
1440
1441/*
1442 * Genericized Port Login/Logout software structure
1443 */
1444typedef struct {
1445 uint16_t handle;
1446 uint16_t channel;
1447 uint32_t
1448 flags : 8,
1449 portid : 24;
1450} isp_plcmd_t;
1451/* the flags to use are those for PLOGX_FLG_* below */
1452
1453/*
1454 * ISP24XX- Login/Logout Port IOCB
1455 */
1456typedef struct {
1457 isphdr_t plogx_header;
1458 uint32_t plogx_handle;
1459 uint16_t plogx_status;
1460 uint16_t plogx_nphdl;
1461 uint16_t plogx_flags;
1462 uint16_t plogx_vphdl; /* low 8 bits */
1463 uint16_t plogx_portlo; /* low 16 bits */
1464 uint16_t plogx_rspsz_porthi;
1465 struct {
1466 uint16_t lo16;
1467 uint16_t hi16;
1468 } plogx_ioparm[11];
1469} isp_plogx_t;
1470
1471#define PLOGX_STATUS_OK 0x00
1472#define PLOGX_STATUS_UNAVAIL 0x28
1473#define PLOGX_STATUS_LOGOUT 0x29
1474#define PLOGX_STATUS_IOCBERR 0x31
1475
1476#define PLOGX_IOCBERR_NOLINK 0x01
1477#define PLOGX_IOCBERR_NOIOCB 0x02
1478#define PLOGX_IOCBERR_NOXGHG 0x03
1479#define PLOGX_IOCBERR_FAILED 0x04 /* further info in IOPARM 1 */
1480#define PLOGX_IOCBERR_NOFABRIC 0x05
1481#define PLOGX_IOCBERR_NOTREADY 0x07
1482#define PLOGX_IOCBERR_NOLOGIN 0x09 /* further info in IOPARM 1 */
1483#define PLOGX_IOCBERR_NOPCB 0x0a
1484#define PLOGX_IOCBERR_REJECT 0x18 /* further info in IOPARM 1 */
1485#define PLOGX_IOCBERR_EINVAL 0x19 /* further info in IOPARM 1 */
1486#define PLOGX_IOCBERR_PORTUSED 0x1a /* further info in IOPARM 1 */
1487#define PLOGX_IOCBERR_HNDLUSED 0x1b /* further info in IOPARM 1 */
1488#define PLOGX_IOCBERR_NOHANDLE 0x1c
1489#define PLOGX_IOCBERR_NOFLOGI 0x1f /* further info in IOPARM 1 */
1490
1491#define PLOGX_FLG_CMD_MASK 0xf
1492#define PLOGX_FLG_CMD_PLOGI 0
1493#define PLOGX_FLG_CMD_PRLI 1
1494#define PLOGX_FLG_CMD_PDISC 2
1495#define PLOGX_FLG_CMD_LOGO 8
1496#define PLOGX_FLG_CMD_PRLO 9
1497#define PLOGX_FLG_CMD_TPRLO 10
1498
1499#define PLOGX_FLG_COND_PLOGI 0x10 /* if with PLOGI */
1500#define PLOGX_FLG_IMPLICIT 0x10 /* if with LOGO, PRLO, TPRLO */
1501#define PLOGX_FLG_SKIP_PRLI 0x20 /* if with PLOGI */
1502#define PLOGX_FLG_IMPLICIT_LOGO_ALL 0x20 /* if with LOGO */
1503#define PLOGX_FLG_EXPLICIT_LOGO 0x40 /* if with LOGO */
1504#define PLOGX_FLG_COMMON_FEATURES 0x80 /* if with PLOGI */
1505#define PLOGX_FLG_FREE_NPHDL 0x80 /* if with with LOGO */
1506
1507#define PLOGX_FLG_CLASS2 0x100 /* if with PLOGI */
1508#define PLOGX_FLG_FCP2_OVERRIDE 0x200 /* if with PRLOG, PRLI */
1509
1510/*
1511 * Report ID Acquisistion (24XX multi-id firmware)
1512 */
1513typedef struct {
1514 isphdr_t ridacq_hdr;
1515 uint32_t ridacq_handle;
1516 uint8_t ridacq_vp_acquired;
1517 uint8_t ridacq_vp_setup;
1518 uint8_t ridacq_vp_index;
1519 uint8_t ridacq_vp_status;
1520 uint16_t ridacq_vp_port_lo;
1521 uint8_t ridacq_vp_port_hi;
1522 uint8_t ridacq_format; /* 0 or 1 */
1523 uint16_t ridacq_map[8];
1524 uint8_t ridacq_reserved1[32];
1525} isp_ridacq_t;
1526
1527#define RIDACQ_STS_COMPLETE 0
1528#define RIDACQ_STS_UNACQUIRED 1
1529#define RIDACQ_STS_CHANGED 2
1530#define RIDACQ_STS_SNS_TIMEOUT 3
1531#define RIDACQ_STS_SNS_REJECTED 4
1532#define RIDACQ_STS_SCR_TIMEOUT 5
1533#define RIDACQ_STS_SCR_REJECTED 6
1534
1535/*
1536 * Simple Name Server Data Structures
1537 */
1538#define SNS_GA_NXT 0x100
1539#define SNS_GPN_ID 0x112
1540#define SNS_GNN_ID 0x113
1541#define SNS_GFF_ID 0x11F
1542#define SNS_GID_FT 0x171
1543#define SNS_RFT_ID 0x217
1544#define SNS_RFF_ID 0x21F
1545typedef struct {
1546 uint16_t snscb_rblen; /* response buffer length (words) */
1547 uint16_t snscb_reserved0;
1548 uint16_t snscb_addr[4]; /* response buffer address */
1549 uint16_t snscb_sblen; /* subcommand buffer length (words) */
1550 uint16_t snscb_reserved1;
1551 uint16_t snscb_data[]; /* variable data */
1552} sns_screq_t; /* Subcommand Request Structure */
1553
1554typedef struct {
1555 uint16_t snscb_rblen; /* response buffer length (words) */
1556 uint16_t snscb_reserved0;
1557 uint16_t snscb_addr[4]; /* response buffer address */
1558 uint16_t snscb_sblen; /* subcommand buffer length (words) */
1559 uint16_t snscb_reserved1;
1560 uint16_t snscb_cmd;
1561 uint16_t snscb_reserved2;
1562 uint32_t snscb_reserved3;
1563 uint32_t snscb_port;
1564} sns_ga_nxt_req_t;
1565#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t))
1566
1567typedef struct {
1568 uint16_t snscb_rblen; /* response buffer length (words) */
1569 uint16_t snscb_reserved0;
1570 uint16_t snscb_addr[4]; /* response buffer address */
1571 uint16_t snscb_sblen; /* subcommand buffer length (words) */
1572 uint16_t snscb_reserved1;
1573 uint16_t snscb_cmd;
1574 uint16_t snscb_reserved2;
1575 uint32_t snscb_reserved3;
1576 uint32_t snscb_portid;
1577} sns_gxn_id_req_t;
1578#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t))
1579
1580typedef struct {
1581 uint16_t snscb_rblen; /* response buffer length (words) */
1582 uint16_t snscb_reserved0;
1583 uint16_t snscb_addr[4]; /* response buffer address */
1584 uint16_t snscb_sblen; /* subcommand buffer length (words) */
1585 uint16_t snscb_reserved1;
1586 uint16_t snscb_cmd;
1587 uint16_t snscb_mword_div_2;
1588 uint32_t snscb_reserved3;
1589 uint32_t snscb_fc4_type;
1590} sns_gid_ft_req_t;
1591#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t))
1592
1593typedef struct {
1594 uint16_t snscb_rblen; /* response buffer length (words) */
1595 uint16_t snscb_reserved0;
1596 uint16_t snscb_addr[4]; /* response buffer address */
1597 uint16_t snscb_sblen; /* subcommand buffer length (words) */
1598 uint16_t snscb_reserved1;
1599 uint16_t snscb_cmd;
1600 uint16_t snscb_reserved2;
1601 uint32_t snscb_reserved3;
1602 uint32_t snscb_port;
1603 uint32_t snscb_fc4_types[8];
1604} sns_rft_id_req_t;
1605#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t))
1606
1607typedef struct {
1608 ct_hdr_t snscb_cthdr;
1609 uint8_t snscb_port_type;
1610 uint8_t snscb_port_id[3];
1611 uint8_t snscb_portname[8];
1612 uint16_t snscb_data[]; /* variable data */
1613} sns_scrsp_t; /* Subcommand Response Structure */
1614
1615typedef struct {
1616 ct_hdr_t snscb_cthdr;
1617 uint8_t snscb_port_type;
1618 uint8_t snscb_port_id[3];
1619 uint8_t snscb_portname[8];
1620 uint8_t snscb_pnlen; /* symbolic port name length */
1621 uint8_t snscb_pname[255]; /* symbolic port name */
1622 uint8_t snscb_nodename[8];
1623 uint8_t snscb_nnlen; /* symbolic node name length */
1624 uint8_t snscb_nname[255]; /* symbolic node name */
1625 uint8_t snscb_ipassoc[8];
1626 uint8_t snscb_ipaddr[16];
1627 uint8_t snscb_svc_class[4];
1628 uint8_t snscb_fc4_types[32];
1629 uint8_t snscb_fpname[8];
1630 uint8_t snscb_reserved;
1631 uint8_t snscb_hardaddr[3];
1632} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */
1633#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t))
1634
1635typedef struct {
1636 ct_hdr_t snscb_cthdr;
1637 uint8_t snscb_wwn[8];
1638} sns_gxn_id_rsp_t;
1639#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t))
1640
1641typedef struct {
1642 ct_hdr_t snscb_cthdr;
1643 uint32_t snscb_fc4_features[32];
1644} sns_gff_id_rsp_t;
1645#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t))
1646
1647typedef struct {
1648 ct_hdr_t snscb_cthdr;
1649 struct {
1650 uint8_t control;
1651 uint8_t portid[3];
1652 } snscb_ports[1];
1653} sns_gid_ft_rsp_t;
1654#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2))
1655#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t))
1656
1657/*
1658 * Other Misc Structures
1659 */
1660
1661/* ELS Pass Through */
1662typedef struct {
1663 isphdr_t els_hdr;
1664 uint32_t els_handle;
1665 uint16_t els_status;
1666 uint16_t els_nphdl;
1667 uint16_t els_xmit_dsd_count; /* outgoing only */
1668 uint8_t els_vphdl;
1669 uint8_t els_sof;
1670 uint32_t els_rxid;
1671 uint16_t els_recv_dsd_count; /* outgoing only */
1672 uint8_t els_opcode;
1673 uint8_t els_reserved1;
1674 uint8_t els_did_lo;
1675 uint8_t els_did_mid;
1676 uint8_t els_did_hi;
1677 uint8_t els_reserved2;
1678 uint16_t els_reserved3;
1679 uint16_t els_ctl_flags;
1680 union {
1681 struct {
1682 uint32_t _els_bytecnt;
1683 uint32_t _els_subcode1;
1684 uint32_t _els_subcode2;
1685 uint8_t _els_reserved4[20];
1686 } in;
1687 struct {
1688 uint32_t _els_recv_bytecnt;
1689 uint32_t _els_xmit_bytecnt;
1690 uint32_t _els_xmit_dsd_length;
1691 uint16_t _els_xmit_dsd_a1500;
1692 uint16_t _els_xmit_dsd_a3116;
1693 uint16_t _els_xmit_dsd_a4732;
1694 uint16_t _els_xmit_dsd_a6348;
1695 uint32_t _els_recv_dsd_length;
1696 uint16_t _els_recv_dsd_a1500;
1697 uint16_t _els_recv_dsd_a3116;
1698 uint16_t _els_recv_dsd_a4732;
1699 uint16_t _els_recv_dsd_a6348;
1700 } out;
1701 } inout;
1702#define els_bytecnt inout.in._els_bytecnt
1703#define els_subcode1 inout.in._els_subcode1
1704#define els_subcode2 inout.in._els_subcode2
1705#define els_reserved4 inout.in._els_reserved4
1706#define els_recv_bytecnt inout.out._els_recv_bytecnt
1707#define els_xmit_bytecnt inout.out._els_xmit_bytecnt
1708#define els_xmit_dsd_length inout.out._els_xmit_dsd_length
1709#define els_xmit_dsd_a1500 inout.out._els_xmit_dsd_a1500
1710#define els_xmit_dsd_a3116 inout.out._els_xmit_dsd_a3116
1711#define els_xmit_dsd_a4732 inout.out._els_xmit_dsd_a4732
1712#define els_xmit_dsd_a6348 inout.out._els_xmit_dsd_a6348
1713#define els_recv_dsd_length inout.out._els_recv_dsd_length
1714#define els_recv_dsd_a1500 inout.out._els_recv_dsd_a1500
1715#define els_recv_dsd_a3116 inout.out._els_recv_dsd_a3116
1716#define els_recv_dsd_a4732 inout.out._els_recv_dsd_a4732
1717#define els_recv_dsd_a6348 inout.out._els_recv_dsd_a6348
1718} els_t;
1719
1720/*
1721 * A handy package structure for running FC-SCSI commands internally
1722 */
1723typedef struct {
1724 uint16_t handle;
1725 uint16_t lun;
1726 uint32_t
1727 channel : 8,
1728 portid : 24;
1729 uint32_t timeout;
1730 union {
1731 struct {
1732 uint32_t data_length;
1733 uint32_t
1734 no_wait : 1,
1735 do_read : 1;
1736 uint8_t cdb[16];
1737 void *data_ptr;
1738 } beg;
1739 struct {
1740 uint32_t data_residual;
1741 uint8_t status;
1742 uint8_t pad;
1743 uint16_t sense_length;
1744 uint8_t sense_data[32];
1745 } end;
1746 } fcd;
1747} isp_xcmd_t;
1748
1749/*
1750 * Target Mode related definitions
1751 */
1752#define QLTM_SENSELEN 18 /* non-FC cards only */
1753#define QLTM_SVALID 0x80
1754
1755/*
1756 * Structure for Enable Lun and Modify Lun queue entries
1757 */
1758typedef struct {
1759 isphdr_t le_header;
1760 uint32_t le_reserved;
1761 uint8_t le_lun;
1762 uint8_t le_rsvd;
1763 uint8_t le_ops; /* Modify LUN only */
1764 uint8_t le_tgt; /* Not for FC */
1765 uint32_t le_flags; /* Not for FC */
1766 uint8_t le_status;
1767 uint8_t le_reserved2;
1768 uint8_t le_cmd_count;
1769 uint8_t le_in_count;
1770 uint8_t le_cdb6len; /* Not for FC */
1771 uint8_t le_cdb7len; /* Not for FC */
1772 uint16_t le_timeout;
1773 uint16_t le_reserved3[20];
1774} lun_entry_t;
1775
1776/*
1777 * le_flags values
1778 */
1779#define LUN_TQAE 0x00000002 /* bit1 Tagged Queue Action Enable */
1780#define LUN_DSSM 0x01000000 /* bit24 Disable Sending SDP Message */
1781#define LUN_DISAD 0x02000000 /* bit25 Disable autodisconnect */
1782#define LUN_DM 0x40000000 /* bit30 Disconnects Mandatory */
1783
1784/*
1785 * le_ops values
1786 */
1787#define LUN_CCINCR 0x01 /* increment command count */
1788#define LUN_CCDECR 0x02 /* decrement command count */
1789#define LUN_ININCR 0x40 /* increment immed. notify count */
1790#define LUN_INDECR 0x80 /* decrement immed. notify count */
1791
1792/*
1793 * le_status values
1794 */
1795#define LUN_OK 0x01 /* we be rockin' */
1796#define LUN_ERR 0x04 /* request completed with error */
1797#define LUN_INVAL 0x06 /* invalid request */
1798#define LUN_NOCAP 0x16 /* can't provide requested capability */
1799#define LUN_ENABLED 0x3E /* LUN already enabled */
1800
1801/*
1802 * Immediate Notify Entry structure
1803 */
1804#define IN_MSGLEN 8 /* 8 bytes */
1805#define IN_RSVDLEN 8 /* 8 words */
1806typedef struct {
1807 isphdr_t in_header;
1808 uint32_t in_reserved;
1809 uint8_t in_lun; /* lun */
1810 uint8_t in_iid; /* initiator */
1811 uint8_t in_reserved2;
1812 uint8_t in_tgt; /* target */
1813 uint32_t in_flags;
1814 uint8_t in_status;
1815 uint8_t in_rsvd2;
1816 uint8_t in_tag_val; /* tag value */
1817 uint8_t in_tag_type; /* tag type */
1818 uint16_t in_seqid; /* sequence id */
1819 uint8_t in_msg[IN_MSGLEN]; /* SCSI message bytes */
1820 uint16_t in_reserved3[IN_RSVDLEN];
1821 uint8_t in_sense[QLTM_SENSELEN];/* suggested sense data */
1822} in_entry_t;
1823
1824typedef struct {
1825 isphdr_t in_header;
1826 uint32_t in_reserved;
1827 uint8_t in_lun; /* lun */
1828 uint8_t in_iid; /* initiator */
1829 uint16_t in_scclun;
1830 uint32_t in_reserved2;
1831 uint16_t in_status;
1832 uint16_t in_task_flags;
1833 uint16_t in_seqid; /* sequence id */
1834} in_fcentry_t;
1835
1836typedef struct {
1837 isphdr_t in_header;
1838 uint32_t in_reserved;
1839 uint16_t in_iid; /* initiator */
1840 uint16_t in_scclun;
1841 uint32_t in_reserved2;
1842 uint16_t in_status;
1843 uint16_t in_task_flags;
1844 uint16_t in_seqid; /* sequence id */
1845} in_fcentry_e_t;
1846
1847/*
1848 * Values for the in_status field
1849 */
1850#define IN_REJECT 0x0D /* Message Reject message received */
1851#define IN_RESET 0x0E /* Bus Reset occurred */
1852#define IN_NO_RCAP 0x16 /* requested capability not available */
1853#define IN_IDE_RECEIVED 0x33 /* Initiator Detected Error msg received */
1854#define IN_RSRC_UNAVAIL 0x34 /* resource unavailable */
1855#define IN_MSG_RECEIVED 0x36 /* SCSI message received */
1856#define IN_ABORT_TASK 0x20 /* task named in RX_ID is being aborted (FC) */
1857#define IN_PORT_LOGOUT 0x29 /* port has logged out (FC) */
1858#define IN_PORT_CHANGED 0x2A /* port changed */
1859#define IN_GLOBAL_LOGO 0x2E /* all ports logged out */
1860#define IN_NO_NEXUS 0x3B /* Nexus not established */
1861#define IN_SRR_RCVD 0x45 /* SRR received */
1862
1863/*
1864 * Values for the in_task_flags field- should only get one at a time!
1865 */
1866#define TASK_FLAGS_RESERVED_MASK (0xe700)
1867#define TASK_FLAGS_CLEAR_ACA (1<<14)
1868#define TASK_FLAGS_TARGET_RESET (1<<13)
1869#define TASK_FLAGS_LUN_RESET (1<<12)
1870#define TASK_FLAGS_CLEAR_TASK_SET (1<<10)
1871#define TASK_FLAGS_ABORT_TASK_SET (1<<9)
1872
1873/*
1874 * ISP24XX Immediate Notify
1875 */
1876typedef struct {
1877 isphdr_t in_header;
1878 uint32_t in_reserved;
1879 uint16_t in_nphdl;
1880 uint16_t in_reserved1;
1881 uint16_t in_flags;
1882 uint16_t in_srr_rxid;
1883 uint16_t in_status;
1884 uint8_t in_status_subcode;
1885 uint8_t in_fwhandle;
1886 uint32_t in_rxid;
1887 uint16_t in_srr_reloff_lo;
1888 uint16_t in_srr_reloff_hi;
1889 uint16_t in_srr_iu;
1890 uint16_t in_srr_oxid;
1891 /*
1892 * If bit 2 is set in in_flags, the N-Port and
1893 * handle tags are valid. If the received ELS is
1894 * a LOGO, then these tags contain the N Port ID
1895 * from the LOGO payload. If the received ELS
1896 * request is TPRLO, these tags contain the
1897 * Third Party Originator N Port ID.
1898 */
1899 uint16_t in_nport_id_hi;
1900#define in_prli_options in_nport_id_hi
1901 uint8_t in_nport_id_lo;
1902 uint8_t in_reserved3;
1903 uint16_t in_np_handle;
1904 uint8_t in_reserved4[12];
1905 uint8_t in_reserved5;
1906 uint8_t in_vpidx;
1907 uint32_t in_reserved6;
1908 uint16_t in_portid_lo;
1909 uint8_t in_portid_hi;
1910 uint8_t in_reserved7;
1911 uint16_t in_reserved8;
1912 uint16_t in_oxid;
1913} in_fcentry_24xx_t;
1914
1915#define IN24XX_FLAG_PUREX_IOCB 0x1
1916#define IN24XX_FLAG_GLOBAL_LOGOUT 0x2
1917#define IN24XX_FLAG_NPHDL_VALID 0x4
1918#define IN24XX_FLAG_N2N_PRLI 0x8
1919#define IN24XX_FLAG_PN_NN_VALID 0x10
1920
1921#define IN24XX_LIP_RESET 0x0E
1922#define IN24XX_LINK_RESET 0x0F
1923#define IN24XX_PORT_LOGOUT 0x29
1924#define IN24XX_PORT_CHANGED 0x2A
1925#define IN24XX_LINK_FAILED 0x2E
1926#define IN24XX_SRR_RCVD 0x45
1927#define IN24XX_ELS_RCVD 0x46 /*
1928 * login-affectin ELS received- check
1929 * subcode for specific opcode
1930 */
1931
1932/*
1933 * For f/w > 4.0.25, these offsets in the Immediate Notify contain
1934 * the WWNN/WWPN if the ELS is PLOGI, PDISC or ADISC. The WWN is in
1935 * Big Endian format.
1936 */
1937#define IN24XX_PRLI_WWNN_OFF 0x18
1938#define IN24XX_PRLI_WWPN_OFF 0x28
1939#define IN24XX_PLOGI_WWNN_OFF 0x20
1940#define IN24XX_PLOGI_WWPN_OFF 0x28
1941
1942/*
1943 * For f/w > 4.0.25, this offset in the Immediate Notify contain
1944 * the WWPN if the ELS is LOGO. The WWN is in Big Endian format.
1945 */
1946#define IN24XX_LOGO_WWPN_OFF 0x28
1947
1948/*
1949 * Immediate Notify Status Subcodes for IN24XX_PORT_LOGOUT
1950 */
1951#define IN24XX_PORT_LOGOUT_PDISC_TMO 0x00
1952#define IN24XX_PORT_LOGOUT_UXPR_DISC 0x01
1953#define IN24XX_PORT_LOGOUT_OWN_OPN 0x02
1954#define IN24XX_PORT_LOGOUT_OWN_OPN_SFT 0x03
1955#define IN24XX_PORT_LOGOUT_ABTS_TMO 0x04
1956#define IN24XX_PORT_LOGOUT_DISC_RJT 0x05
1957#define IN24XX_PORT_LOGOUT_LOGIN_NEEDED 0x06
1958#define IN24XX_PORT_LOGOUT_BAD_DISC 0x07
1959#define IN24XX_PORT_LOGOUT_LOST_ALPA 0x08
1960#define IN24XX_PORT_LOGOUT_XMIT_FAILURE 0x09
1961
1962/*
1963 * Immediate Notify Status Subcodes for IN24XX_PORT_CHANGED
1964 */
1965#define IN24XX_PORT_CHANGED_BADFAN 0x00
1966#define IN24XX_PORT_CHANGED_TOPO_CHANGE 0x01
1967#define IN24XX_PORT_CHANGED_FLOGI_ACC 0x02
1968#define IN24XX_PORT_CHANGED_FLOGI_RJT 0x03
1969#define IN24XX_PORT_CHANGED_TIMEOUT 0x04
1970#define IN24XX_PORT_CHANGED_PORT_CHANGE 0x05
1971
1972/*
1973 * Notify Acknowledge Entry structure
1974 */
1975#define NA_RSVDLEN 22
1976typedef struct {
1977 isphdr_t na_header;
1978 uint32_t na_reserved;
1979 uint8_t na_lun; /* lun */
1980 uint8_t na_iid; /* initiator */
1981 uint8_t na_reserved2;
1982 uint8_t na_tgt; /* target */
1983 uint32_t na_flags;
1984 uint8_t na_status;
1985 uint8_t na_event;
1986 uint16_t na_seqid; /* sequence id */
1987 uint16_t na_reserved3[NA_RSVDLEN];
1988} na_entry_t;
1989
1990/*
1991 * Value for the na_event field
1992 */
1993#define NA_RST_CLRD 0x80 /* Clear an async event notification */
1994#define NA_OK 0x01 /* Notify Acknowledge Succeeded */
1995#define NA_INVALID 0x06 /* Invalid Notify Acknowledge */
1996
1997#define NA2_RSVDLEN 21
1998typedef struct {
1999 isphdr_t na_header;
2000 uint32_t na_reserved;
2001 uint8_t na_reserved1;
2002 uint8_t na_iid; /* initiator loop id */
2003 uint16_t na_response;
2004 uint16_t na_flags;
2005 uint16_t na_reserved2;
2006 uint16_t na_status;
2007 uint16_t na_task_flags;
2008 uint16_t na_seqid; /* sequence id */
2009 uint16_t na_reserved3[NA2_RSVDLEN];
2010} na_fcentry_t;
2011
2012typedef struct {
2013 isphdr_t na_header;
2014 uint32_t na_reserved;
2015 uint16_t na_iid; /* initiator loop id */
2016 uint16_t na_response; /* response code */
2017 uint16_t na_flags;
2018 uint16_t na_reserved2;
2019 uint16_t na_status;
2020 uint16_t na_task_flags;
2021 uint16_t na_seqid; /* sequence id */
2022 uint16_t na_reserved3[NA2_RSVDLEN];
2023} na_fcentry_e_t;
2024
2025#define NAFC_RCOUNT 0x80 /* increment resource count */
2026#define NAFC_RST_CLRD 0x20 /* Clear LIP Reset */
2027#define NAFC_TVALID 0x10 /* task mangement response code is valid */
2028
2029/*
2030 * ISP24XX Notify Acknowledge
2031 */
2032
2033typedef struct {
2034 isphdr_t na_header;
2035 uint32_t na_handle;
2036 uint16_t na_nphdl;
2037 uint16_t na_reserved1;
2038 uint16_t na_flags;
2039 uint16_t na_srr_rxid;
2040 uint16_t na_status;
2041 uint8_t na_status_subcode;
2042 uint8_t na_fwhandle;
2043 uint32_t na_rxid;
2044 uint16_t na_srr_reloff_lo;
2045 uint16_t na_srr_reloff_hi;
2046 uint16_t na_srr_iu;
2047 uint16_t na_srr_flags;
2048 uint8_t na_reserved3[18];
2049 uint8_t na_reserved4;
2050 uint8_t na_vpidx;
2051 uint8_t na_srr_reject_vunique;
2052 uint8_t na_srr_reject_explanation;
2053 uint8_t na_srr_reject_code;
2054 uint8_t na_reserved5;
2055 uint8_t na_reserved6[6];
2056 uint16_t na_oxid;
2057} na_fcentry_24xx_t;
2058
2059/*
2060 * Accept Target I/O Entry structure
2061 */
2062#define ATIO_CDBLEN 26
2063
2064typedef struct {
2065 isphdr_t at_header;
2066 uint16_t at_reserved;
2067 uint16_t at_handle;
2068 uint8_t at_lun; /* lun */
2069 uint8_t at_iid; /* initiator */
2070 uint8_t at_cdblen; /* cdb length */
2071 uint8_t at_tgt; /* target */
2072 uint32_t at_flags;
2073 uint8_t at_status; /* firmware status */
2074 uint8_t at_scsi_status; /* scsi status */
2075 uint8_t at_tag_val; /* tag value */
2076 uint8_t at_tag_type; /* tag type */
2077 uint8_t at_cdb[ATIO_CDBLEN]; /* received CDB */
2078 uint8_t at_sense[QLTM_SENSELEN];/* suggested sense data */
2079} at_entry_t;
2080
2081/*
2082 * at_flags values
2083 */
2084#define AT_NODISC 0x00008000 /* disconnect disabled */
2085#define AT_TQAE 0x00000002 /* Tagged Queue Action enabled */
2086
2087/*
2088 * at_status values
2089 */
2090#define AT_PATH_INVALID 0x07 /* ATIO sent to firmware for disabled lun */
2091#define AT_RESET 0x0E /* SCSI Bus Reset Occurred */
2092#define AT_PHASE_ERROR 0x14 /* Bus phase sequence error */
2093#define AT_NOCAP 0x16 /* Requested capability not available */
2094#define AT_BDR_MSG 0x17 /* Bus Device Reset msg received */
2095#define AT_CDB 0x3D /* CDB received */
2096/*
2097 * Macros to create and fetch and test concatenated handle and tag value macros
2098 * (SPI only)
2099 */
2100#define AT_MAKE_TAGID(tid, aep) \
2101 tid = aep->at_handle; \
2102 if (aep->at_flags & AT_TQAE) { \
2103 tid |= (aep->at_tag_val << 16); \
2104 tid |= (1 << 24); \
2105 }
2106
2107#define CT_MAKE_TAGID(tid, ct) \
2108 tid = ct->ct_fwhandle; \
2109 if (ct->ct_flags & CT_TQAE) { \
2110 tid |= (ct->ct_tag_val << 16); \
2111 tid |= (1 << 24); \
2112 }
2113
2114#define AT_HAS_TAG(val) ((val) & (1 << 24))
2115#define AT_GET_TAG(val) (((val) >> 16) & 0xff)
2116#define AT_GET_HANDLE(val) ((val) & 0xffff)
2117
2118#define IN_MAKE_TAGID(tid, inp) \
2119 tid = inp->in_seqid; \
2120 tid |= (inp->in_tag_val << 16); \
2121 tid |= (1 << 24)
2122
2123/*
2124 * Accept Target I/O Entry structure, Type 2
2125 */
2126#define ATIO2_CDBLEN 16
2127
2128typedef struct {
2129 isphdr_t at_header;
2130 uint32_t at_reserved;
2131 uint8_t at_lun; /* lun or reserved */
2132 uint8_t at_iid; /* initiator */
2133 uint16_t at_rxid; /* response ID */
2134 uint16_t at_flags;
2135 uint16_t at_status; /* firmware status */
2136 uint8_t at_crn; /* command reference number */
2137 uint8_t at_taskcodes;
2138 uint8_t at_taskflags;
2139 uint8_t at_execodes;
2140 uint8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */
2141 uint32_t at_datalen; /* allocated data len */
2142 uint16_t at_scclun; /* SCC Lun or reserved */
2143 uint16_t at_wwpn[4]; /* WWPN of initiator */
2144 uint16_t at_reserved2[6];
2145 uint16_t at_oxid;
2146} at2_entry_t;
2147
2148typedef struct {
2149 isphdr_t at_header;
2150 uint32_t at_reserved;
2151 uint16_t at_iid; /* initiator */
2152 uint16_t at_rxid; /* response ID */
2153 uint16_t at_flags;
2154 uint16_t at_status; /* firmware status */
2155 uint8_t at_crn; /* command reference number */
2156 uint8_t at_taskcodes;
2157 uint8_t at_taskflags;
2158 uint8_t at_execodes;
2159 uint8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */
2160 uint32_t at_datalen; /* allocated data len */
2161 uint16_t at_scclun; /* SCC Lun or reserved */
2162 uint16_t at_wwpn[4]; /* WWPN of initiator */
2163 uint16_t at_reserved2[6];
2164 uint16_t at_oxid;
2165} at2e_entry_t;
2166
2167#define ATIO2_WWPN_OFFSET 0x2A
2168#define ATIO2_OXID_OFFSET 0x3E
2169
2170#define ATIO2_TC_ATTR_MASK 0x7
2171#define ATIO2_TC_ATTR_SIMPLEQ 0
2172#define ATIO2_TC_ATTR_HEADOFQ 1
2173#define ATIO2_TC_ATTR_ORDERED 2
2174#define ATIO2_TC_ATTR_ACAQ 4
2175#define ATIO2_TC_ATTR_UNTAGGED 5
2176
2177#define ATIO2_EX_WRITE 0x1
2178#define ATIO2_EX_READ 0x2
2179/*
2180 * Macros to create and fetch and test concatenated handle and tag value macros
2181 */
2182#define AT2_MAKE_TAGID(tid, bus, inst, aep) \
2183 tid = aep->at_rxid; \
2184 tid |= (((uint64_t)inst) << 32); \
2185 tid |= (((uint64_t)bus) << 48)
2186
2187#define CT2_MAKE_TAGID(tid, bus, inst, ct) \
2188 tid = ct->ct_rxid; \
2189 tid |= (((uint64_t)inst) << 32); \
2190 tid |= (((uint64_t)(bus & 0xff)) << 48)
2191
2192#define AT2_HAS_TAG(val) 1
2193#define AT2_GET_TAG(val) ((val) & 0xffffffff)
2194#define AT2_GET_INST(val) (((val) >> 32) & 0xffff)
2195#define AT2_GET_HANDLE AT2_GET_TAG
2196#define AT2_GET_BUS(val) (((val) >> 48) & 0xff)
2197
2198#define FC_HAS_TAG AT2_HAS_TAG
2199#define FC_GET_TAG AT2_GET_TAG
2200#define FC_GET_INST AT2_GET_INST
2201#define FC_GET_HANDLE AT2_GET_HANDLE
2202
2203#define IN_FC_MAKE_TAGID(tid, bus, inst, seqid) \
2204 tid = seqid; \
2205 tid |= (((uint64_t)inst) << 32); \
2206 tid |= (((uint64_t)(bus & 0xff)) << 48)
2207
2208#define FC_TAG_INSERT_INST(tid, inst) \
2209 tid &= ~0x0000ffff00000000ull; \
2210 tid |= (((uint64_t)inst) << 32)
2211
2212/*
2213 * 24XX ATIO Definition
2214 *
2215 * This is *quite* different from other entry types.
2216 * First of all, it has its own queue it comes in on.
2217 *
2218 * Secondly, it doesn't have a normal header.
2219 *
2220 * Thirdly, it's just a passthru of the FCP CMND IU
2221 * which is recorded in big endian mode.
2222 */
2223typedef struct {
2224 uint8_t at_type;
2225 uint8_t at_count;
2226 /*
2227 * Task attribute in high four bits,
2228 * the rest is the FCP CMND IU Length.
2229 * NB: the command can extend past the
2230 * length for a single queue entry.
2231 */
2232 uint16_t at_ta_len;
2233 uint32_t at_rxid;
2234 fc_hdr_t at_hdr;
2235 fcp_cmnd_iu_t at_cmnd;
2236} at7_entry_t;
2237#define AT7_NORESRC_RXID 0xffffffff
2238
2239
2240/*
2241 * Continue Target I/O Entry structure
2242 * Request from driver. The response from the
2243 * ISP firmware is the same except that the last 18
2244 * bytes are overwritten by suggested sense data if
2245 * the 'autosense valid' bit is set in the status byte.
2246 */
2247typedef struct {
2248 isphdr_t ct_header;
2249 uint16_t ct_syshandle;
2250 uint16_t ct_fwhandle; /* required by f/w */
2251 uint8_t ct_lun; /* lun */
2252 uint8_t ct_iid; /* initiator id */
2253 uint8_t ct_reserved2;
2254 uint8_t ct_tgt; /* our target id */
2255 uint32_t ct_flags;
2256 uint8_t ct_status; /* isp status */
2257 uint8_t ct_scsi_status; /* scsi status */
2258 uint8_t ct_tag_val; /* tag value */
2259 uint8_t ct_tag_type; /* tag type */
2260 uint32_t ct_xfrlen; /* transfer length */
2261 uint32_t ct_resid; /* residual length */
2262 uint16_t ct_timeout;
2263 uint16_t ct_seg_count;
2264 ispds_t ct_dataseg[ISP_RQDSEG];
2265} ct_entry_t;
2266
2267/*
2268 * For some of the dual port SCSI adapters, port (bus #) is reported
2269 * in the MSbit of ct_iid. Bit fields are a bit too awkward here.
2270 *
2271 * Note that this does not apply to FC adapters at all which can and
2272 * do report IIDs between 0x81 && 0xfe (or 0x7ff) which represent devices
2273 * that have logged in across a SCSI fabric.
2274 */
2275#define GET_IID_VAL(x) (x & 0x3f)
2276#define GET_BUS_VAL(x) ((x >> 7) & 0x1)
2277#define SET_IID_VAL(y, x) y = ((y & ~0x3f) | (x & 0x3f))
2278#define SET_BUS_VAL(y, x) y = ((y & 0x3f) | ((x & 0x1) << 7))
2279
2280/*
2281 * ct_flags values
2282 */
2283#define CT_TQAE 0x00000002 /* bit 1, Tagged Queue Action enable */
2284#define CT_DATA_IN 0x00000040 /* bits 6&7, Data direction - *to* initiator */
2285#define CT_DATA_OUT 0x00000080 /* bits 6&7, Data direction - *from* initiator */
2286#define CT_NO_DATA 0x000000C0 /* bits 6&7, Data direction */
2287#define CT_CCINCR 0x00000100 /* bit 8, autoincrement atio count */
2288#define CT_DATAMASK 0x000000C0 /* bits 6&7, Data direction */
2289#define CT_INISYNCWIDE 0x00004000 /* bit 14, Do Sync/Wide Negotiation */
2290#define CT_NODISC 0x00008000 /* bit 15, Disconnects disabled */
2291#define CT_DSDP 0x01000000 /* bit 24, Disable Save Data Pointers */
2292#define CT_SENDRDP 0x04000000 /* bit 26, Send Restore Pointers msg */
2293#define CT_SENDSTATUS 0x80000000 /* bit 31, Send SCSI status byte */
2294
2295/*
2296 * ct_status values
2297 * - set by the firmware when it returns the CTIO
2298 */
2299#define CT_OK 0x01 /* completed without error */
2300#define CT_ABORTED 0x02 /* aborted by host */
2301#define CT_ERR 0x04 /* see sense data for error */
2302#define CT_INVAL 0x06 /* request for disabled lun */
2303#define CT_NOPATH 0x07 /* invalid ITL nexus */
2304#define CT_INVRXID 0x08 /* (FC only) Invalid RX_ID */
2305#define CT_DATA_OVER 0x09 /* (FC only) Data Overrun */
2306#define CT_RSELTMO 0x0A /* reselection timeout after 2 tries */
2307#define CT_TIMEOUT 0x0B /* timed out */
2308#define CT_RESET 0x0E /* SCSI Bus Reset occurred */
2309#define CT_PARITY 0x0F /* Uncorrectable Parity Error */
2310#define CT_BUS_ERROR 0x10 /* (FC Only) DMA PCI Error */
2311#define CT_PANIC 0x13 /* Unrecoverable Error */
2312#define CT_PHASE_ERROR 0x14 /* Bus phase sequence error */
2313#define CT_DATA_UNDER 0x15 /* (FC only) Data Underrun */
2314#define CT_BDR_MSG 0x17 /* Bus Device Reset msg received */
2315#define CT_TERMINATED 0x19 /* due to Terminate Transfer mbox cmd */
2316#define CT_PORTUNAVAIL 0x28 /* port not available */
2317#define CT_LOGOUT 0x29 /* port logout */
2318#define CT_PORTCHANGED 0x2A /* port changed */
2319#define CT_IDE 0x33 /* Initiator Detected Error */
2320#define CT_NOACK 0x35 /* Outstanding Immed. Notify. entry */
2321#define CT_SRR 0x45 /* SRR Received */
2322#define CT_LUN_RESET 0x48 /* Lun Reset Received */
2323
2324#define CT_HBA_RESET 0xffff /* pseudo error - command destroyed by HBA reset*/
2325
2326/*
2327 * When the firmware returns a CTIO entry, it may overwrite the last
2328 * part of the structure with sense data. This starts at offset 0x2E
2329 * into the entry, which is in the middle of ct_dataseg[1]. Rather
2330 * than define a new struct for this, I'm just using the sense data
2331 * offset.
2332 */
2333#define CTIO_SENSE_OFFSET 0x2E
2334
2335/*
2336 * Entry length in u_longs. All entries are the same size so
2337 * any one will do as the numerator.
2338 */
2339#define UINT32_ENTRY_SIZE (sizeof(at_entry_t)/sizeof(uint32_t))
2340
2341/*
2342 * QLA2100 CTIO (type 2) entry
2343 */
2344#define MAXRESPLEN 26
2345typedef struct {
2346 isphdr_t ct_header;
2347 uint32_t ct_syshandle;
2348 uint8_t ct_lun; /* lun */
2349 uint8_t ct_iid; /* initiator id */
2350 uint16_t ct_rxid; /* response ID */
2351 uint16_t ct_flags;
2352 uint16_t ct_status; /* isp status */
2353 uint16_t ct_timeout;
2354 uint16_t ct_seg_count;
2355 uint32_t ct_reloff; /* relative offset */
2356 uint32_t ct_resid; /* residual length */
2357 union {
2358 /*
2359 * The three different modes that the target driver
2360 * can set the CTIO{2,3,4} up as.
2361 *
2362 * The first is for sending FCP_DATA_IUs as well as
2363 * (optionally) sending a terminal SCSI status FCP_RSP_IU.
2364 *
2365 * The second is for sending SCSI sense data in an FCP_RSP_IU.
2366 * Note that no FCP_DATA_IUs will be sent.
2367 *
2368 * The third is for sending FCP_RSP_IUs as built specifically
2369 * in system memory as located by the isp_dataseg.
2370 */
2371 struct {
2372 uint32_t _reserved;
2373 uint16_t _reserved2;
2374 uint16_t ct_scsi_status;
2375 uint32_t ct_xfrlen;
2376 union {
2377 ispds_t ct_dataseg[ISP_RQDSEG_T2];
2378 ispds64_t ct_dataseg64[ISP_RQDSEG_T3];
2379 ispdslist_t ct_dslist;
2380 } u;
2381 } m0;
2382 struct {
2383 uint16_t _reserved;
2384 uint16_t _reserved2;
2385 uint16_t ct_senselen;
2386 uint16_t ct_scsi_status;
2387 uint16_t ct_resplen;
2388 uint8_t ct_resp[MAXRESPLEN];
2389 } m1;
2390 struct {
2391 uint32_t _reserved;
2392 uint16_t _reserved2;
2393 uint16_t _reserved3;
2394 uint32_t ct_datalen;
2395 union {
2396 ispds_t ct_fcp_rsp_iudata_32;
2397 ispds64_t ct_fcp_rsp_iudata_64;
2398 } u;
2399 } m2;
2400 } rsp;
2401} ct2_entry_t;
2402
2403typedef struct {
2404 isphdr_t ct_header;
2405 uint32_t ct_syshandle;
2406 uint16_t ct_iid; /* initiator id */
2407 uint16_t ct_rxid; /* response ID */
2408 uint16_t ct_flags;
2409 uint16_t ct_status; /* isp status */
2410 uint16_t ct_timeout;
2411 uint16_t ct_seg_count;
2412 uint32_t ct_reloff; /* relative offset */
2413 uint32_t ct_resid; /* residual length */
2414 union {
2415 struct {
2416 uint32_t _reserved;
2417 uint16_t _reserved2;
2418 uint16_t ct_scsi_status;
2419 uint32_t ct_xfrlen;
2420 union {
2421 ispds_t ct_dataseg[ISP_RQDSEG_T2];
2422 ispds64_t ct_dataseg64[ISP_RQDSEG_T3];
2423 ispdslist_t ct_dslist;
2424 } u;
2425 } m0;
2426 struct {
2427 uint16_t _reserved;
2428 uint16_t _reserved2;
2429 uint16_t ct_senselen;
2430 uint16_t ct_scsi_status;
2431 uint16_t ct_resplen;
2432 uint8_t ct_resp[MAXRESPLEN];
2433 } m1;
2434 struct {
2435 uint32_t _reserved;
2436 uint16_t _reserved2;
2437 uint16_t _reserved3;
2438 uint32_t ct_datalen;
2439 union {
2440 ispds_t ct_fcp_rsp_iudata_32;
2441 ispds64_t ct_fcp_rsp_iudata_64;
2442 } u;
2443 } m2;
2444 } rsp;
2445} ct2e_entry_t;
2446
2447/*
2448 * ct_flags values for CTIO2
2449 */
2450#define CT2_FLAG_MODE0 0x0000
2451#define CT2_FLAG_MODE1 0x0001
2452#define CT2_FLAG_MODE2 0x0002
2453#define CT2_FLAG_MMASK 0x0003
2454#define CT2_DATA_IN 0x0040 /* *to* initiator */
2455#define CT2_DATA_OUT 0x0080 /* *from* initiator */
2456#define CT2_NO_DATA 0x00C0
2457#define CT2_DATAMASK 0x00C0
2458#define CT2_CCINCR 0x0100
2459#define CT2_FASTPOST 0x0200
2460#define CT2_CONFIRM 0x2000
2461#define CT2_TERMINATE 0x4000
2462#define CT2_SENDSTATUS 0x8000
2463
2464/*
2465 * ct_status values are (mostly) the same as that for ct_entry.
2466 */
2467
2468/*
2469 * ct_scsi_status values- the low 8 bits are the normal SCSI status
2470 * we know and love. The upper 8 bits are validity markers for FCP_RSP_IU
2471 * fields.
2472 */
2473#define CT2_RSPLEN_VALID 0x0100
2474#define CT2_SNSLEN_VALID 0x0200
2475#define CT2_DATA_OVER 0x0400
2476#define CT2_DATA_UNDER 0x0800
2477
2478/*
2479 * ISP24XX CTIO
2480 */
2481#define MAXRESPLEN_24XX 24
2482typedef struct {
2483 isphdr_t ct_header;
2484 uint32_t ct_syshandle;
2485 uint16_t ct_nphdl; /* status on returned CTIOs */
2486 uint16_t ct_timeout;
2487 uint16_t ct_seg_count;
2488 uint8_t ct_vpidx;
2489 uint8_t ct_xflags;
2490 uint16_t ct_iid_lo; /* low 16 bits of portid */
2491 uint8_t ct_iid_hi; /* hi 8 bits of portid */
2492 uint8_t ct_reserved;
2493 uint32_t ct_rxid;
2494 uint16_t ct_senselen; /* mode 1 only */
2495 uint16_t ct_flags;
2496 uint32_t ct_resid; /* residual length */
2497 uint16_t ct_oxid;
2498 uint16_t ct_scsi_status; /* modes 0 && 1 only */
2499 union {
2500 struct {
2501 uint32_t reloff;
2502 uint32_t reserved0;
2503 uint32_t ct_xfrlen;
2504 uint32_t reserved1;
2505 ispds64_t ds;
2506 } m0;
2507 struct {
2508 uint16_t ct_resplen;
2509 uint16_t reserved;
2510 uint8_t ct_resp[MAXRESPLEN_24XX];
2511 } m1;
2512 struct {
2513 uint32_t reserved0;
2514 uint32_t reserved1;
2515 uint32_t ct_datalen;
2516 uint32_t reserved2;
2517 ispds64_t ct_fcp_rsp_iudata;
2518 } m2;
2519 } rsp;
2520} ct7_entry_t;
2521
2522/*
2523 * ct_flags values for CTIO7
2524 */
2525#define CT7_NO_DATA 0x0000
2526#define CT7_DATA_OUT 0x0001 /* *from* initiator */
2527#define CT7_DATA_IN 0x0002 /* *to* initiator */
2528#define CT7_DATAMASK 0x3
2529#define CT7_DSD_ENABLE 0x0004
2530#define CT7_CONF_STSFD 0x0010
2531#define CT7_EXPLCT_CONF 0x0020
2532#define CT7_FLAG_MODE0 0x0000
2533#define CT7_FLAG_MODE1 0x0040
2534#define CT7_FLAG_MODE2 0x0080
2535#define CT7_FLAG_MMASK 0x00C0
2536#define CT7_NOACK 0x0100
2537#define CT7_TASK_ATTR_SHIFT 9
2538#define CT7_CONFIRM 0x2000
2539#define CT7_TERMINATE 0x4000
2540#define CT7_SENDSTATUS 0x8000
2541
2542/*
2543 * Type 7 CTIO status codes
2544 */
2545#define CT7_OK 0x01 /* completed without error */
2546#define CT7_ABORTED 0x02 /* aborted by host */
2547#define CT7_ERR 0x04 /* see sense data for error */
2548#define CT7_INVAL 0x06 /* request for disabled lun */
2549#define CT7_INVRXID 0x08 /* Invalid RX_ID */
2550#define CT7_DATA_OVER 0x09 /* Data Overrun */
2551#define CT7_TIMEOUT 0x0B /* timed out */
2552#define CT7_RESET 0x0E /* LIP Rset Received */
2553#define CT7_BUS_ERROR 0x10 /* DMA PCI Error */
2554#define CT7_REASSY_ERR 0x11 /* DMA reassembly error */
2555#define CT7_DATA_UNDER 0x15 /* Data Underrun */
2556#define CT7_PORTUNAVAIL 0x28 /* port not available */
2557#define CT7_LOGOUT 0x29 /* port logout */
2558#define CT7_PORTCHANGED 0x2A /* port changed */
2559#define CT7_SRR 0x45 /* SRR Received */
2560
2561/*
2562 * Other 24XX related target IOCBs
2563 */
2564
2565/*
2566 * ABTS Received
2567 */
2568typedef struct {
2569 isphdr_t abts_header;
2570 uint8_t abts_reserved0[6];
2571 uint16_t abts_nphdl;
2572 uint16_t abts_reserved1;
2573 uint16_t abts_sof;
2574 uint32_t abts_rxid_abts;
2575 uint16_t abts_did_lo;
2576 uint8_t abts_did_hi;
2577 uint8_t abts_r_ctl;
2578 uint16_t abts_sid_lo;
2579 uint8_t abts_sid_hi;
2580 uint8_t abts_cs_ctl;
2581 uint16_t abts_fs_ctl;
2582 uint8_t abts_f_ctl;
2583 uint8_t abts_type;
2584 uint16_t abts_seq_cnt;
2585 uint8_t abts_df_ctl;
2586 uint8_t abts_seq_id;
2587 uint16_t abts_rx_id;
2588 uint16_t abts_ox_id;
2589 uint32_t abts_param;
2590 uint8_t abts_reserved2[16];
2591 uint32_t abts_rxid_task;
2592} abts_t;
2593
2594typedef struct {
2595 isphdr_t abts_rsp_header;
2596 uint32_t abts_rsp_handle;
2597 uint16_t abts_rsp_status;
2598 uint16_t abts_rsp_nphdl;
2599 uint16_t abts_rsp_ctl_flags;
2600 uint16_t abts_rsp_sof;
2601 uint32_t abts_rsp_rxid_abts;
2602 uint16_t abts_rsp_did_lo;
2603 uint8_t abts_rsp_did_hi;
2604 uint8_t abts_rsp_r_ctl;
2605 uint16_t abts_rsp_sid_lo;
2606 uint8_t abts_rsp_sid_hi;
2607 uint8_t abts_rsp_cs_ctl;
2608 uint16_t abts_rsp_f_ctl_lo;
2609 uint8_t abts_rsp_f_ctl_hi;
2610 uint8_t abts_rsp_type;
2611 uint16_t abts_rsp_seq_cnt;
2612 uint8_t abts_rsp_df_ctl;
2613 uint8_t abts_rsp_seq_id;
2614 uint16_t abts_rsp_rx_id;
2615 uint16_t abts_rsp_ox_id;
2616 uint32_t abts_rsp_param;
2617 union {
2618 struct {
2619 uint16_t reserved;
2620 uint8_t last_seq_id;
2621 uint8_t seq_id_valid;
2622 uint16_t aborted_rx_id;
2623 uint16_t aborted_ox_id;
2624 uint16_t high_seq_cnt;
2625 uint16_t low_seq_cnt;
2626 uint8_t reserved2[4];
2627 } ba_acc;
2628 struct {
2629 uint8_t vendor_unique;
2630 uint8_t explanation;
2631 uint8_t reason;
2632 uint8_t reserved;
2633 uint8_t reserved2[12];
2634 } ba_rjt;
2635 struct {
2636 uint8_t reserved[8];
2637 uint32_t subcode1;
2638 uint32_t subcode2;
2639 } rsp;
2640 uint8_t reserved[16];
2641 } abts_rsp_payload;
2642 uint32_t abts_rsp_rxid_task;
2643} abts_rsp_t;
2644
2645/* terminate this ABTS exchange */
2646#define ISP24XX_ABTS_RSP_TERMINATE 0x01
2647
2648#define ISP24XX_ABTS_RSP_COMPLETE 0x00
2649#define ISP24XX_ABTS_RSP_RESET 0x04
2650#define ISP24XX_ABTS_RSP_ABORTED 0x05
2651#define ISP24XX_ABTS_RSP_TIMEOUT 0x06
2652#define ISP24XX_ABTS_RSP_INVXID 0x08
2653#define ISP24XX_ABTS_RSP_LOGOUT 0x29
2654#define ISP24XX_ABTS_RSP_SUBCODE 0x31
2655
2656#define ISP24XX_NO_TASK 0xffffffff
2657
2658/*
2659 * Miscellaneous
2660 *
2661 * These are the limits of the number of dma segments we
2662 * can deal with based not on the size of the segment counter
2663 * (which is 16 bits), but on the size of the number of
2664 * queue entries field (which is 8 bits). We assume no
2665 * segments in the first queue entry, so we can either
2666 * have 7 dma segments per continuation entry or 5
2667 * (for 64 bit dma).. multiplying out by 254....
2668 */
2669#define ISP_NSEG_MAX 1778
2670#define ISP_NSEG64_MAX 1270
2671
2672#endif /* _ISPMBOX_H */