33
34static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
35 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
36 .calNumSamples = MIN_CAL_SAMPLES,
37 .calCountMax = PER_MAX_LOG_COUNT,
38 .calCollect = ar5416IQCalCollect,
39 .calPostProc = ar5416IQCalibration
40};
41static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
43 .calNumSamples = MIN_CAL_SAMPLES,
44 .calCountMax = PER_MIN_LOG_COUNT,
45 .calCollect = ar5416AdcGainCalCollect,
46 .calPostProc = ar5416AdcGainCalibration
47};
48static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
49 .calName = "ADC DC", .calType = ADC_DC_CAL,
50 .calNumSamples = MIN_CAL_SAMPLES,
51 .calCountMax = PER_MIN_LOG_COUNT,
52 .calCollect = ar5416AdcDcCalCollect,
53 .calPostProc = ar5416AdcDcCalibration
54};
55static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
57 .calNumSamples = MIN_CAL_SAMPLES,
58 .calCountMax = INIT_LOG_COUNT,
59 .calCollect = ar5416AdcDcCalCollect,
60 .calPostProc = ar5416AdcDcCalibration
61};
62
63static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
64static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);
65static void ar9280WriteIni(struct ath_hal *ah,
66 const struct ieee80211_channel *chan);
67
68static void
69ar9280AniSetup(struct ath_hal *ah)
70{
71 /* NB: disable ANI for reliable RIFS rx */
72 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
73}
74
75/*
76 * Attach for an AR9280 part.
77 */
78static struct ath_hal *
79ar9280Attach(uint16_t devid, HAL_SOFTC sc,
80 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
81 HAL_STATUS *status)
82{
83 struct ath_hal_9280 *ahp9280;
84 struct ath_hal_5212 *ahp;
85 struct ath_hal *ah;
86 uint32_t val;
87 HAL_STATUS ecode;
88 HAL_BOOL rfStatus;
89
90 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
91 __func__, sc, (void*) st, (void*) sh);
92
93 /* NB: memory is returned zero'd */
94 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));
95 if (ahp9280 == AH_NULL) {
96 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
97 "%s: cannot allocate memory for state block\n", __func__);
98 *status = HAL_ENOMEM;
99 return AH_NULL;
100 }
101 ahp = AH5212(ahp9280);
102 ah = &ahp->ah_priv.h;
103
104 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
105
106 /* XXX override with 9280 specific state */
107 /* override 5416 methods for our needs */
108 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
109 ah->ah_configPCIE = ar9280ConfigPCIE;
110
111 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
112 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
113 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
114 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
115 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
116
117 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
118 AH5416(ah)->ah_writeIni = ar9280WriteIni;
119 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
120 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
121
122 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
123 /* reset chip */
124 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
125 __func__);
126 ecode = HAL_EIO;
127 goto bad;
128 }
129
130 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
131 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
132 __func__);
133 ecode = HAL_EIO;
134 goto bad;
135 }
136 /* Read Revisions from Chips before taking out of reset */
137 val = OS_REG_READ(ah, AR_SREV);
138 HALDEBUG(ah, HAL_DEBUG_ATTACH,
139 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
140 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
141 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
142 /* NB: include chip type to differentiate from pre-Sowl versions */
143 AH_PRIVATE(ah)->ah_macVersion =
144 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
145 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
146 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
147
148 /* setup common ini data; rf backends handle remainder */
149 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
150 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
151 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
152 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
153 ar9280PciePhy_clkreq_always_on_L1_v2, 2);
154 HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
155 ar9280Modes_fast_clock_v2, 3);
156 } else {
157 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
158 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
159 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
160 ar9280PciePhy_v1, 2);
161 }
162 ar5416AttachPCIE(ah);
163
164 ecode = ath_hal_v14EepromAttach(ah);
165 if (ecode != HAL_OK)
166 goto bad;
167
168 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
169 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
170 ecode = HAL_EIO;
171 goto bad;
172 }
173
174 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
175
176 if (!ar5212ChipTest(ah)) {
177 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
178 __func__);
179 ecode = HAL_ESELFTEST;
180 goto bad;
181 }
182
183 /*
184 * Set correct Baseband to analog shift
185 * setting to access analog chips.
186 */
187 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
188
189 /* Read Radio Chip Rev Extract */
190 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
191 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
192 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
193 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
194 break;
195 default:
196 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
197 AH_PRIVATE(ah)->ah_analog5GhzRev =
198 AR_RAD5133_SREV_MAJOR;
199 break;
200 }
201#ifdef AH_DEBUG
202 HALDEBUG(ah, HAL_DEBUG_ANY,
203 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
204 "this driver\n", __func__,
205 AH_PRIVATE(ah)->ah_analog5GhzRev);
206 ecode = HAL_ENOTSUPP;
207 goto bad;
208#endif
209 }
210 rfStatus = ar9280RfAttach(ah, &ecode);
211 if (!rfStatus) {
212 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
213 __func__, ecode);
214 goto bad;
215 }
216
217 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
218 /* setup rxgain table */
219 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
220 case AR5416_EEP_RXGAIN_13dB_BACKOFF:
221 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
222 ar9280Modes_backoff_13db_rxgain_v2, 6);
223 break;
224 case AR5416_EEP_RXGAIN_23dB_BACKOFF:
225 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
226 ar9280Modes_backoff_23db_rxgain_v2, 6);
227 break;
228 case AR5416_EEP_RXGAIN_ORIG:
229 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
230 ar9280Modes_original_rxgain_v2, 6);
231 break;
232 default:
233 HALASSERT(AH_FALSE);
234 goto bad; /* XXX ? try to continue */
235 }
236 }
237 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
238 /* setp txgain table */
239 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
240 case AR5416_EEP_TXGAIN_HIGH_POWER:
241 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
242 ar9280Modes_high_power_tx_gain_v2, 6);
243 break;
244 case AR5416_EEP_TXGAIN_ORIG:
245 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
246 ar9280Modes_original_tx_gain_v2, 6);
247 break;
248 default:
249 HALASSERT(AH_FALSE);
250 goto bad; /* XXX ? try to continue */
251 }
252 }
253
254 /*
255 * Got everything we need now to setup the capabilities.
256 */
257 if (!ar9280FillCapabilityInfo(ah)) {
258 ecode = HAL_EEREAD;
259 goto bad;
260 }
261
262 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
263 if (ecode != HAL_OK) {
264 HALDEBUG(ah, HAL_DEBUG_ANY,
265 "%s: error getting mac address from EEPROM\n", __func__);
266 goto bad;
267 }
268 /* XXX How about the serial number ? */
269 /* Read Reg Domain */
270 AH_PRIVATE(ah)->ah_currentRD =
271 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
272
273 /*
274 * ah_miscMode is populated by ar5416FillCapabilityInfo()
275 * starting from griffin. Set here to make sure that
276 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
277 * placed into hardware.
278 */
279 if (ahp->ah_miscMode != 0)
280 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
281
282 ar9280AniSetup(ah); /* Anti Noise Immunity */
283 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
284
285 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
286
287 return ah;
288bad:
289 if (ah != AH_NULL)
290 ah->ah_detach(ah);
291 if (status)
292 *status = ecode;
293 return AH_NULL;
294}
295
296static void
297ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
298{
299 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
300 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
301 OS_DELAY(1000);
302 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
303 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
304 }
305}
306
307static void
308ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
309{
310 u_int modesIndex, freqIndex;
311 int regWrites = 0;
312
313 /* Setup the indices for the next set of register array writes */
314 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
315 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
316 freqIndex = 2;
317 if (IEEE80211_IS_CHAN_HT40(chan))
318 modesIndex = 3;
319 else if (IEEE80211_IS_CHAN_108G(chan))
320 modesIndex = 5;
321 else
322 modesIndex = 4;
323 } else {
324 freqIndex = 1;
325 if (IEEE80211_IS_CHAN_HT40(chan) ||
326 IEEE80211_IS_CHAN_TURBO(chan))
327 modesIndex = 2;
328 else
329 modesIndex = 1;
330 }
331
332 /* Set correct Baseband to analog shift setting to access analog chips. */
333 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
334 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
335
336 /* XXX Merlin ini fixups */
337 /* XXX Merlin 100us delay for shift registers */
338 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
339 modesIndex, regWrites);
340 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
341 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
342 modesIndex, regWrites);
343 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
344 modesIndex, regWrites);
345 }
346 /* XXX Merlin 100us delay for shift registers */
347 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
348 1, regWrites);
349
350 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
351 /* 5GHz channels w/ Fast Clock use different modal values */
352 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
353 modesIndex, regWrites);
354 }
355}
356
357#define AR_BASE_FREQ_2GHZ 2300
358#define AR_BASE_FREQ_5GHZ 4900
359#define AR_SPUR_FEEQ_BOUND_HT40 19
360#define AR_SPUR_FEEQ_BOUND_HT20 10
361
362void
363ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
364{
365 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
366 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
367 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
368 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
369 static int inc[4] = { 0, 100, 0, 0 };
370
371 int bb_spur = AR_NO_SPUR;
372 int freq;
373 int bin, cur_bin;
374 int bb_spur_off, spur_subchannel_sd;
375 int spur_freq_sd;
376 int spur_delta_phase;
377 int denominator;
378 int upper, lower, cur_vit_mask;
379 int tmp, newVal;
380 int i;
381 CHAN_CENTERS centers;
382
383 int8_t mask_m[123];
384 int8_t mask_p[123];
385 int8_t mask_amt;
386 int tmp_mask;
387 int cur_bb_spur;
388 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
389
390 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
391 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
392
393 ar5416GetChannelCenters(ah, chan, ¢ers);
394 freq = centers.synth_center;
395
396 /*
397 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
398 * otherwise spur is out-of-band and can be ignored.
399 */
400 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
401 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
402 /* Get actual spur freq in MHz from EEPROM read value */
403 if (is2GHz) {
404 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
405 } else {
406 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
407 }
408
409 if (AR_NO_SPUR == cur_bb_spur)
410 break;
411 cur_bb_spur = cur_bb_spur - freq;
412
413 if (IEEE80211_IS_CHAN_HT40(chan)) {
414 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
415 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
416 bb_spur = cur_bb_spur;
417 break;
418 }
419 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
420 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
421 bb_spur = cur_bb_spur;
422 break;
423 }
424 }
425
426 if (AR_NO_SPUR == bb_spur) {
427#if 1
428 /*
429 * MRC CCK can interfere with beacon detection and cause deaf/mute.
430 * Disable MRC CCK for now.
431 */
432 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
433#else
434 /* Enable MRC CCK if no spur is found in this channel. */
435 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
436#endif
437 return;
438 } else {
439 /*
440 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
441 * is found in this channel.
442 */
443 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
444 }
445
446 bin = bb_spur * 320;
447
448 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
449
450 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
451 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
452 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
453 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
454 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
455
456 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
457 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
458 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
459 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
460 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
461 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
462
463 /* Pick control or extn channel to cancel the spur */
464 if (IEEE80211_IS_CHAN_HT40(chan)) {
465 if (bb_spur < 0) {
466 spur_subchannel_sd = 1;
467 bb_spur_off = bb_spur + 10;
468 } else {
469 spur_subchannel_sd = 0;
470 bb_spur_off = bb_spur - 10;
471 }
472 } else {
473 spur_subchannel_sd = 0;
474 bb_spur_off = bb_spur;
475 }
476
477 /*
478 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
479 * /80 for dyn2040.
480 */
481 if (IEEE80211_IS_CHAN_HT40(chan))
482 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
483 else
484 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
485
486 /*
487 * in 11A mode the denominator of spur_freq_sd should be 40 and
488 * it should be 44 in 11G
489 */
490 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40;
491 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
492
493 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
494 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
495 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
496 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
497
498 /* Choose to cancel between control and extension channels */
499 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
500 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
501
502 /*
503 * ============================================
504 * Set Pilot and Channel Masks
505 *
506 * pilot mask 1 [31:0] = +6..-26, no 0 bin
507 * pilot mask 2 [19:0] = +26..+7
508 *
509 * channel mask 1 [31:0] = +6..-26, no 0 bin
510 * channel mask 2 [19:0] = +26..+7
511 */
512 cur_bin = -6000;
513 upper = bin + 100;
514 lower = bin - 100;
515
516 for (i = 0; i < 4; i++) {
517 int pilot_mask = 0;
518 int chan_mask = 0;
519 int bp = 0;
520 for (bp = 0; bp < 30; bp++) {
521 if ((cur_bin > lower) && (cur_bin < upper)) {
522 pilot_mask = pilot_mask | 0x1 << bp;
523 chan_mask = chan_mask | 0x1 << bp;
524 }
525 cur_bin += 100;
526 }
527 cur_bin += inc[i];
528 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
529 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
530 }
531
532 /* =================================================
533 * viterbi mask 1 based on channel magnitude
534 * four levels 0-3
535 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
536 * [1 2 2 1] for -9.6 or [1 2 1] for +16
537 * - enable_mask_ppm, all bins move with freq
538 *
539 * - mask_select, 8 bits for rates (reg 67,0x990c)
540 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
541 * choose which mask to use mask or mask2
542 */
543
544 /*
545 * viterbi mask 2 2nd set for per data rate puncturing
546 * four levels 0-3
547 * - mask_select, 8 bits for rates (reg 67)
548 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
549 * [1 2 2 1] for -9.6 or [1 2 1] for +16
550 */
551 cur_vit_mask = 6100;
552 upper = bin + 120;
553 lower = bin - 120;
554
555 for (i = 0; i < 123; i++) {
556 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
557 if ((abs(cur_vit_mask - bin)) < 75) {
558 mask_amt = 1;
559 } else {
560 mask_amt = 0;
561 }
562 if (cur_vit_mask < 0) {
563 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
564 } else {
565 mask_p[cur_vit_mask / 100] = mask_amt;
566 }
567 }
568 cur_vit_mask -= 100;
569 }
570
571 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
572 | (mask_m[48] << 26) | (mask_m[49] << 24)
573 | (mask_m[50] << 22) | (mask_m[51] << 20)
574 | (mask_m[52] << 18) | (mask_m[53] << 16)
575 | (mask_m[54] << 14) | (mask_m[55] << 12)
576 | (mask_m[56] << 10) | (mask_m[57] << 8)
577 | (mask_m[58] << 6) | (mask_m[59] << 4)
578 | (mask_m[60] << 2) | (mask_m[61] << 0);
579 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
580 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
581
582 tmp_mask = (mask_m[31] << 28)
583 | (mask_m[32] << 26) | (mask_m[33] << 24)
584 | (mask_m[34] << 22) | (mask_m[35] << 20)
585 | (mask_m[36] << 18) | (mask_m[37] << 16)
586 | (mask_m[48] << 14) | (mask_m[39] << 12)
587 | (mask_m[40] << 10) | (mask_m[41] << 8)
588 | (mask_m[42] << 6) | (mask_m[43] << 4)
589 | (mask_m[44] << 2) | (mask_m[45] << 0);
590 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
591 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
592
593 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
594 | (mask_m[18] << 26) | (mask_m[18] << 24)
595 | (mask_m[20] << 22) | (mask_m[20] << 20)
596 | (mask_m[22] << 18) | (mask_m[22] << 16)
597 | (mask_m[24] << 14) | (mask_m[24] << 12)
598 | (mask_m[25] << 10) | (mask_m[26] << 8)
599 | (mask_m[27] << 6) | (mask_m[28] << 4)
600 | (mask_m[29] << 2) | (mask_m[30] << 0);
601 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
602 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
603
604 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
605 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
606 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
607 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
608 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
609 | (mask_m[10] << 10) | (mask_m[11] << 8)
610 | (mask_m[12] << 6) | (mask_m[13] << 4)
611 | (mask_m[14] << 2) | (mask_m[15] << 0);
612 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
613 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
614
615 tmp_mask = (mask_p[15] << 28)
616 | (mask_p[14] << 26) | (mask_p[13] << 24)
617 | (mask_p[12] << 22) | (mask_p[11] << 20)
618 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
619 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
620 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
621 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
622 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
623 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
624 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
625
626 tmp_mask = (mask_p[30] << 28)
627 | (mask_p[29] << 26) | (mask_p[28] << 24)
628 | (mask_p[27] << 22) | (mask_p[26] << 20)
629 | (mask_p[25] << 18) | (mask_p[24] << 16)
630 | (mask_p[23] << 14) | (mask_p[22] << 12)
631 | (mask_p[21] << 10) | (mask_p[20] << 8)
632 | (mask_p[19] << 6) | (mask_p[18] << 4)
633 | (mask_p[17] << 2) | (mask_p[16] << 0);
634 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
635 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
636
637 tmp_mask = (mask_p[45] << 28)
638 | (mask_p[44] << 26) | (mask_p[43] << 24)
639 | (mask_p[42] << 22) | (mask_p[41] << 20)
640 | (mask_p[40] << 18) | (mask_p[39] << 16)
641 | (mask_p[38] << 14) | (mask_p[37] << 12)
642 | (mask_p[36] << 10) | (mask_p[35] << 8)
643 | (mask_p[34] << 6) | (mask_p[33] << 4)
644 | (mask_p[32] << 2) | (mask_p[31] << 0);
645 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
646 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
647
648 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
649 | (mask_p[59] << 26) | (mask_p[58] << 24)
650 | (mask_p[57] << 22) | (mask_p[56] << 20)
651 | (mask_p[55] << 18) | (mask_p[54] << 16)
652 | (mask_p[53] << 14) | (mask_p[52] << 12)
653 | (mask_p[51] << 10) | (mask_p[50] << 8)
654 | (mask_p[49] << 6) | (mask_p[48] << 4)
655 | (mask_p[47] << 2) | (mask_p[46] << 0);
656 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
657 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
658}
659
660/*
661 * Fill all software cached or static hardware state information.
662 * Return failure if capabilities are to come from EEPROM and
663 * cannot be read.
664 */
665static HAL_BOOL
666ar9280FillCapabilityInfo(struct ath_hal *ah)
667{
668 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
669
670 if (!ar5416FillCapabilityInfo(ah))
671 return AH_FALSE;
672 pCap->halNumGpioPins = 10;
673 pCap->halWowSupport = AH_TRUE;
674 pCap->halWowMatchPatternExact = AH_TRUE;
675#if 0
676 pCap->halWowMatchPatternDword = AH_TRUE;
677#endif
678 pCap->halCSTSupport = AH_TRUE;
679 pCap->halRifsRxSupport = AH_TRUE;
680 pCap->halRifsTxSupport = AH_TRUE;
681 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
682 pCap->halExtChanDfsSupport = AH_TRUE;
683#if 0
684 /* XXX bluetooth */
685 pCap->halBtCoexSupport = AH_TRUE;
686#endif
687 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
688#if 0
689 pCap->hal4kbSplitTransSupport = AH_FALSE;
690#endif
691 pCap->halRxStbcSupport = 1;
692 pCap->halTxStbcSupport = 1;
693
694 return AH_TRUE;
695}
696
697HAL_BOOL
698ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
699{
700#define ANTENNA0_CHAINMASK 0x1
701#define ANTENNA1_CHAINMASK 0x2
702 struct ath_hal_5416 *ahp = AH5416(ah);
703
704 /* Antenna selection is done by setting the tx/rx chainmasks approp. */
705 switch (settings) {
706 case HAL_ANT_FIXED_A:
707 /* Enable first antenna only */
708 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
709 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
710 break;
711 case HAL_ANT_FIXED_B:
712 /* Enable second antenna only, after checking capability */
713 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
714 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
715 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
716 break;
717 case HAL_ANT_VARIABLE:
718 /* Restore original chainmask settings */
719 /* XXX */
720 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
721 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
722 break;
723 }
724 return AH_TRUE;
725#undef ANTENNA0_CHAINMASK
726#undef ANTENNA1_CHAINMASK
727}
728
729static const char*
730ar9280Probe(uint16_t vendorid, uint16_t devid)
731{
732 if (vendorid == ATHEROS_VENDOR_ID &&
733 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
734 return "Atheros 9280";
735 return AH_NULL;
736}
737AH_CHIP(AR9280, ar9280Probe, ar9280Attach);
| 33
34static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
35 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
36 .calNumSamples = MIN_CAL_SAMPLES,
37 .calCountMax = PER_MAX_LOG_COUNT,
38 .calCollect = ar5416IQCalCollect,
39 .calPostProc = ar5416IQCalibration
40};
41static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
43 .calNumSamples = MIN_CAL_SAMPLES,
44 .calCountMax = PER_MIN_LOG_COUNT,
45 .calCollect = ar5416AdcGainCalCollect,
46 .calPostProc = ar5416AdcGainCalibration
47};
48static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
49 .calName = "ADC DC", .calType = ADC_DC_CAL,
50 .calNumSamples = MIN_CAL_SAMPLES,
51 .calCountMax = PER_MIN_LOG_COUNT,
52 .calCollect = ar5416AdcDcCalCollect,
53 .calPostProc = ar5416AdcDcCalibration
54};
55static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
57 .calNumSamples = MIN_CAL_SAMPLES,
58 .calCountMax = INIT_LOG_COUNT,
59 .calCollect = ar5416AdcDcCalCollect,
60 .calPostProc = ar5416AdcDcCalibration
61};
62
63static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
64static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);
65static void ar9280WriteIni(struct ath_hal *ah,
66 const struct ieee80211_channel *chan);
67
68static void
69ar9280AniSetup(struct ath_hal *ah)
70{
71 /* NB: disable ANI for reliable RIFS rx */
72 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
73}
74
75/*
76 * Attach for an AR9280 part.
77 */
78static struct ath_hal *
79ar9280Attach(uint16_t devid, HAL_SOFTC sc,
80 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
81 HAL_STATUS *status)
82{
83 struct ath_hal_9280 *ahp9280;
84 struct ath_hal_5212 *ahp;
85 struct ath_hal *ah;
86 uint32_t val;
87 HAL_STATUS ecode;
88 HAL_BOOL rfStatus;
89
90 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
91 __func__, sc, (void*) st, (void*) sh);
92
93 /* NB: memory is returned zero'd */
94 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));
95 if (ahp9280 == AH_NULL) {
96 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
97 "%s: cannot allocate memory for state block\n", __func__);
98 *status = HAL_ENOMEM;
99 return AH_NULL;
100 }
101 ahp = AH5212(ahp9280);
102 ah = &ahp->ah_priv.h;
103
104 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
105
106 /* XXX override with 9280 specific state */
107 /* override 5416 methods for our needs */
108 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
109 ah->ah_configPCIE = ar9280ConfigPCIE;
110
111 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
112 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
113 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
114 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
115 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
116
117 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
118 AH5416(ah)->ah_writeIni = ar9280WriteIni;
119 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
120 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
121
122 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
123 /* reset chip */
124 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
125 __func__);
126 ecode = HAL_EIO;
127 goto bad;
128 }
129
130 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
131 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
132 __func__);
133 ecode = HAL_EIO;
134 goto bad;
135 }
136 /* Read Revisions from Chips before taking out of reset */
137 val = OS_REG_READ(ah, AR_SREV);
138 HALDEBUG(ah, HAL_DEBUG_ATTACH,
139 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
140 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
141 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
142 /* NB: include chip type to differentiate from pre-Sowl versions */
143 AH_PRIVATE(ah)->ah_macVersion =
144 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
145 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
146 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
147
148 /* setup common ini data; rf backends handle remainder */
149 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
150 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
151 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
152 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
153 ar9280PciePhy_clkreq_always_on_L1_v2, 2);
154 HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
155 ar9280Modes_fast_clock_v2, 3);
156 } else {
157 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
158 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
159 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
160 ar9280PciePhy_v1, 2);
161 }
162 ar5416AttachPCIE(ah);
163
164 ecode = ath_hal_v14EepromAttach(ah);
165 if (ecode != HAL_OK)
166 goto bad;
167
168 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
169 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
170 ecode = HAL_EIO;
171 goto bad;
172 }
173
174 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
175
176 if (!ar5212ChipTest(ah)) {
177 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
178 __func__);
179 ecode = HAL_ESELFTEST;
180 goto bad;
181 }
182
183 /*
184 * Set correct Baseband to analog shift
185 * setting to access analog chips.
186 */
187 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
188
189 /* Read Radio Chip Rev Extract */
190 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
191 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
192 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
193 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
194 break;
195 default:
196 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
197 AH_PRIVATE(ah)->ah_analog5GhzRev =
198 AR_RAD5133_SREV_MAJOR;
199 break;
200 }
201#ifdef AH_DEBUG
202 HALDEBUG(ah, HAL_DEBUG_ANY,
203 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
204 "this driver\n", __func__,
205 AH_PRIVATE(ah)->ah_analog5GhzRev);
206 ecode = HAL_ENOTSUPP;
207 goto bad;
208#endif
209 }
210 rfStatus = ar9280RfAttach(ah, &ecode);
211 if (!rfStatus) {
212 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
213 __func__, ecode);
214 goto bad;
215 }
216
217 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
218 /* setup rxgain table */
219 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
220 case AR5416_EEP_RXGAIN_13dB_BACKOFF:
221 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
222 ar9280Modes_backoff_13db_rxgain_v2, 6);
223 break;
224 case AR5416_EEP_RXGAIN_23dB_BACKOFF:
225 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
226 ar9280Modes_backoff_23db_rxgain_v2, 6);
227 break;
228 case AR5416_EEP_RXGAIN_ORIG:
229 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
230 ar9280Modes_original_rxgain_v2, 6);
231 break;
232 default:
233 HALASSERT(AH_FALSE);
234 goto bad; /* XXX ? try to continue */
235 }
236 }
237 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
238 /* setp txgain table */
239 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
240 case AR5416_EEP_TXGAIN_HIGH_POWER:
241 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
242 ar9280Modes_high_power_tx_gain_v2, 6);
243 break;
244 case AR5416_EEP_TXGAIN_ORIG:
245 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
246 ar9280Modes_original_tx_gain_v2, 6);
247 break;
248 default:
249 HALASSERT(AH_FALSE);
250 goto bad; /* XXX ? try to continue */
251 }
252 }
253
254 /*
255 * Got everything we need now to setup the capabilities.
256 */
257 if (!ar9280FillCapabilityInfo(ah)) {
258 ecode = HAL_EEREAD;
259 goto bad;
260 }
261
262 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
263 if (ecode != HAL_OK) {
264 HALDEBUG(ah, HAL_DEBUG_ANY,
265 "%s: error getting mac address from EEPROM\n", __func__);
266 goto bad;
267 }
268 /* XXX How about the serial number ? */
269 /* Read Reg Domain */
270 AH_PRIVATE(ah)->ah_currentRD =
271 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
272
273 /*
274 * ah_miscMode is populated by ar5416FillCapabilityInfo()
275 * starting from griffin. Set here to make sure that
276 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
277 * placed into hardware.
278 */
279 if (ahp->ah_miscMode != 0)
280 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
281
282 ar9280AniSetup(ah); /* Anti Noise Immunity */
283 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
284
285 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
286
287 return ah;
288bad:
289 if (ah != AH_NULL)
290 ah->ah_detach(ah);
291 if (status)
292 *status = ecode;
293 return AH_NULL;
294}
295
296static void
297ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
298{
299 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
300 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
301 OS_DELAY(1000);
302 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
303 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
304 }
305}
306
307static void
308ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
309{
310 u_int modesIndex, freqIndex;
311 int regWrites = 0;
312
313 /* Setup the indices for the next set of register array writes */
314 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
315 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
316 freqIndex = 2;
317 if (IEEE80211_IS_CHAN_HT40(chan))
318 modesIndex = 3;
319 else if (IEEE80211_IS_CHAN_108G(chan))
320 modesIndex = 5;
321 else
322 modesIndex = 4;
323 } else {
324 freqIndex = 1;
325 if (IEEE80211_IS_CHAN_HT40(chan) ||
326 IEEE80211_IS_CHAN_TURBO(chan))
327 modesIndex = 2;
328 else
329 modesIndex = 1;
330 }
331
332 /* Set correct Baseband to analog shift setting to access analog chips. */
333 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
334 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
335
336 /* XXX Merlin ini fixups */
337 /* XXX Merlin 100us delay for shift registers */
338 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
339 modesIndex, regWrites);
340 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
341 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
342 modesIndex, regWrites);
343 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
344 modesIndex, regWrites);
345 }
346 /* XXX Merlin 100us delay for shift registers */
347 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
348 1, regWrites);
349
350 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
351 /* 5GHz channels w/ Fast Clock use different modal values */
352 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
353 modesIndex, regWrites);
354 }
355}
356
357#define AR_BASE_FREQ_2GHZ 2300
358#define AR_BASE_FREQ_5GHZ 4900
359#define AR_SPUR_FEEQ_BOUND_HT40 19
360#define AR_SPUR_FEEQ_BOUND_HT20 10
361
362void
363ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
364{
365 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
366 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
367 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
368 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
369 static int inc[4] = { 0, 100, 0, 0 };
370
371 int bb_spur = AR_NO_SPUR;
372 int freq;
373 int bin, cur_bin;
374 int bb_spur_off, spur_subchannel_sd;
375 int spur_freq_sd;
376 int spur_delta_phase;
377 int denominator;
378 int upper, lower, cur_vit_mask;
379 int tmp, newVal;
380 int i;
381 CHAN_CENTERS centers;
382
383 int8_t mask_m[123];
384 int8_t mask_p[123];
385 int8_t mask_amt;
386 int tmp_mask;
387 int cur_bb_spur;
388 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
389
390 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
391 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
392
393 ar5416GetChannelCenters(ah, chan, ¢ers);
394 freq = centers.synth_center;
395
396 /*
397 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
398 * otherwise spur is out-of-band and can be ignored.
399 */
400 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
401 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
402 /* Get actual spur freq in MHz from EEPROM read value */
403 if (is2GHz) {
404 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
405 } else {
406 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
407 }
408
409 if (AR_NO_SPUR == cur_bb_spur)
410 break;
411 cur_bb_spur = cur_bb_spur - freq;
412
413 if (IEEE80211_IS_CHAN_HT40(chan)) {
414 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
415 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
416 bb_spur = cur_bb_spur;
417 break;
418 }
419 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
420 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
421 bb_spur = cur_bb_spur;
422 break;
423 }
424 }
425
426 if (AR_NO_SPUR == bb_spur) {
427#if 1
428 /*
429 * MRC CCK can interfere with beacon detection and cause deaf/mute.
430 * Disable MRC CCK for now.
431 */
432 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
433#else
434 /* Enable MRC CCK if no spur is found in this channel. */
435 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
436#endif
437 return;
438 } else {
439 /*
440 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
441 * is found in this channel.
442 */
443 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
444 }
445
446 bin = bb_spur * 320;
447
448 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
449
450 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
451 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
452 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
453 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
454 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
455
456 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
457 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
458 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
459 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
460 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
461 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
462
463 /* Pick control or extn channel to cancel the spur */
464 if (IEEE80211_IS_CHAN_HT40(chan)) {
465 if (bb_spur < 0) {
466 spur_subchannel_sd = 1;
467 bb_spur_off = bb_spur + 10;
468 } else {
469 spur_subchannel_sd = 0;
470 bb_spur_off = bb_spur - 10;
471 }
472 } else {
473 spur_subchannel_sd = 0;
474 bb_spur_off = bb_spur;
475 }
476
477 /*
478 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
479 * /80 for dyn2040.
480 */
481 if (IEEE80211_IS_CHAN_HT40(chan))
482 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
483 else
484 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
485
486 /*
487 * in 11A mode the denominator of spur_freq_sd should be 40 and
488 * it should be 44 in 11G
489 */
490 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40;
491 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
492
493 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
494 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
495 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
496 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
497
498 /* Choose to cancel between control and extension channels */
499 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
500 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
501
502 /*
503 * ============================================
504 * Set Pilot and Channel Masks
505 *
506 * pilot mask 1 [31:0] = +6..-26, no 0 bin
507 * pilot mask 2 [19:0] = +26..+7
508 *
509 * channel mask 1 [31:0] = +6..-26, no 0 bin
510 * channel mask 2 [19:0] = +26..+7
511 */
512 cur_bin = -6000;
513 upper = bin + 100;
514 lower = bin - 100;
515
516 for (i = 0; i < 4; i++) {
517 int pilot_mask = 0;
518 int chan_mask = 0;
519 int bp = 0;
520 for (bp = 0; bp < 30; bp++) {
521 if ((cur_bin > lower) && (cur_bin < upper)) {
522 pilot_mask = pilot_mask | 0x1 << bp;
523 chan_mask = chan_mask | 0x1 << bp;
524 }
525 cur_bin += 100;
526 }
527 cur_bin += inc[i];
528 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
529 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
530 }
531
532 /* =================================================
533 * viterbi mask 1 based on channel magnitude
534 * four levels 0-3
535 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
536 * [1 2 2 1] for -9.6 or [1 2 1] for +16
537 * - enable_mask_ppm, all bins move with freq
538 *
539 * - mask_select, 8 bits for rates (reg 67,0x990c)
540 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
541 * choose which mask to use mask or mask2
542 */
543
544 /*
545 * viterbi mask 2 2nd set for per data rate puncturing
546 * four levels 0-3
547 * - mask_select, 8 bits for rates (reg 67)
548 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
549 * [1 2 2 1] for -9.6 or [1 2 1] for +16
550 */
551 cur_vit_mask = 6100;
552 upper = bin + 120;
553 lower = bin - 120;
554
555 for (i = 0; i < 123; i++) {
556 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
557 if ((abs(cur_vit_mask - bin)) < 75) {
558 mask_amt = 1;
559 } else {
560 mask_amt = 0;
561 }
562 if (cur_vit_mask < 0) {
563 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
564 } else {
565 mask_p[cur_vit_mask / 100] = mask_amt;
566 }
567 }
568 cur_vit_mask -= 100;
569 }
570
571 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
572 | (mask_m[48] << 26) | (mask_m[49] << 24)
573 | (mask_m[50] << 22) | (mask_m[51] << 20)
574 | (mask_m[52] << 18) | (mask_m[53] << 16)
575 | (mask_m[54] << 14) | (mask_m[55] << 12)
576 | (mask_m[56] << 10) | (mask_m[57] << 8)
577 | (mask_m[58] << 6) | (mask_m[59] << 4)
578 | (mask_m[60] << 2) | (mask_m[61] << 0);
579 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
580 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
581
582 tmp_mask = (mask_m[31] << 28)
583 | (mask_m[32] << 26) | (mask_m[33] << 24)
584 | (mask_m[34] << 22) | (mask_m[35] << 20)
585 | (mask_m[36] << 18) | (mask_m[37] << 16)
586 | (mask_m[48] << 14) | (mask_m[39] << 12)
587 | (mask_m[40] << 10) | (mask_m[41] << 8)
588 | (mask_m[42] << 6) | (mask_m[43] << 4)
589 | (mask_m[44] << 2) | (mask_m[45] << 0);
590 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
591 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
592
593 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
594 | (mask_m[18] << 26) | (mask_m[18] << 24)
595 | (mask_m[20] << 22) | (mask_m[20] << 20)
596 | (mask_m[22] << 18) | (mask_m[22] << 16)
597 | (mask_m[24] << 14) | (mask_m[24] << 12)
598 | (mask_m[25] << 10) | (mask_m[26] << 8)
599 | (mask_m[27] << 6) | (mask_m[28] << 4)
600 | (mask_m[29] << 2) | (mask_m[30] << 0);
601 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
602 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
603
604 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
605 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
606 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
607 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
608 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
609 | (mask_m[10] << 10) | (mask_m[11] << 8)
610 | (mask_m[12] << 6) | (mask_m[13] << 4)
611 | (mask_m[14] << 2) | (mask_m[15] << 0);
612 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
613 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
614
615 tmp_mask = (mask_p[15] << 28)
616 | (mask_p[14] << 26) | (mask_p[13] << 24)
617 | (mask_p[12] << 22) | (mask_p[11] << 20)
618 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
619 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
620 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
621 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
622 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
623 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
624 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
625
626 tmp_mask = (mask_p[30] << 28)
627 | (mask_p[29] << 26) | (mask_p[28] << 24)
628 | (mask_p[27] << 22) | (mask_p[26] << 20)
629 | (mask_p[25] << 18) | (mask_p[24] << 16)
630 | (mask_p[23] << 14) | (mask_p[22] << 12)
631 | (mask_p[21] << 10) | (mask_p[20] << 8)
632 | (mask_p[19] << 6) | (mask_p[18] << 4)
633 | (mask_p[17] << 2) | (mask_p[16] << 0);
634 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
635 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
636
637 tmp_mask = (mask_p[45] << 28)
638 | (mask_p[44] << 26) | (mask_p[43] << 24)
639 | (mask_p[42] << 22) | (mask_p[41] << 20)
640 | (mask_p[40] << 18) | (mask_p[39] << 16)
641 | (mask_p[38] << 14) | (mask_p[37] << 12)
642 | (mask_p[36] << 10) | (mask_p[35] << 8)
643 | (mask_p[34] << 6) | (mask_p[33] << 4)
644 | (mask_p[32] << 2) | (mask_p[31] << 0);
645 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
646 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
647
648 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
649 | (mask_p[59] << 26) | (mask_p[58] << 24)
650 | (mask_p[57] << 22) | (mask_p[56] << 20)
651 | (mask_p[55] << 18) | (mask_p[54] << 16)
652 | (mask_p[53] << 14) | (mask_p[52] << 12)
653 | (mask_p[51] << 10) | (mask_p[50] << 8)
654 | (mask_p[49] << 6) | (mask_p[48] << 4)
655 | (mask_p[47] << 2) | (mask_p[46] << 0);
656 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
657 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
658}
659
660/*
661 * Fill all software cached or static hardware state information.
662 * Return failure if capabilities are to come from EEPROM and
663 * cannot be read.
664 */
665static HAL_BOOL
666ar9280FillCapabilityInfo(struct ath_hal *ah)
667{
668 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
669
670 if (!ar5416FillCapabilityInfo(ah))
671 return AH_FALSE;
672 pCap->halNumGpioPins = 10;
673 pCap->halWowSupport = AH_TRUE;
674 pCap->halWowMatchPatternExact = AH_TRUE;
675#if 0
676 pCap->halWowMatchPatternDword = AH_TRUE;
677#endif
678 pCap->halCSTSupport = AH_TRUE;
679 pCap->halRifsRxSupport = AH_TRUE;
680 pCap->halRifsTxSupport = AH_TRUE;
681 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
682 pCap->halExtChanDfsSupport = AH_TRUE;
683#if 0
684 /* XXX bluetooth */
685 pCap->halBtCoexSupport = AH_TRUE;
686#endif
687 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
688#if 0
689 pCap->hal4kbSplitTransSupport = AH_FALSE;
690#endif
691 pCap->halRxStbcSupport = 1;
692 pCap->halTxStbcSupport = 1;
693
694 return AH_TRUE;
695}
696
697HAL_BOOL
698ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
699{
700#define ANTENNA0_CHAINMASK 0x1
701#define ANTENNA1_CHAINMASK 0x2
702 struct ath_hal_5416 *ahp = AH5416(ah);
703
704 /* Antenna selection is done by setting the tx/rx chainmasks approp. */
705 switch (settings) {
706 case HAL_ANT_FIXED_A:
707 /* Enable first antenna only */
708 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
709 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
710 break;
711 case HAL_ANT_FIXED_B:
712 /* Enable second antenna only, after checking capability */
713 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
714 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
715 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
716 break;
717 case HAL_ANT_VARIABLE:
718 /* Restore original chainmask settings */
719 /* XXX */
720 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
721 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
722 break;
723 }
724 return AH_TRUE;
725#undef ANTENNA0_CHAINMASK
726#undef ANTENNA1_CHAINMASK
727}
728
729static const char*
730ar9280Probe(uint16_t vendorid, uint16_t devid)
731{
732 if (vendorid == ATHEROS_VENDOR_ID &&
733 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
734 return "Atheros 9280";
735 return AH_NULL;
736}
737AH_CHIP(AR9280, ar9280Probe, ar9280Attach);
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