ata-dma.c (64027) | ata-dma.c (64307) |
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1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 64027 2000-07-30 17:54:34Z steve $ | 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 64307 2000-08-06 19:51:58Z sos $ |
29 */ 30 31#include "pci.h" 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> --- 6 unchanged lines hidden (view full) --- 43#endif 44#include <dev/ata/ata-all.h> 45#include <dev/ata/ata-disk.h> 46 47#if NPCI > 0 48 49/* prototypes */ 50static void promise_timing(struct ata_softc *, int32_t, int32_t); | 29 */ 30 31#include "pci.h" 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> --- 6 unchanged lines hidden (view full) --- 43#endif 44#include <dev/ata/ata-all.h> 45#include <dev/ata/ata-disk.h> 46 47#if NPCI > 0 48 49/* prototypes */ 50static void promise_timing(struct ata_softc *, int32_t, int32_t); |
51static void hpt366_timing(struct ata_softc *, int32_t, int32_t); | 51static void hpt_timing(struct ata_softc *, int32_t, int32_t); |
52 53/* misc defines */ 54#ifdef __alpha__ 55#undef vtophys 56#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 57#endif 58 59void 60ata_dmainit(struct ata_softc *scp, int32_t device, 61 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 62{ 63 device_t parent = device_get_parent(scp->dev); | 52 53/* misc defines */ 54#ifdef __alpha__ 55#undef vtophys 56#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 57#endif 58 59void 60ata_dmainit(struct ata_softc *scp, int32_t device, 61 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 62{ 63 device_t parent = device_get_parent(scp->dev); |
64 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 65 int32_t error; | 64 int devno = (scp->unit << 1) + ATA_DEV(device); 65 int error; |
66 67 /* set our most pessimistic default mode */ 68 scp->mode[ATA_DEV(device)] = ATA_PIO; 69 70 if (!scp->bmaddr) 71 return; 72 73 /* if simplex controller, only allow DMA on primary channel */ --- 22 unchanged lines hidden (view full) --- 96 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 97 ata_printf(scp, device, 98 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 99 udmamode = 2; 100 } 101 102 switch (scp->chiptype) { 103 | 66 67 /* set our most pessimistic default mode */ 68 scp->mode[ATA_DEV(device)] = ATA_PIO; 69 70 if (!scp->bmaddr) 71 return; 72 73 /* if simplex controller, only allow DMA on primary channel */ --- 22 unchanged lines hidden (view full) --- 96 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 97 ata_printf(scp, device, 98 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 99 udmamode = 2; 100 } 101 102 switch (scp->chiptype) { 103 |
104 case 0x244b8086: /* Intel ICH2 */ 105 if (udmamode >= 5) { 106 int32_t mask48, new48; 107 int16_t word54; 108 109 word54 = pci_read_config(parent, 0x54, 2); 110 if (word54 & (0x10 << devno)) { 111 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 112 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 113 if (bootverbose) 114 ata_printf(scp, device, 115 "%s setting up UDMA5 mode on ICH2 chip\n", 116 (error) ? "failed" : "success"); 117 if (!error) { 118 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 119 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 120 pci_write_config(parent, 0x48, 121 (pci_read_config(parent, 0x48, 4) & 122 ~mask48) | new48, 4); 123 pci_write_config(parent, 0x54, word54 & ~(0x1000<<devno),2); 124 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 125 return; 126 } 127 } 128 } 129 if (udmamode >= 4) { 130 int16_t word54; 131 132 word54 = pci_read_config(parent, 0x54, 2); 133 pci_write_config(parent, 0x54, word54 & ~(0x1000 << devno), 2); 134 } 135 /* FALLTHROUGH */ 136 |
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104 case 0x24118086: /* Intel ICH */ 105 if (udmamode >= 4) { 106 int32_t mask48, new48; 107 int16_t word54; 108 109 word54 = pci_read_config(parent, 0x54, 2); 110 if (word54 & (0x10 << devno)) { 111 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 112 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 113 if (bootverbose) 114 ata_printf(scp, device, | 137 case 0x24118086: /* Intel ICH */ 138 if (udmamode >= 4) { 139 int32_t mask48, new48; 140 int16_t word54; 141 142 word54 = pci_read_config(parent, 0x54, 2); 143 if (word54 & (0x10 << devno)) { 144 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 145 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 146 if (bootverbose) 147 ata_printf(scp, device, |
115 "%s setting up UDMA4 mode on ICH chip\n", 116 (error) ? "failed" : "success"); | 148 "%s setting up UDMA4 mode on ICH%s chip\n", 149 (error) ? "failed" : "success", 150 (scp->chiptype == 0x244b8086) ? "2" : ""); |
117 if (!error) { 118 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 119 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 120 pci_write_config(parent, 0x48, 121 (pci_read_config(parent, 0x48, 4) & 122 ~mask48) | new48, 4); 123 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 124 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 125 return; 126 } 127 } 128 } | 151 if (!error) { 152 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 153 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 154 pci_write_config(parent, 0x48, 155 (pci_read_config(parent, 0x48, 4) & 156 ~mask48) | new48, 4); 157 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 158 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 159 return; 160 } 161 } 162 } |
163 if (udmamode >= 2) { 164 int16_t word54; 165 166 word54 = pci_read_config(parent, 0x54, 2); 167 pci_write_config(parent, 0x54, word54 & ~(1 << devno), 2); 168 } |
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129 /* FALLTHROUGH */ 130 131 case 0x71118086: /* Intel PIIX4 */ 132 case 0x71998086: /* Intel PIIX4e */ 133 case 0x24218086: /* Intel ICH0 */ 134 if (udmamode >= 2) { 135 int32_t mask48, new48; 136 137 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 138 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 139 if (bootverbose) 140 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 141 (error) ? "failed" : "success", | 169 /* FALLTHROUGH */ 170 171 case 0x71118086: /* Intel PIIX4 */ 172 case 0x71998086: /* Intel PIIX4e */ 173 case 0x24218086: /* Intel ICH0 */ 174 if (udmamode >= 2) { 175 int32_t mask48, new48; 176 177 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 178 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 179 if (bootverbose) 180 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 181 (error) ? "failed" : "success", |
142 (scp->chiptype == 0x24118086) ? "ICH" : 143 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); | 182 (scp->chiptype == 0x244b8086) ? "ICH2" : 183 (scp->chiptype == 0x24118086) ? "ICH" : 184 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); |
144 if (!error) { 145 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 146 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 147 pci_write_config(parent, 0x48, 148 (pci_read_config(parent, 0x48, 4) & 149 ~mask48) | new48, 4); 150 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 151 return; --- 21 unchanged lines hidden (view full) --- 173 pci_write_config(parent, 0x40, new40, 4); 174 pci_write_config(parent, 0x44, new44, 4); 175 } 176 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 177 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 178 if (bootverbose) 179 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 180 (error) ? "failed" : "success", | 185 if (!error) { 186 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 187 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 188 pci_write_config(parent, 0x48, 189 (pci_read_config(parent, 0x48, 4) & 190 ~mask48) | new48, 4); 191 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 192 return; --- 21 unchanged lines hidden (view full) --- 214 pci_write_config(parent, 0x40, new40, 4); 215 pci_write_config(parent, 0x44, new44, 4); 216 } 217 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 218 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 219 if (bootverbose) 220 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 221 (error) ? "failed" : "success", |
181 (scp->chiptype == 0x70108086) ? "PIIX3" : | 222 (scp->chiptype == 0x244b8086) ? "ICH2" : |
182 (scp->chiptype == 0x24118086) ? "ICH" : | 223 (scp->chiptype == 0x24118086) ? "ICH" : |
183 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); | 224 (scp->chiptype == 0x24218086) ? "ICH0" : 225 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); |
184 if (!error) { 185 if (device == ATA_MASTER) { 186 mask40 = 0x0000330f; 187 new40 = 0x00002307; 188 mask44 = 0; 189 new44 = 0; 190 } 191 else { --- 247 unchanged lines hidden (view full) --- 439 return; 440 } 441 } 442 /* we could set PIO mode timings, but we assume the BIOS did that */ 443 break; 444 445 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 446 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ | 226 if (!error) { 227 if (device == ATA_MASTER) { 228 mask40 = 0x0000330f; 229 new40 = 0x00002307; 230 mask44 = 0; 231 new44 = 0; 232 } 233 else { --- 247 unchanged lines hidden (view full) --- 481 return; 482 } 483 } 484 /* we could set PIO mode timings, but we assume the BIOS did that */ 485 break; 486 487 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 488 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ |
489 case 0x4d30105a: /* Promise Ultra100 / FastTrak100 controllers */ |
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447 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 448 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 449 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 450 break; 451 | 490 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 491 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 492 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 493 break; 494 |
452 if (udmamode >=4 && scp->chiptype == 0x4d38105a && | 495 if (udmamode >=5 && scp->chiptype == 0x4d30105a && |
453 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 454 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, | 496 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 497 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, |
498 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 499 if (bootverbose) 500 ata_printf(scp, device, 501 "%s setting up UDMA5 mode on Promise chip\n", 502 (error) ? "failed" : "success"); 503 if (!error) { 504 promise_timing(scp, devno, ATA_UDMA5); 505 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 506 return; 507 } 508 } 509 if (udmamode >=4 && 510 (scp->chiptype == 0x4d38105a || scp->chiptype == 0x4d30105a) && 511 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 512 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, |
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455 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 456 if (bootverbose) 457 ata_printf(scp, device, 458 "%s setting up UDMA4 mode on Promise chip\n", 459 (error) ? "failed" : "success"); 460 if (!error) { 461 promise_timing(scp, devno, ATA_UDMA4); 462 scp->mode[ATA_DEV(device)] = ATA_UDMA4; --- 33 unchanged lines hidden (view full) --- 496 ata_printf(scp, device, 497 "%s setting up PIO%d mode on Promise chip\n", 498 (error) ? "failed" : "success", 499 (apiomode >= 0) ? apiomode : 0); 500 promise_timing(scp, devno, ata_pio2mode(apiomode)); 501 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 502 return; 503 | 513 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 514 if (bootverbose) 515 ata_printf(scp, device, 516 "%s setting up UDMA4 mode on Promise chip\n", 517 (error) ? "failed" : "success"); 518 if (!error) { 519 promise_timing(scp, devno, ATA_UDMA4); 520 scp->mode[ATA_DEV(device)] = ATA_UDMA4; --- 33 unchanged lines hidden (view full) --- 554 ata_printf(scp, device, 555 "%s setting up PIO%d mode on Promise chip\n", 556 (error) ? "failed" : "success", 557 (apiomode >= 0) ? apiomode : 0); 558 promise_timing(scp, devno, ata_pio2mode(apiomode)); 559 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 560 return; 561 |
504 case 0x00041103: /* HighPoint HPT366 controller */ | 562 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ |
505 /* no ATAPI devices for now */ 506 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 507 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 508 break; 509 | 563 /* no ATAPI devices for now */ 564 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 565 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 566 break; 567 |
510 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) { | 568 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 569 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { |
511 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, | 570 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, |
571 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 572 if (bootverbose) 573 ata_printf(scp, device, 574 "%s setting up UDMA5 mode on HPT370 chip\n", 575 (error) ? "failed" : "success"); 576 if (!error) { 577 hpt_timing(scp, devno, ATA_UDMA5); 578 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 579 return; 580 } 581 } 582 583 if (udmamode >=4 && 584 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 585 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, |
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512 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 513 if (bootverbose) 514 ata_printf(scp, device, 515 "%s setting up UDMA4 mode on HPT366 chip\n", 516 (error) ? "failed" : "success"); 517 if (!error) { | 586 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 587 if (bootverbose) 588 ata_printf(scp, device, 589 "%s setting up UDMA4 mode on HPT366 chip\n", 590 (error) ? "failed" : "success"); 591 if (!error) { |
518 hpt366_timing(scp, devno, ATA_UDMA4); | 592 hpt_timing(scp, devno, ATA_UDMA4); |
519 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 520 return; 521 } 522 } 523 if (udmamode >= 2) { 524 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 525 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 526 if (bootverbose) 527 ata_printf(scp, device, 528 "%s setting up UDMA2 mode on HPT366 chip\n", 529 (error) ? "failed" : "success"); 530 if (!error) { | 593 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 594 return; 595 } 596 } 597 if (udmamode >= 2) { 598 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 599 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 600 if (bootverbose) 601 ata_printf(scp, device, 602 "%s setting up UDMA2 mode on HPT366 chip\n", 603 (error) ? "failed" : "success"); 604 if (!error) { |
531 hpt366_timing(scp, devno, ATA_UDMA2); | 605 hpt_timing(scp, devno, ATA_UDMA2); |
532 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 533 return; 534 } 535 } 536 if (wdmamode >= 2 && apiomode >= 4) { 537 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 538 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 539 if (bootverbose) 540 ata_printf(scp, device, 541 "%s setting up WDMA2 mode on HPT366 chip\n", 542 (error) ? "failed" : "success"); 543 if (!error) { | 606 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 607 return; 608 } 609 } 610 if (wdmamode >= 2 && apiomode >= 4) { 611 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 613 if (bootverbose) 614 ata_printf(scp, device, 615 "%s setting up WDMA2 mode on HPT366 chip\n", 616 (error) ? "failed" : "success"); 617 if (!error) { |
544 hpt366_timing(scp, devno, ATA_WDMA2); | 618 hpt_timing(scp, devno, ATA_WDMA2); |
545 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 546 return; 547 } 548 } 549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 550 ata_pio2mode(apiomode), 551 ATA_C_F_SETXFER, ATA_WAIT_READY); 552 if (bootverbose) 553 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 554 (error) ? "failed" : "success", 555 (apiomode >= 0) ? apiomode : 0); | 619 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 620 return; 621 } 622 } 623 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 624 ata_pio2mode(apiomode), 625 ATA_C_F_SETXFER, ATA_WAIT_READY); 626 if (bootverbose) 627 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 628 (error) ? "failed" : "success", 629 (apiomode >= 0) ? apiomode : 0); |
556 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); | 630 hpt_timing(scp, devno, ata_pio2mode(apiomode)); |
557 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 558 return; 559 560 default: /* unknown controller chip */ 561 /* better not try generic DMA on ATAPI devices it almost never works */ 562 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 563 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 564 break; --- 37 unchanged lines hidden (view full) --- 602} 603 604int32_t 605ata_dmasetup(struct ata_softc *scp, int32_t device, 606 int8_t *data, int32_t count, int32_t flags) 607{ 608 struct ata_dmaentry *dmatab; 609 u_int32_t dma_count, dma_base; | 631 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 632 return; 633 634 default: /* unknown controller chip */ 635 /* better not try generic DMA on ATAPI devices it almost never works */ 636 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 637 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 638 break; --- 37 unchanged lines hidden (view full) --- 676} 677 678int32_t 679ata_dmasetup(struct ata_softc *scp, int32_t device, 680 int8_t *data, int32_t count, int32_t flags) 681{ 682 struct ata_dmaentry *dmatab; 683 u_int32_t dma_count, dma_base; |
610 int32_t i = 0; | 684 int i = 0; |
611 612 if (((uintptr_t)data & 1) || (count & 1)) 613 return -1; 614 615 if (!count) { 616 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 617 return -1; 618 } --- 84 unchanged lines hidden (view full) --- 703 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 704 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 705 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 706 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 707 } 708 break; 709 710 case 0x4d38105a: /* Promise 66's */ | 685 686 if (((uintptr_t)data & 1) || (count & 1)) 687 return -1; 688 689 if (!count) { 690 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 691 return -1; 692 } --- 84 unchanged lines hidden (view full) --- 777 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 778 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 779 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 780 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 781 } 782 break; 783 784 case 0x4d38105a: /* Promise 66's */ |
785 case 0x4d30105a: /* Promise 100's */ |
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711 switch (mode) { 712 default: 713 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 714 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 715 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 716 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 717 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 718 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 719 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 720 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; | 786 switch (mode) { 787 default: 788 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 789 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 790 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 791 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 792 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 793 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 794 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 795 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; |
796 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; |
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721 } 722 break; 723 } 724 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 725} 726 727static void | 797 } 798 break; 799 } 800 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 801} 802 803static void |
728hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) | 804hpt_timing(struct ata_softc *scp, int32_t devno, int32_t mode) |
729{ 730 device_t parent = device_get_parent(scp->dev); 731 u_int32_t timing; 732 | 805{ 806 device_t parent = device_get_parent(scp->dev); 807 u_int32_t timing; 808 |
733 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 734 case 0x85: /* 25Mhz */ | 809 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ |
735 switch (mode) { | 810 switch (mode) { |
736 case ATA_PIO0: timing = 0xc0d08585; break; 737 case ATA_PIO1: timing = 0xc0d08572; break; 738 case ATA_PIO2: timing = 0xc0ca8542; break; 739 case ATA_PIO3: timing = 0xc0ca8532; break; 740 case ATA_PIO4: timing = 0xc0ca8521; break; 741 case ATA_WDMA2: timing = 0xa0ca8521; break; 742 case ATA_UDMA2: timing = 0x90cf8521; break; 743 case ATA_UDMA4: timing = 0x90c98521; break; 744 default: timing = 0x01208585; | 811 case ATA_PIO0: timing = 0x06914e57; break; 812 case ATA_PIO1: timing = 0x06914e43; break; 813 case ATA_PIO2: timing = 0x06514e33; break; 814 case ATA_PIO3: timing = 0x06514e22; break; 815 case ATA_PIO4: timing = 0x06514e21; break; 816 case ATA_WDMA2: timing = 0x26514e21; break; 817 case ATA_UDMA2: timing = 0x16494e31; break; 818 case ATA_UDMA4: timing = 0x16454e31; break; 819 case ATA_UDMA5: timing = 0x16454e31; break; 820 default: timing = 0x06514e57; |
745 } | 821 } |
746 break; 747 default: 748 case 0xa7: /* 33MHz */ 749 switch (mode) { 750 case ATA_PIO0: timing = 0xc0d0a7aa; break; 751 case ATA_PIO1: timing = 0xc0d0a7a3; break; 752 case ATA_PIO2: timing = 0xc0d0a753; break; 753 case ATA_PIO3: timing = 0xc0c8a742; break; 754 case ATA_PIO4: timing = 0xc0c8a731; break; 755 case ATA_WDMA2: timing = 0xa0c8a731; break; 756 case ATA_UDMA2: timing = 0x90caa731; break; 757 case ATA_UDMA4: timing = 0x90c9a731; break; 758 default: timing = 0x0120a7a7; | 822 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 823 pci_write_config(parent, 0x5b, 0x22, 1); 824 } 825 else { /* HPT36[68] */ 826 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 827 case 0x85: /* 25Mhz */ 828 switch (mode) { 829 case ATA_PIO0: timing = 0xc0d08585; break; 830 case ATA_PIO1: timing = 0xc0d08572; break; 831 case ATA_PIO2: timing = 0xc0ca8542; break; 832 case ATA_PIO3: timing = 0xc0ca8532; break; 833 case ATA_PIO4: timing = 0xc0ca8521; break; 834 case ATA_WDMA2: timing = 0xa0ca8521; break; 835 case ATA_UDMA2: timing = 0x90cf8521; break; 836 case ATA_UDMA4: timing = 0x90c98521; break; 837 default: timing = 0x01208585; 838 } 839 break; 840 default: 841 case 0xa7: /* 33MHz */ 842 switch (mode) { 843 case ATA_PIO0: timing = 0xc0d0a7aa; break; 844 case ATA_PIO1: timing = 0xc0d0a7a3; break; 845 case ATA_PIO2: timing = 0xc0d0a753; break; 846 case ATA_PIO3: timing = 0xc0c8a742; break; 847 case ATA_PIO4: timing = 0xc0c8a731; break; 848 case ATA_WDMA2: timing = 0xa0c8a731; break; 849 case ATA_UDMA2: timing = 0x90caa731; break; 850 case ATA_UDMA4: timing = 0x90c9a731; break; 851 default: timing = 0x0120a7a7; 852 } 853 break; 854 case 0xd9: /* 40Mhz */ 855 switch (mode) { 856 case ATA_PIO0: timing = 0xc018d9d9; break; 857 case ATA_PIO1: timing = 0xc010d9c7; break; 858 case ATA_PIO2: timing = 0xc010d997; break; 859 case ATA_PIO3: timing = 0xc010d974; break; 860 case ATA_PIO4: timing = 0xc008d963; break; 861 case ATA_WDMA2: timing = 0xa008d943; break; 862 case ATA_UDMA2: timing = 0x900bd943; break; 863 case ATA_UDMA4: timing = 0x900fd943; break; 864 default: timing = 0x0120d9d9; 865 } |
759 } | 866 } |
760 break; 761 case 0xd9: /* 40Mhz */ 762 switch (mode) { 763 case ATA_PIO0: timing = 0xc018d9d9; break; 764 case ATA_PIO1: timing = 0xc010d9c7; break; 765 case ATA_PIO2: timing = 0xc010d997; break; 766 case ATA_PIO3: timing = 0xc010d974; break; 767 case ATA_PIO4: timing = 0xc008d963; break; 768 case ATA_WDMA2: timing = 0xa008d943; break; 769 case ATA_UDMA2: timing = 0x900bd943; break; 770 case ATA_UDMA4: timing = 0x900fd943; break; 771 default: timing = 0x0120d9d9; 772 } | 867 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); |
773 } | 868 } |
774 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4); | |
775} 776 777#else /* NPCI > 0 */ 778 779void 780ata_dmainit(struct ata_softc *scp, int32_t device, 781 int32_t piomode, int32_t wdmamode, int32_t udmamode) 782{ --- 27 unchanged lines hidden --- | 869} 870 871#else /* NPCI > 0 */ 872 873void 874ata_dmainit(struct ata_softc *scp, int32_t device, 875 int32_t piomode, int32_t wdmamode, int32_t udmamode) 876{ --- 27 unchanged lines hidden --- |