1/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */
2
3/*-
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
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29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 * $FreeBSD: head/sys/arm/xscale/i80321/i80321reg.h 139735 2005-01-05 21:58:49Z imp $
38 *
39 */
40
41#ifndef _ARM_XSCALE_I80321REG_H_
42#define _ARM_XSCALE_I80321REG_H_
43
44/*
45 * Register definitions for the Intel 80321 (``Verde'') I/O processor,
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86#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00)
87#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40)
88#define VERDE_DMA_SIZE 0x0100
89#define VERDE_DMA_CHSIZE 0x0040
90
91#define VERDE_MCU_BASE 0x0500
92#define VERDE_MCU_SIZE 0x0100
93
94#define VERDE_SSP_BASE 0x0600
95#define VERDE_SSP_SIZE 0x0080
96
97#define VERDE_PBIU_BASE 0x0680
98#define VERDE_PBIU_SIZE 0x0080
99
100#define VERDE_AAU_BASE 0x0800
101#define VERDE_AAU_SIZE 0x0100
102
103#define VERDE_I2C_BASE 0x1680
104#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)
105#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20)
106#define VERDE_I2C_SIZE 0x0080
107#define VERDE_I2C_CHSIZE 0x0020
108
109/*
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330/*
331 * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE
332 * INTERRUPTS. See i80321_icu.c
333 */
334#define ICU_INT_HPI 31 /* high priority interrupt */
335#define ICU_INT_XINT0 27 /* external interrupts */
336#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0)
337#define ICU_INT_bit26 26
338#define ICU_INT_SSP 25 /* SSP serial port */
339#define ICU_INT_MUE 24 /* msg unit error */
340#define ICU_INT_AAUE 23 /* AAU error */
341#define ICU_INT_bit22 22
342#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */
343#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */
344#define ICU_INT_MCUE 19 /* memory controller error */
345#define ICU_INT_ATUE 18 /* ATU error */
346#define ICU_INT_BIUE 17 /* bus interface unit error */
347#define ICU_INT_PMU 16 /* XScale PMU */
348#define ICU_INT_PPM 15 /* peripheral PMU */
349#define ICU_INT_BIST 14 /* ATU Start BIST */
350#define ICU_INT_MU 13 /* messaging unit */
351#define ICU_INT_I2C1 12 /* i2c unit 1 */
352#define ICU_INT_I2C0 11 /* i2c unit 0 */
353#define ICU_INT_TMR1 10 /* timer 1 */
354#define ICU_INT_TMR0 9 /* timer 0 */
355#define ICU_INT_CPPM 8 /* core processor PMU */
356#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
357#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
358#define ICU_INT_bit5 5
359#define ICU_INT_bit4 4
360#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */
361#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */
362#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */
363#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */
364
365#define ICU_INT_HWMASK (0xffffffff & \
366 ~((1 << ICU_INT_bit26) | \
367 (1 << ICU_INT_bit22) | \
368 (1 << ICU_INT_bit5) | \
369 (1 << ICU_INT_bit4)))
370
371/*
372 * SSP Serial Port
373 */
374
375#define SSP_SSCR0 0x00 /* SSC control 0 */
376#define SSP_SSCR1 0x04 /* SSC control 1 */
377#define SSP_SSSR 0x08 /* SSP status */
378#define SSP_SSITR 0x0c /* SSP interrupt test */
379#define SSP_SSDR 0x10 /* SSP data */
380
381#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */
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416#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */
417#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */
418#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */
419
420#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */
421#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */
422#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */
423
424/*
425 * Peripheral Bus Interface Unit
426 */
427
428#define PBIU_PBCR 0x00 /* PBIU Control Register */
429#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */
430#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */
431#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */
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2
3/*-
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
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29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 * $FreeBSD: head/sys/arm/xscale/i80321/i80321reg.h 139735 2005-01-05 21:58:49Z imp $
38 *
39 */
40
41#ifndef _ARM_XSCALE_I80321REG_H_
42#define _ARM_XSCALE_I80321REG_H_
43
44/*
45 * Register definitions for the Intel 80321 (``Verde'') I/O processor,
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86#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00)
87#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40)
88#define VERDE_DMA_SIZE 0x0100
89#define VERDE_DMA_CHSIZE 0x0040
90
91#define VERDE_MCU_BASE 0x0500
92#define VERDE_MCU_SIZE 0x0100
93
94#define VERDE_SSP_BASE 0x0600
95#define VERDE_SSP_SIZE 0x0080
96
97#define VERDE_PBIU_BASE 0x0680
98#define VERDE_PBIU_SIZE 0x0080
99
100#define VERDE_AAU_BASE 0x0800
101#define VERDE_AAU_SIZE 0x0100
102
103#define VERDE_I2C_BASE 0x1680
104#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)
105#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20)
106#define VERDE_I2C_SIZE 0x0080
107#define VERDE_I2C_CHSIZE 0x0020
108
109/*
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330/*
331 * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE
332 * INTERRUPTS. See i80321_icu.c
333 */
334#define ICU_INT_HPI 31 /* high priority interrupt */
335#define ICU_INT_XINT0 27 /* external interrupts */
336#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0)
337#define ICU_INT_bit26 26
338#define ICU_INT_SSP 25 /* SSP serial port */
339#define ICU_INT_MUE 24 /* msg unit error */
340#define ICU_INT_AAUE 23 /* AAU error */
341#define ICU_INT_bit22 22
342#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */
343#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */
344#define ICU_INT_MCUE 19 /* memory controller error */
345#define ICU_INT_ATUE 18 /* ATU error */
346#define ICU_INT_BIUE 17 /* bus interface unit error */
347#define ICU_INT_PMU 16 /* XScale PMU */
348#define ICU_INT_PPM 15 /* peripheral PMU */
349#define ICU_INT_BIST 14 /* ATU Start BIST */
350#define ICU_INT_MU 13 /* messaging unit */
351#define ICU_INT_I2C1 12 /* i2c unit 1 */
352#define ICU_INT_I2C0 11 /* i2c unit 0 */
353#define ICU_INT_TMR1 10 /* timer 1 */
354#define ICU_INT_TMR0 9 /* timer 0 */
355#define ICU_INT_CPPM 8 /* core processor PMU */
356#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
357#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
358#define ICU_INT_bit5 5
359#define ICU_INT_bit4 4
360#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */
361#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */
362#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */
363#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */
364
365#define ICU_INT_HWMASK (0xffffffff & \
366 ~((1 << ICU_INT_bit26) | \
367 (1 << ICU_INT_bit22) | \
368 (1 << ICU_INT_bit5) | \
369 (1 << ICU_INT_bit4)))
370
371/*
372 * SSP Serial Port
373 */
374
375#define SSP_SSCR0 0x00 /* SSC control 0 */
376#define SSP_SSCR1 0x04 /* SSC control 1 */
377#define SSP_SSSR 0x08 /* SSP status */
378#define SSP_SSITR 0x0c /* SSP interrupt test */
379#define SSP_SSDR 0x10 /* SSP data */
380
381#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */
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416#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */
417#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */
418#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */
419
420#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */
421#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */
422#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */
423
424/*
425 * Peripheral Bus Interface Unit
426 */
427
428#define PBIU_PBCR 0x00 /* PBIU Control Register */
429#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */
430#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */
431#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */
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